Vishay SST421NL, SST423NL Schematic [ru]

SST421NL/423NL

Vishay Siliconix

Monolithic N-Channel JFET Duals

PRODUCT SUMMARY

Part Number V

SST421NL −0.4 to−2 −40 0.3 10

SST423NL −0.4 to −2 −40 0.3 25

FEATURES BENEFITS APPLICATIONS

D Anti Latchup Capability
D Monolithic Design
D High Slew Rate
D Low Offset/Drift Voltage
D Low Gate Leakage: 0.6 pA
D Low Noise
D High CMRR: 102 dB

GS(off)

(V) V

(BR)GSS

Min (V) gfs Min (mS) V

GS1

− V

GS2

D External Substrate Bias—Avoids Latchup
D Tight Differential Match vs. Current
D Improved Op Amp Speed, Settling Time Accuracy
D Minimum Input Error/Trimming Requirement
D Insignificant Signal Loss/Error Voltage
D High System Sensitivity
D Minimum Error with Large Input Signals

 Max (mV)

D Ultralow Input Current

Differential Amps

D High-Speed Comparators
D Impedance Converters

DESCRIPTION

The SST421NL/423NL are monolithic dual n-channel JFETs
designed to provide very high input impedance for differential
amplification and impedance matching. Among its many
unique features, this series offers low operating gate current.

Pins 4 and 8 on SST421NL/423NL part numbers enable the
substrate to be connected to a positive polarity, external bias

) to avoid latchup.

(V

DD

Narrow Body SOIC

S

1

1

D

2

1

G

3

1

SUBSTRATE S

4

Top View

Marking Codes:

SST421NL − (421NL)

SST423NL − (423NL)

ABSOLUTE MAXIMUM RATINGS

The SO-8 package provides ease of manufacturing, and the
symmetrical pinout prevents improper orientation. The SO-8
package is available with tape-and-reel options for
compatibility with automatic assembly methods.

Similar versions of these part numbers are available in the
hermetically sealed TO-78 package. Full military processing
is available. See data sheets for part numbers U421/423.

SUBSTRATE

8

G

7

2

D

6

2

5

2

Gate-Drain, Gate-Source Voltage −40 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Gate-Gate Voltage "40 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Gate Current 10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead Temperature (

Storage Temperature −65 to 200_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating Junction Temperature −55 to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . .

Document Number: 72060
S-40391—Rev. B, 15-Mar-04

1

/16” from case for 10 sec.) 300 _C. . . . . . . . . . . . . . . . . .

Power Dissipation : Per Side

Notes
a. Derate 2.4 mW/_C above 25_C
b. Derate 4 mW/_C above 25_C

Total

b

a

300 mW. . . . . . . . . . . . . . . . . . . . . . . .

500 mW. . . . . . . . . . . . . . . . . . . . . . . . . . .

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1

SST421NL/423NL

VDS = 10 V, VGS = 0 V, f = 1 kH

Vishay Siliconix

SPECIFICATIONS (TA = 25_C UNLESS OTHERWISE NOTED)

Limits

SST421NL SST423NL

Parameter

Symbol

Specific Test Conditions Ty p

a

Min Max Min Max

Unit

Static

Gate-Source
Breakdown Voltage

Gate-Gate
Breakdown Voltage

Gate-Source
Cutoff Voltage

Saturation Drain Current I

Gate Reverse Current I

Gate Operating Current I

Drain-Source
On-Resistance

Gate-Source Voltage V

Gate-Source
Forward Voltage

V

(BR)GSS

V

(BR)G1 − G2

V

GS(off)

DSS

GSS

G

r

DS(on)

GS

V

GS(F)

IG = −1 A, VDS = 0 V

IG = "1 A, ID = 0, IS = 0

VDS = 10 V, ID = 1 nA −1.2 −0.4 −2 −0.4 −2

VDS = 10 V, VGS = 0 V 400 60 1000 60 1000

VGS = −20 V, VDS = 0 V −0.6 −50 −50 pA

TA = 125_C

VDG = 10 V, ID = 30 A

VGS = 0 V, ID = 10 A

VDG = 10 V, ID = 30 A

IG = 1 mA , VDS = 0 V 0.7

−60 −40 −40

"55 "40 "40 V

−0.3 −50 −50 nA

−1.0 pA

2000

−0.8 −1.8 −1.8

A



V

Dynamic

Common-Source Forward
Transconductance

Common-Source
Output Conductance

Common-Source Forward
Transconductance

Common-Source
Output Conductance

Common-Source
Input Capacitance

Common-Source
Reverse Transfer
Capacitance

Equivalent Input
Noise Voltage

g

fs

g

os

g

fs

g

os

C

iss

C

rss

e

n

VDS = 10 V, ID = 30 A , f = 1 kHz

VDS = 10 V, VGS = 0 V, f = 1 MHz

VDS = 10 V, ID = 30 A , f = 10 Hz

z

0.6 0.3 1.5 0.3 1.5 mS

4 10 10

0.2 0.12 0.35 0.12 0.35 mS

0.4 3 3

1.4 3 3

0.7 1.5 1.5

30

S

S

pF

nV⁄

√Hz

Matching

Differential
Gate-Source Voltage

Gate-Source Voltage
Differential Change
with Temperature

Common Mode
Rejection Ratio

Notes
a. Typical values are for DESIGN AID ONLY, not guaranteed or subject to production testing. NNT

Ť

V

GS1–VGS2

ŤV

GS1–VGS2

T

CMRR

Ť

Ť

VDG = 10 V, ID = 30 A

VDG = 10 V, ID = 30 A

T

= −55 to 125_C

A

VDG = 10 to 20 V, ID = 30 A

102 90 80 dB

10 25 mV

10 40

V/_C

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2

Document Number: 72060

S-40391—Rev. B, 15-Mar-04