New Product
N-Channel 12-V (D-S) MOSFET
SiR492DP
Vishay Siliconix
PRODUCT SUMMARY
VDS (V) R
12
0.0038 at V
0.0047 at V
PowerPAK SO-8
DS(on)
(Ω)
GS
GS
= 4.5 V
= 2.5 V
e
I
(A)
D
40
40
Qg (Typ.)
41 nC
FEATURES
• Halogen-free
• TrenchFET
• Low Thermal Resistance PowerPAK
Package with Small Size and Low 1.07 mm Profile
• 100 % R
®
Power MOSFET
Tested
g
®
APPLICATIONS
• Secondary Synchronous Rectification
RoHS
COMPLIANT
• Point-of-Load
6.15 mm
D
8
D
7
D
6
5
Bottom View
Ordering Information: SiR492DP-T1-GE3 (Lead (Pb)-free and Halogen-free)
S
1
D
5.15 mm
S
2
S
3
G
4
• Load Switch
D
G
S
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter Symbol Limit Unit
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current (T
= 150 °C)
J
= 25 °C
T
C
T
= 70 °C
C
TA = 25 °C
V
DS
V
GS
I
D
TA = 70 °C
Pulsed Drain Current
Continuous Source-Drain Diode Current
Maximum Power Dissipation
= 25 °C
T
C
= 25 °C
T
A
T
= 25 °C
C
T
= 70 °C
C
T
= 25 °C
A
I
DM
I
S
P
D
TA = 70 °C
, T
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
c, d
T
J
stg
Notes:
a. Surface Mounted on 1" x 1" FR4 board.
b. t = 10 s.
c. See Solder Profile (
http://www.vishay.com/ppg?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and
is not required to ensure adequate bottom side solder interconnection.
d. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
e. Package limited, pulse time ≤ 200 ms.
12
± 8
e
40
e
35
a, b
27
a, b
21.6
60
30
a, b
3.5
36
23
a, b
4.2
a, b
2.7
- 50 to 150
260
V
A
W
°C
Document Number: 68840
S-82288-Rev. B, 22-Sep-08
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1
New Product
SiR492DP
Vishay Siliconix
THERMAL RESISTANCE RATINGS
Parameter Symbol Typical Maximum Unit
Maximum Junction-to-Ambient
a, b
t ≤ 10 s
Maximum Junction-to-Case (Drain) Steady State
Notes:
a. Surface Mounted on 1" x 1" FR4 board.
b. Maximum under Steady State conditions is 70 °C/W.
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter Symbol Test Conditions Min. Typ. Max. Unit
Static
Drain-Source Breakdown Voltage
V
Temperature Coefficient ΔVDS/T
DS
V
Temperature Coefficient ΔV
GS(th)
Gate-Source Threshold Voltage
Gate-Source Leakage
Zero Gate Voltage Drain Current
On-State Drain Current
Drain-Source On-State Resistance
Forward Transconductance
Dynamic
b
a
a
a
Input Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
Tur n -O n De l ay T i m e
Rise Time
Turn-Off Delay Time
Fall Time
Tur n -O n De l ay T i m e
Rise Time
Turn-Off Delay Time
Fall Time
V
DS
J
GS(th)/TJ
V
GS(th)
I
GSS
I
DSS
I
V
D(on)
R
DS(on)
g
fs
C
iss
C
oss
C
rss
Q
g
Q
gs
Q
gd
R
g
t
d(on)
t
r
t
d(off)
t
f
t
d(on)
t
r
t
d(off)
t
f
VGS = 0 V, ID = 250 µA
V
= VGS, ID = 250 µA
DS
VDS = 0 V, VGS = ± 8 V
V
DS
V
= 12 V, V
DS
DS
V
GS
V
GS
VDS = 5 V, ID = 15 A
VDS = 6 V, V
VDS = 6 V, V
= 6 V, V
V
DS
V
DD
≅ 5 A, V
I
D
V
DD
I
≅ 5 A, V
D
R
R
thJA
thJC
25 30
2.9 3.5
°C/W
12 V
ID = 250 µA
12
- 3.1
0.4 1.0 V
± 100 nA
= 12 V, V
GS
≥ 5 V, V
= 4.5 V, ID = 15 A
= 2.5 V, ID = 10 A
= 0 V
GS
= 0 V, TJ = 55 °C
= 4.5 V
GS
1
10
30 A
0.0031 0.0038
0.0037 0.0047
110 S
3720
= 0 V, f = 1 MHz
GS
1290
840
= 8 V, ID = 10 A
GS
73 110
41 62
= 4.5 V, ID = 10 A
GS
4.5
8.5
f = 1 MHz 1.4 2.1 Ω
27 41
= 6 V, RL = 1.2 Ω
= 4.5 V, Rg = 1 Ω
GEN
125 190
53 80
12 18
16 25
= 6 V, RL = 1.2 Ω
= 8 V, Rg = 1 Ω
GEN
55 85
53 80
915
mV/°C
µA
Ω
pFOutput Capacitance
nC
ns
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2
Document Number: 68840
S-82288-Rev. B, 22-Sep-08
New Product
SiR492DP
Vishay Siliconix
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter Symbol Test Conditions Min. Typ. Max. Unit
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulse Diode Forward Current
Body Diode Voltage
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Reverse Recovery Fall Time
Reverse Recovery Rise Time
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and fun ctional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
a
I
S
I
SM
V
SD
t
rr
Q
rr
t
a
t
b
IF = 2 A, dI/dt = 100 A/µs, TJ = 25 °C
TC = 25 °C
IS = 3.2 A
35
60
0.61 1.2 V
46 70 ns
30 50 nC
20
26
A
ns
Document Number: 68840
S-82288-Rev. B, 22-Sep-08
www.vishay.com
3
New Product
SiR492DP
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
60
V = 5 thru 1.5 V
50
)A( tnerruC niarD -I
40
30
20
D
10
0
0.0 0.5 1.0 1.5 2.0 2.5
GS
V
- Drain-to-Source Voltage (V)
DS
1 V
Output Characteristics
0.0040
0.0038
(mΩ) ecnatsis
0.0036
e
R-nO
0.0034
-
)no(SD
R
0.0032
V
GS
= 2.5 V
V
GS
= 4.5 V
2.0
1.6
)A( tnerruC niarD -I
1.2
TC = 125 °C
0.8
D
0.4
0.0
0.0 0.3 0.6 0.9 1.2 1.5
TC = 25 °C
- Gate-to-Source Voltage (V)
V
GS
TC = - 55 °C
Transfer Characteristics
5000
C
4000
)Fp( ecnati
3000
c
a
pa
2000
C
-
C
1000
C
rss
iss
C
oss
0.0030
0
On-Resistance vs. Drain Current and Gate Voltage
8.0
)V( e
6.4
g
atl
o
V ecruoS-ot-etaG
4.8
3.2
-
GS
1.6
V
0.0
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4
10
I D = 10 A
0 1530456075
20 30 40 50 60
I
- Drain Current (A)
D
VDS = 6 V
VDS = 4 V
V
= 8 V
DS
Qg - Total Gate Charge (nC)
Gate Charge
0
0.0 1.6 3.2 4.8 6.4 8.0
VDS - Drain-to-Source Voltage (V)
Capacitance
1.5
ID = 15 A
1.3
e c n a t s i s
)dezilam
e
R - n O -
1.1
r
oN(
)no(SD
R
0.9
0.7
- 50 - 25 0 25 50 75 100 125 150
T
J
V
= 2.5 V
GS
- Junction Temperature (°C)
On-Resistance vs. Junction Temperature
Document Number: 68840
S-82288-Rev. B, 22-Sep-08
VGS = 4.5 V
New Product
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
100
(Ω) ecnatsiseR-nO ecruoS-ot-niarD -
10
)A( t
nerr
uC
ec
r
u
oS
I
1
0.1
S
0.01
0.001
0
TJ = 150 °C
TJ = 25 °C
0.2
- Source-to-Drain Voltage (V)
V
SD
0.6 0.8 1.0
0.4
Source-Drain Diode Forward Voltage
)no(SD
R
1.2
SiR492DP
Vishay Siliconix
0.020
0.016
0.012
0.008
TA= 125 °C
0.004
TA= 25 °C
0.000
012345
V
- Gate-to-Source Voltage (V)
GS
On-Resistance vs. Gate-to-Source Voltage
Power (W)
50
40
30
20
10
0
0.001
Time (s)
1
10 6000.1
Single Pulse Power, Junction-to-Ambient
1ms
10 ms
1000.01
0.3
I D = 250 µA
0.1
ID = 5 mA
- 0.1
Variance (V)
)ht(
S
G
V
- 0.3
- 0.5
- 50 - 25 0 25 50 75 100 125 150
T
- Temperature (°C)
J
Threshold Voltage
100
Limited byR
10
DS(on)
*
Document Number: 68840
S-82288-Rev. B, 22-Sep-08
- Drain Current (A)
I
100 ms
1
D
TA= 25 °C
0.1
0.01
Single Pulse
0.1 1 10
V
DS
> minimum VGSat which R
* V
GS
BVDSS Limited
- Drain-to-Source Voltage (V)
DS(on)
1s
10 s
DC
100
is specified
Safe Operating Area, Junction-to-Ambient
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5
New Product
SiR492DP
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
100
80
60
Package Limited
Pt ≤ 200 ms
40
- Drain Current (A)
D
I
20
0
0 25 50 75 100 125 150
TC- Case Temperature (°C)
Current Derating*
* The power dissipation PD is based on T
= 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
J(max)
40
32
24
16
Power Dissipation (W)
8
0
25 50 75 100 125 150
TC - Case Temperature (°C)
Power, Junction-to-Case
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
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6
Document Number: 68840
S-82288-Rev. B, 22-Sep-08
New Product
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
2
1
Duty Cycle = 0.5
SiR492DP
Vishay Siliconix
0.1
Thermal Impedance
Normalized Effective Transient
0.01
0.1
Thermal Impedance
Normalized Effective Transient
0.2
0.1
0.05
0.02
-4
10
2
1
Duty Cycle = 0.5
0.2
0.1
Single Pulse
0.02
Single Pulse
10
-3
-2
10
-1
1 10 60010
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
0.05
Notes:
P
DM
t
1
t
Duty Cycle, D =
1.
2. Per Unit Base = R
3. T
4. Surface Mounted
2
= P
- T
JM
A
DMZthJA
t
1
t
2
= 58 °C/W
thJA
(t)
100
0.01
-4
10
-3
10
-2
10
-1
110
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Case
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?68840.
Document Number: 68840
www.vishay.com
S-82288-Rev. B, 22-Sep-08
7
Package Information
Vishay Siliconix
PowerPAK® SO-8, (SINGLE/DUAL)
L
K
E4
D5
L
K
E4
D5
K1
W
1
2
3
4
θ
c
Notes
1.
2
3.
2
E1
E
Inch will govern.
Dimensions exclusive of mold gate burrs.
Dimensions exclusive of mold flash and cutting burrs.
M
e
L1
θ
A
θ
θ
Z
A1
Detail Z
H
D4
2
D
D1
D2
0.150 ± 0.008
Backside View of Single Pad
H
D4
D3(2x)
D2
Backside View of Dual Pad
E2
D
E3
E2
D1
D2
E3
MILLIMETERS INCHES
DIM. MIN. NOM. MAX. MIN. NOM. MAX.
A 0.97 1.04 1.12 0.038 0.041 0.044
A1 0.00 - 0.05 0.000 - 0.002
b 0.33 0.41 0.51 0.013 0.016 0.020
c 0.23 0.28 0.33 0.009 0.011 0.013
D 5.05 5.15 5.26 0.199 0.203 0.207
D1 4.80 4.90 5.00 0.189 0.193 0.197
D2 3.56 3.76 3.91 0.140 0.148 0.154
D3 1.32 1.50 1.68 0.052 0.059 0.066
D4
D5
0.57 TYP. 0.0225 TYP.
3.98 TYP. 0.157 TYP.
E 6.05 6.15 6.25 0.238 0.242 0.246
E1 5.79 5.89 5.99 0.228 0.232 0.236
E2 3.48 3.66 3.84 0.137 0.144 0.151
E3 3.68 3.78 3.91 0.145 0.149 0.154
E4
0.75 TYP. 0.030 TYP.
e 1.27 BSC 0.050 BSC
K
1.27 TYP. 0.050 TYP.
K1 0.56 - - 0.022 - -
H 0.51 0.61 0.71 0.020 0.024 0.028
L 0.51 0.61 0.71 0.020 0.024 0.028
L1 0.06 0.13 0.20 0.002 0.005 0.008
θ 0° - 12° 0° - 12°
W 0.15 0.25 0.36 0.006 0.010 0.014
M
0.125 TYP. 0.005 TYP.
ECN: T10-0055-Rev. J, 15-Feb-10
DWG: 5881
1
2
3
b
4
1
2
3
b
4
Document Number: 71655 www.vishay.com
Revison: 15-Feb-10 1
PowerPAK® SO-8 Mounting and Thermal Considerations
Wharton McDaniel
AN821
Vishay Siliconix
MOSFETs for switching applications are now available
with die on resistances around 1 mΩ and with the
capability to handle 85 A. While these die capabilities
represent a major advance over what was available
just a few years ago, it is important for power MOSFET
packaging technology to keep pace. It should be obvious that degradation of a high performance die by the
package is undesirable. PowerPAK is a new package
technology that addresses these issues. In this application note, PowerPAK’s construction is described.
Following this mounting information is presented
including land patterns and soldering profiles for maximum reliability. Finally, thermal and electrical performance is discussed.
THE PowerPAK PACKAGE
The PowerPAK package was developed around the
SO-8 package (Figure 1). The PowerPAK SO-8 utilizes the same footprint and the same pin-outs as the
standard SO-8. This allows PowerPAK to be substituted directly for a standard SO-8 package. Being a
leadless package, PowerPAK SO-8 utilizes the entire
SO-8 footprint, freeing space normally occupied by the
leads, and thus allowing it to hold a larger die than a
standard SO-8. In fact, this larger die is slightly larger
than a full sized DPAK die. The bottom of the die attach
pad is exposed for the purpose of providing a direct,
low resistance thermal path to the substrate the device
is mounted on. Finally, the package height is lower
than the standard SO-8, making it an excellent choice
for applications with space constraints.
PowerPAK SO-8 SINGLE MOUNTING
The PowerPAK single is simple to use. The pin
arrangement (drain, source, gate pins) and the pin
dimensions are the same as standard SO-8 devices
(see Figure 2). Therefore, the PowerPAK connection
pads match directly to those of the SO-8. The only difference is the extended drain connection area. To take
immediate advantage of the PowerPAK SO-8 single
devices, they can be mounted to existing SO-8 land
patterns.
Standard SO-8 PowerPAK SO-8
Figure 2.
The minimum land pattern recommended to take full
advantage of the PowerPAK thermal performance see
Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs. Click on the PowerPAK SO-8 single
in the index of this document.
In this figure, the drain land pattern is given to make full
contact to the drain pad on the PowerPAK package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-toambient thermal resistance. Under specific conditions
of board configuration, copper weight and layer stack,
experiments have found that more than about 0.25 to
2
0.5 in
of additional copper (in addition to the drain
land) will yield little improvement in thermal performance.
Figure 1. PowerPAK 1212 Devices
Document Number 71622
28-Feb-06
www.vishay.com
1
AN821
Vishay Siliconix
PowerPAK SO-8 DUAL
The pin arrangement (drain, source, gate pins) and the
pin dimensions of the PowerPAK SO-8 dual are the
same as standard SO-8 dual devices. Therefore, the
PowerPAK device connection pads match directly to
those of the SO-8. As in the single-channel package,
the only exception is the extended drain connection
area. Manufacturers can likewise take immediate
advantage of the PowerPAK SO-8 dual devices by
mounting them to existing SO-8 dual land patterns.
To take the advantage of the dual PowerPAK SO-8’s
thermal performance, the minimum recommended
land pattern can be found in Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click
on the PowerPAK 1212-8 dual in the index of this document.
The gap between the two drain pads is 24 mils. This
matches the spacing of the two drain pads on the PowerPAK SO-8 dual package.
REFLOW SOLDERING
Vishay Siliconix surface-mount packages meet solder
reflow reliability requirements. Devices are subjected
to solder reflow as a test preconditioning and are then
reliability-tested using temperature cycle, bias humidity, HAST, or pressure pot. The solder reflow temperature profile used, and the temperatures and time
duration, are shown in Figures 3 and 4.
For the lead (Pb)-free solder profile, see http://
www.vishay.com/doc?73257.
Ramp-Up Rate + 6 °C /Second Maximum
Temperature at 155 ± 15 °C
Temperature Above 180 °C
Maximum Temperature
Time at Maximum Temperature
Ramp-Down Rate
Figure 3. Solder Reflow Temperature Profile
120 Seconds Maximum
70 - 180 Seconds
240 + 5/- 0 °C
20 - 40 Seconds
+ 6 °C/Second Maximum
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2
140 - 170 °C
3 °C(max)
10 s (max)
210 - 220 °C
3 °C(max) 4 ° C/s (max)
183 °C
50 s (max)
60 s (min)
Pre-Heating Zone
Maximum peak temperature at 240 °C is allowed.
Figure 3. Solder Reflow Temperatures and Time Durations
Reflow Zone
Document Number 71622
28-Feb-06
THERMAL PERFORMANCE
AN821
Vishay Siliconix
Introduction
A basic measure of a device’s thermal performance is
the junction-to-case thermal resistance, Rθ
junction-to-foot thermal resistance, Rθ
. This parameter
jf
, or the
jc
is measured for the device mounted to an infinite heat
sink and is therefore a characterization of the device
only, in other words, independent of the properties of the
object to which the device is mounted. Table 1 shows a
comparison of the DPAK, PowerPAK SO-8, and standard SO-8. The PowerPAK has thermal performance
equivalent to the DPAK, while having an order of magnitude better thermal performance over the SO-8.
TABLE 1.
DPAK and PowerPAK SO-8
Equivalent Steady State Performance
Thermal
Resistance Rθ
DPAK PowerPAK
SO-8
1.2 °C/W 1.0 °C/W 16 °C/W
jc
Standard
SO-8
Thermal Performance on Standard SO-8 Pad Pattern
Because of the common footprint, a PowerPAK SO-8
can be mounted on an existing standard SO-8 pad pattern. The question then arises as to the thermal performance of the PowerPAK device under these conditions.
A characterization was made comparing a standard SO-8
and a PowerPAK device on a board with a trough cut out
underneath the PowerPAK drain pad. This configuration
restricted the heat flow to the SO-8 land pads. The
results are shown in Figure 5.
Because of the presence of the trough, this result suggests a minimum performance improvement of 10 °C/W
by using a PowerPAK SO-8 in a standard SO-8 PC
board mount.
The only concern when mounting a PowerPAK on a
standard SO-8 pad pattern is that there should be no
traces running between the body of the MOSFET.
Where the standard SO-8 body is spaced away from the
pc board, allowing traces to run underneath, the PowerPAK sits directly on the pc board.
Thermal Performance - Spreading Copper
Designers may add additional copper, spreading copper, to the drain pad to aid in conducting heat from a
device. It is helpful to have some information about the
thermal performance for a given area of spreading copper.
Figure 6 shows the thermal resistance of a PowerPAK
SO-8 device mounted on a 2-in. 2-in., four-layer FR-4
PC board. The two internal layers and the backside layer
are solid copper. The internal layers were chosen as
solid copper to model the large power and ground
planes common in many applications. The top layer was
cut back to a smaller area and at each step junction-toambient thermal resistance measurements were taken.
The results indicate that an area above 0.3 to 0.4 square
inches of spreading copper gives no additional thermal
performance improvement. A subsequent experiment
was run where the copper on the back-side was
reduced, first to 50 % in stripes to mimic circuit traces,
and then totally removed. No significant effect was
observed.
Si4874DY vs. Si7446DP PPAK on a 4-Layer Board
SO-8 Pattern, Trough Under Drain
60
50
)
s
ttaw/
40
C
( e
cn
30
adep
m
I
20
10
0
0.0001
Figure 5.
Document Number 71622
28-Feb-06
PowerPAK SO-8 and Standard SO-0 Land Pad Thermal Path
Si4874DY
1
Pulse Duration (sec)
Si7446DP
100
vs. Spreading Copper
R
th
(0 %, 50 %, 100 % Back Copper)
56
)sttaw/C(
51
ecn
46
adep
m
I
41
100000.01
36
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
0.00
Figure 6. Spreading Copper Junction-to-Ambient Performance
100 %
0 %
50 %
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3
AN821
Vishay Siliconix
SYSTEM AND ELECTRICAL IMPACT OF
PowerPAK SO-8
In any design, one must take into account the change in
MOSFET r
1.8
1.6
)
( ecnatsiseR-nO -r
1.4
)dezilamroN(
1.2
)no(SD
1.0
0.8
0.6
with temperature (Figure 7).
DS(on)
On-Resistance vs. Junction Temperature
VGS = 10 V
= 23 A
I
D
-50 -25 0 25 50 75 100 125 150
- Junction Temperature (°C)
T
J
Figure 7.
MOSFET
r
vs. Temperature
DS(on)
A MOSFET generates internal heat due to the current
passing through the channel. This self-heating raises
the junction temperature of the device above that of the
PC board to which it is mounted, causing increased
power dissipation in the device. A major source of this
problem lies in the large values of the junction-to-foot
thermal resistance of the SO-8 package.
PowerPAK SO-8 minimizes the junction-to-board thermal resistance to where the MOSFET die temperature is
very close to the temperature of the PC board. Consider
two devices mounted on a PC board heated to 105 °C
by other components on the board (Figure 8).
Suppose each device is dissipating 2.7 W. Using the
junction-to-foot thermal resistance characteristics of the
PowerPAK SO-8 and the standard SO-8, the die temperature is determined to be 107 °C for the PowerPAK
(and for DPAK) and 148 °C for the standard SO-8. This
is a 2 °C rise above the board temperature for the PowerPAK and a 43 °C rise for the standard SO-8. Referring
to Figure 7, a 2 °C difference has minimal effect on
r
whereas a 43C difference has a significant effect
DS(on)
on r
DS(on)
.
Minimizing the thermal rise above the board temperature by using PowerPAK has not only eased the thermal
design but it has allowed the device to run cooler, keep
r
low, and permits the device to handle more cur-
DS(on)
rent than the same MOSFET die in the standard SO-8
package.
CONCLUSIONS
PowerPAK SO-8 has been shown to have the same
thermal performance as the DPAK package while having the same footprint as the standard SO-8 package.
The PowerPAK SO-8 can hold larger die approximately
equal in size to the maximum that the DPAK can accommodate implying no sacrifice in performance because of
package limitations.
Recommended PowerPAK SO-8 land patterns are provided to aid in PC board layout for designs using this
new package.
Thermal considerations have indicated that significant
advantages can be gained by using PowerPAK SO-8
devices in designs where the PC board was laid out for
the standard SO-8. Applications experimental data gave
thermal performance data showing minimum and typical
thermal performance in a SO-8 environment, plus information on the optimum thermal performance obtainable
including spreading copper. This further emphasized the
DPAK equivalency.
PowerPAK SO-8
Figure 8.
www.vishay.com
4
Standard SO-8
107 °C
0.8 °C/W
PC Board at 105 °C
Temperature of Devices on a PC Board
16 C/W
148 °C
PowerPAK SO-8 therefore has the desired small size
characteristics of the SO-8 combined with the attractive
thermal characteristics of the DPAK package.
Document Number 71622
28-Feb-06
RECOMMENDED MINIMUM PADS FOR PowerPAK® SO-8 Single
0.260
(6.61)
0.150
(3.81)
0.024
(0.61)
Application Note 826
Vishay Siliconix
Return to Index
Return to Index
0.026
(0.66)
0.050
(1.27)
0.050
(1.27)
0.032
(0.82)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.154
(3.91)
0.040
(1.02)
0.174
(4.42)
APPLICATION NOTE
Document Number: 72599 www.vishay.com
Revision: 21-Jan-08 15
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www.vishay.com
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Revision: 02-Oct-12
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Document Number: 91000
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