Vishay SiHG20N50C Data Sheet

Power MOSFET

TO-247AC

G

D

S

SiHG20N50C

Vishay Siliconix

PRODUCT SUMMARY

VDS (V) at TJ max. 560

R

(Ω)V

DS(on)

Q

(Max.) (nC) 76

g

Q

(nC) 21

gs

Q

(nC) 34

gd

Configuration Single

= 10 V 0.270

GS

D

FEATURES

• Halogen-free According to IEC 61249-2-21
Definition

• Low Figure-of-Merit R

• 100 % Avalanche Tested

• High Peak Current Capability

• dV/dt Ruggedness

• Improved T

• Improved Gate Charge

• High Power Dissipations Capability

• Compliant to RoHS Directive 2002/95/EC

G

S

N-Channel MOSFET

ORDERING INFORMATION

Package TO-247AC
Lead (Pb)-free SiHG20N50C-E3
Lead (Pb)-free and Halogen-free SiHG20N50C-GE3

rr/Qrr

on

x Q

g

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage V

Gate-Source Voltage V

T

= 25 °C

Continuous Drain Current (T

Pulsed Drain Current

a

= 150 °C)

J

e

VGS at 10 V

C

= 100 °C 11

C

DS

± 30

GS

I

D

IDM 80

500

20

Linear Derating Factor 1.8 W/°C

Single Pulse Avalanche Energy

b

Maximum Power Dissipation P

Peak Diode Recovery dV/dt

c

Operating Junction and Storage Temperature Range T

Soldering Recommendations (Peak Temperature) for 10 s 300

E

AS

D

361 mJ

250 W

dV/dt 5 V/ns

, T

J

stg

- 55 to + 150

d

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature.
b. V

= 50 V, starting TJ = 25 °C, L = 2.5 mH, Rg = 25 Ω, IAS = 17 A.

DD

c. I

≤ 18 A, dI/dt ≤ 380 A/μs, VDD ≤ VDS, TJ ≤ 150 °C.

SD

d. 1.6 mm from case.
e. Limited by maximum junction temperature.

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT

Maximum Junction-to-Ambient R

Maximum Junction-to-Case (Drain)

thJA

R

thJC

-40

-0.5

°C/W

V

AT

°C

Document Number: 91382 www.vishay.com
S11-0440-Rev. C, 14-Mar-11 1

THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

This datasheet is subject to change without notice.

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SiHG20N50C

Vishay Siliconix

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-Source Breakdown Voltage V

Temperature Coefficient

V

DS

ΔV

Gate-Source Threshold Voltage (N) V

Gate-Source Leakage I

Zero Gate Voltage Drain Current I

Drain-Source On-State Resistance R

Forward Transconductance g

Dynamic

Input Capacitance C

Output Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Gate-Drain Charge Q

Turn-On Delay Time t

Rise Time t

Turn-Off Delay Time t

Fall Time t

Gate Input Resistance R

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current I

Pulsed Diode Forward Current I

DS

DS/TJ

GS(th)

V

GSS

DSS

V

DS(on)

fs

iss

- 300 360

oss

-2632

rss

g

-29-

gd

d(on)

r

-32-

d(off)

-44-

f

g

S

MOSFET symbol
showing the
integral reverse

SM

p - n junction diode

VGS = 0 V, ID = 250 μA 500 - - V

Reference to 25 °C, I

= 1 mA

D

-700-

VDS = VGS, ID = 250 μA 3.0 - 5.0 V

= ± 30 V - - ± 100 nA

GS

VDS = 500 V, VGS = 0 V - - 25

V

= 400 V, VGS = 0 V, TJ = 125 °C - - 250

DS

= 10 V ID = 10 A - 0.225 0.270 Ω

GS

VDS = 50 V, ID = 10 A - 6.4 - S

VGS = 0 V,

V

= 25 V,

DS

f = 1.0 MHz

- 2451 2942

-6576

V

= 10 V ID = 18 A, VDS = 400 V

GS

-80-

= 250 V, ID = 18 A,

V

DD

R

= 9.1 Ω

g

-27-

f = 1 MHz, open drain - 1.1 - Ω

D

G

S

--20

--80

mV/°C

μA

pF

nC Gate-Source Charge Qgs -21-

ns

A

Body Diode Voltage V

Body Diode Reverse Recovery Time t

Body Diode Reverse Recovery Charge Q

Reverse Recovery Current I

The information shown here is a preliminary product proposal, not a commercial product datasheet. Vishay Siliconix is not committed to produce this or any similar

product. This information should not be used for design purposes, nor construed as an offer to furnish or sell such products.

SD

rr

rr

RRM

TJ = 25 °C, IS = 18 A, VGS = 0 V - - 1.5 V

-503-ns

TJ = 25 °C, IF = IS,

dI/dt = 100 A/μs, V = 35 V

-6.7-μC

-30-A

www.vishay.com Document Number: 91382
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This datasheet is subject to change without notice.

THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

VDS, Drain-to-Source Voltage (V)

I

D

, Drain Current (A)

0

10

20

30

40

50

60

70

0612 18

24

30

7.0 V

Bottom

To p

V

GS

15 V
14 V
13 V
12 V
11 V
10 V

9.0 V

8.0 V

7.0 V

6.0 V

5.0 V

TJ = 25 °C

0

10

20

30

40

0 6 12 18 24 30

7.0 V

VDS, Drain-to-Source Voltage (V)

I

D

, Drain Current (A)

Bottom

To p

V

GS

15 V
14 V
13 V
12 V
11 V
10 V

9.0 V

8.0 V

7.0 V

6.0 V

5.0 V

TJ = 150 °C

I

D

, Drain Current (A)

V

GS

,

Gate-to-Source Voltage (V)

0.01

0.1

1

10

100

5678910

TJ= 150 °C

T

J

= 25 °C

SiHG20N50C

Vishay Siliconix

Fig. 1 - Typical Output Characteristics, TC = 25 °C

Fig. 2 - Typical Output Characteristics, T

= 150 °C

C

, Drain-to-Source On Resistance

DS(on)

R

Fig. 3 - Typical Transfer Characteristics

3

ID = 17 A

2.5

2

1.5

(Normalized)

1

0.5

0

- 60 - 40 - 20 0 20 40 60 80 100 120 140 160

T

Junction Temperature (°C)

,

J

V

GS

= 10 V

Fig. 4 - Normalized On-Resistance vs. Temperature

Document Number: 91382 www.vishay.com
S11-0440-Rev. C, 14-Mar-11 3

THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

This datasheet is subject to change without notice.

www.vishay.com/doc?91000

SiHG20N50C

Capacitance (pF)

V

DS

,

Drain-to-Source Voltage (V)

10

10

2

10

3

10

4

10

5

1101001000

V

GS

= 0 V, f = 1 MHz

C

iss

= Cgs + Cgd, Cds Shorted

C

rss

= C

gd

C

oss

= Cds + C

gd

C

iss

C

rss

C

oss

QG, Total Gate Charge (nC)

V

GS

, Gate-to-Source Voltage (V)

0

4

8

12

16

20

0306090120

ID = 17 A

V

DS

= 250 V

V

DS

= 100 V

V

DS

= 400 V

VDS, Drain-to-Source Voltage (V)

I

D

, Drain Current (A)

TC = 25 °C
T

J

= 150 °C

Single Pulse

Operation in this area limited

by R

DS(on)

1 ms

10 ms

100 µs

1000

1

10

100

10

100 1000

10 000

0.1

Vishay Siliconix

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

100

TJ = 150 °C

10

T

= 25 °C

J

Fig. 8 - Maximum Safe Operating Area

20

15

10

, Drain Current (A)

D

5

I

0

25 50 75 100 125 150

TC, Case Temperature (°C)

Fig. 9 - Maximum Drain Current vs. Case Temperature

1

, Reverse Drain Current (A)

SD

I

0.1

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THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

Fig. 7 - Typical Source-Drain Diode Forward Voltage

0.2 0.5 0.8 1.1 1.4

VSD, Source-to-Drain Voltage (V)

V

= 0 V

GS

This datasheet is subject to change without notice.

www.vishay.com/doc?91000

Fig. 10 - Normalized Thermal Transient Impedance, Junction-to-Case (TO-247)

10

-4

10

-3

10

-2

0.1 1

Normalized Effective Transient

Thermal Impedance

0.01

0.1

1

Pulse Time (s)

Single Pulse

0.02

0.05

0.1

0.2

Duty Cycle = 0.5

Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

R

D

V

GS

R

g

D.U.T.

10 V

+

-

V

DS

V

DD

V

DS

90 %

10 %

V

GS

t

d(on)

t

r

t

d(off)

t

f

R

g

I

AS

0.01 Ω

t

p

D.U.T

L

V

DS

+

-

V

DD

10 V

Var y tp to obtain
required I

AS

I

AS

V

DS

V

DD

V

DS

t

p

SiHG20N50C

Vishay Siliconix

Fig. 11a - Switching Time Test Circuit

Fig. 12b - Unclamped Inductive Waveforms

Q

G

Q

GD

Charge

Fig. 11b - Switching Time Waveforms

10 V

Q

GS

V

G

Fig. 13a - Basic Gate Charge Waveform

Current regulator

Same type as D.U.T.

50 kΩ

0.2 µF

12 V

V

GS

3 mA

0.3 µF

D.U.T.

+

V

DS

-

Document Number: 91382 www.vishay.com
S11-0440-Rev. C, 14-Mar-11 5

THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

Fig. 12a - Unclamped Inductive Test Circuit

I

G

Current sampling resistors

I

D

Fig. 13b - Gate Charge Test Circuit

This datasheet is subject to change without notice.

www.vishay.com/doc?91000

SiHG20N50C

P.W.

Period

dI/dt

Diode recovery

dV/dt

Ripple ≤ 5 %

Body diode forward drop

Re-applied
voltage

Reverse
recovery
current

Body diode forward

current

V

GS

= 10 Va

I

SD

Driver gate drive

D.U.T. l

SD

waveform

D.U.T. V

DS

waveform

Inductor current

D =

P.W.

Period

+

-

+

+

+

-

-

-

Peak Diode Recovery dV/dt Test Circuit

V

DD

• dV/dt controlled by R

g

• Driver same type as D.U.T.

•

I

SD

controlled by duty factor “D”

• D.U.T. - device under test

D.U.T.

Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance

current transformer

R

g

Note

a. V

GS

= 5 V for logic level devices

V

DD

Vishay Siliconix

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91382

www.vishay.com Document Number: 91382
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.

This datasheet is subject to change without notice.

THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

Fig. 14 - For N-Channel

www.vishay.com/doc?91000

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0.10 AC

M M

E

E/2

(2)

(4)

R/2

B

2 x R

S

D

See view B

2 x e

b4

3 x b

2 x b2

L

C

L1

1

2

3

Q

D

A

A2

A

A

A1

C

Ø k BD

M M

A

ØP

(Datum B)

ØP1

D1

4

E1

0.01 BD

M M

View A - A

Thermal pad

D2

DDE E

C

C

View B

(b1, b3, b5)

Base metal

c1

(b, b2, b4)

Section C - C, D - D, E - E

(c)

Planting

4

3

5

7

4

4

4

Lead Assignments

1. Gate

2. Drain

3. Source

4. Drain

Package Information

Vishay Siliconix

TO-247AC (High Voltage)

MILLIMETERS INCHES MILLIMETERS INCHES

DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.

A 4.58 5.31 0.180 0.209 D2 0.51 1.30 0.020 0.051
A1 2.21 2.59 0.087 0.102 E 15.29 15.87 0.602 0.625
A2 1.17 2.49 0.046 0.098 E1 13.72 - 0.540 -

b 0.99 1.40 0.039 0.055 e 5.46 BSC 0.215 BSC
b1 0.99 1.35 0.039 0.053 Ø k 0.254 0.010
b2 1.53 2.39 0.060 0.094 L 14.20 16.25 0.559 0.640
b3 1.65 2.37 0.065 0.093 L1 3.71 4.29 0.146 0.169
b4 2.42 3.43 0.095 0.135 N 7.62 BSC 0.300 BSC
b5 2.59 3.38 0.102 0.133 Ø P 3.51 3.66 0.138 0.144

c 0.38 0.86 0.015 0.034 Ø P1 - 7.39 - 0.291
c1 0.38 0.76 0.015 0.030 Q 5.31 5.69 0.209 0.224

D 19.71 20.82 0.776 0.820 R 4.52 5.49 0.178 0.216

D1 13.08 - 0.515 - S 5.51 BSC 0.217 BSC

ECN: X13-0103-Rev. D, 01-Jul-13
DWG: 5971

Notes

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Contour of slot optional.

3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outermost extremes of the plastic body.

4. Thermal pad contour optional with dimensions D1 and E1.

5. Lead finish uncontrolled in L1.

6. Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154").

7. Outline conforms to JEDEC outline TO-247 with exception of dimension c.

8. Xian and Mingxin actually photo.

Revision: 01-Jul-13

Document Number: 91360

1

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Revision: 13-Jun-16

1

Document Number: 91000