Datasheet SiC632, SiC632A Datasheet (Vishay)

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50 A VRPower® Integrated Power Stage

SiC632, SiC632A

Vishay Siliconix

DESCRIPTION

The SiC632 and SiC632A are integrated power stage
solutions optimized for synchronous buck applications to
offer high current, high efficiency, and high power density
performance. Packaged in Vishay’s proprietary
MLP package, SiC632 and SiC632A enables voltage
regulator designs to deliver up to 50 A continuous current
per phase.

The internal power MOSFETs utilizes Vishay’s

®

state-of-the-art Gen IV TrenchFET

technology that delivers
industry benchmark performance to significantly reduce
switching and conduction losses.

The SiC632 and SiC632A incorporate an advanced
MOSFET gate driver IC that features high current driving
capability, adaptive dead-time control, an integrated
bootstrap Schottky diode, a thermal warning (THWn) that
alerts the system of excessive junction temperature, and
zero current detection to improve light load efficiency. The
drivers are also compatible with a wide range of PWM
controllers and supports tri-state PWM, 3.3 V (SiC632A), 5 V
(SiC632) PWM logic.

5 mm x 5 mm

FEATURES

• Thermally enhanced PowerPAK® MLP55-31L
package

• Vishay’s Gen IV MOSFET technology and a low
side MOSFET with integrated Schottky diode

• Delivers up to 50 A continuous current

• High efficiency performance

• High frequency operation up to 1.5 MHz

• Power MOSFETs optimized for 19 V input stage

• 3.3 V (SiC632A), 5 V (SiC632) PWM logic with tri-state and
hold-off

• Zero current detect control for light load efficiency
improvement

• Low PWM propagation delay (< 20 ns)

• Faster disable

• Thermal monitor flag

• Under voltage lockout for V

CIN

• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912

APPLICATIONS

• Multi-phase VRDs for computing, graphics card and
memory

• Intel IMVP-8 VRPower delivery

- V

- V

• Up to 24 V rail input DC/DC VR modules

CORE

, V

GRAPHICS

, V

platforms

for Apollo Lake platforms

CCGI

SYSTEM AGENT

Skylake, Kabylake

TYPICAL APPLICATION DIAGRAM

5V V

V

DRV

V

CIN

ZCD_EN#

PWM

controller

S20-0486-Rev. E, 29-Jun-2020

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DSBL#

PWM

THWn

Fig. 1 - SiC632 and SiC632A Typical Application Diagram

For technical questions, contact: [e-mail]

Gate

driver

GL

C

GND

V

IN

BOOT

PHASE

V

SWH

P

GND

1

Document Number: 62992

IN

V

OUT

www.vishay.com

P

GND

C

GND

BOOT

PHASE

V

IN

P

GNDPGNDPGNDPGND

VINVINV

IN

N.C.

GL

V

DRV

THWn

DSBL#

PWM

ZCD_EN#

V

CIN

PGND

VIN

CGND

GL

Top view Bottom view

P

GND

C

GND

BOOT

PHASE

V

IN

P

GNDPGNDPGNDPGND

VINV

INVIN

N.C.

GL

V

DRV

THWn

DSBL#

PWM

ZCD_EN#

V

CIN

35

P

GND

34

V

IN

32

C

GND

GL

2

1

4

3

6

5

8

7

2425262728293031

1514131211109

2

1

4

3

6

5

8

7

15 14 13 12 11 10 9

24 25 26 27 28 29 30 31

V

SWH

23

V

SWHVSWH

V

SWH

V

SWHVSWH

V

SWH

33
GL

V

SWH

22

V

SWH

21

V

SWH

20

V

SWH

19

V

SWH

18

V

SWH

17

V

SWH

16

23 V

SWH

22 V

SWH

21 V

SWH

20 V

SWH

19 V

SWH

16 V

SWH

18 V

SWH

17 V

SWH

PINOUT CONFIGURATION

SiC632, SiC632A

Vishay Siliconix

PIN CONFIGURATION

PIN NUMBER NAME FUNCTION

1 PWM PWM input logic

2 ZCD_EN# ZCD control. Active low

3V

4, 32 C

5 BOOT High side driver bootstrap voltage

6 N.C. Not connected internally, can be left floating or connected to ground

7 PHASE Return path of high side gate driver

8 to 11, 34 V

12 to 15, 28, 35 P

16 to 26 V

27, 33 GL Low side MOSFET gate signal

29 V

30 THWn Thermal warning open drain output

31 DSBL# Disable pin. Active low

ORDERING INFORMATION

PART NUMBER PACKAGE MARKING CODE OPTION

SiC632CD-T1-GE3 PowerPAK MLP55-31L SiC632 5 V PWM optimized

SiC632ACD-T1-GE3 PowerPAK MLP55-31L SiC632A 3.3 V PWM optimized

SiC632DB / SiC632ADB Reference board

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Fig. 2 - SiC632 and SiC632A Pin Configuration

CIN

GND

IN

GND

SWH

DRV

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Supply voltage for internal logic circuitry

Signal ground

Power stage input voltage. Drain of high side MOSFET

Power ground

Phase node of the power stage

Supply voltage for internal gate driver

2

For technical questions, contact: [e-mail]

Document Number: 62992

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PART MARKING INFORMATION

P/N

SiC632, SiC632A

Vishay Siliconix

= Pin 1 Indicator

P/N = Part Number Code

= Siliconix Logo

LL

= ESD Symbol

F = Assembly Factory Code

F Y W W

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL PARAMETER CONDITIONS LIMIT UNIT

Input voltage V

Control logic supply voltage V

Drive supply voltage V

Switch node (DC voltage)

Switch node (AC voltage)

BOOT voltage (DC voltage)

BOOT voltage (AC voltage)

BOOT to PHASE (DC voltage)

BOOT to PHASE (AC voltage)

All lo gic i npu ts an d o utpu ts
(PWM, DSBL#, and THWn)

Max. operating junction temperature T

Storage temperature T

Electrostatic discharge protection

Notes

• Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability

(1)

The specification values indicated “AC” is V

(2)

The specification value indicates “AC voltage” is V

(3)

The specification value indicates “AC voltage” is V

(1)

(2)

(3)

Human body model, JESD22-A114 3000

Charged device model, JESD22-C101 1000

to P

SWH

GND

BOOT

BOOT

V

V

BOOT

V

BOOT-PHASE

-8 V (< 20 ns, 10 μJ), min. and 33 V (< 50 ns), max.

to P

, 40 V (< 50 ns) max.

GND

to V

PHASE

Y = Year Code

WW = Week Code

LL = Lot Code

IN

CIN

DRV

SWH

J

A

stg

, 8 V (< 20 ns) max.

-0.3 to +28

-0.3 to +7

-0.3 to +7

-0.3 to +28

-7 to +33

-0.3 to +7

-0.3 to +8

-0.3 to V

-40 to +125

-65 to +150

35

40

150

CIN

V

+ 0.3

°CAmbient temperature T

V

RECOMMENDED OPERATING RANGE

ELECTRICAL PARAMETER MINIMUM TYPICAL MAXIMUM UNIT

Input voltage (V

Drive supply voltage (V

Control logic supply voltage (V

BOOT to PHASE (V

Thermal resistance from junction to ambient - 10.6 -

Thermal resistance from junction to case - 1.6 -

S20-0486-Rev. E, 29-Jun-2020

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)4.5-24

IN

) 4.555.5

DRV

) 4.555.5

CIN

BOOT-PHASE

, DC voltage) 4 4.5 5.5

3

For technical questions, contact: [e-mail]

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Document Number: 62992

V

°C/W

SiC632, SiC632A

www.vishay.com

ELECTRICAL SPECIFICATIONS

(DSBL# = ZCD_EN# = 5 V, V

PARAMETER SYMBOL TEST CONDITION

POWER SUPPLY

Control logic supply current I

Drive supply current I

BOOTSTRAP SUPPLY

Bootstrap diode forward voltage V

PWM CONTROL INPUT (SiC632)

Rising threshold V

Falling threshold V

Tri-state voltage V

Tri-state rising threshold V

Tri-state falling threshold V

Tri-state rising threshold hysteresis V

Tri-state falling threshold hysteresis V

PWM input current I

PWM CONTROL INPUT (SiC632A)

Rising threshold V

Falling threshold V

Tri-state Voltage V

Tri-state rising threshold V

Tri-state falling threshold V

Tri-state rising threshold hysteresis V

Tri-state falling threshold hysteresis V

PWM input current I

TIMING SPECIFICATIONS

Tri-state to GH/GL rising
propagation delay

Tri-state hold-off time t

GH - turn off propagation delay t

GH - turn on propagation delay
(dead time rising)

GL - turn off propagation delay t

GL - turn on propagation delay
(dead time falling)

DSBL# Lo to GH/GL falling
propagation delay

PWM minimum on-time t

= 12 V, V

IN

VDRV

TH_PWM_R

TH_PWM_F

TRI_TH_R

TRI_TH_F

HYS_TRI_R

HYS_TRI_F

PWM

TH_PWM_R

TH_PWM_F

TRI_TH_R

TRI_TH_F

HYS_TRI_R

HYS_TRI_F

PWM

t

PD_TRI_R

TSHO

PD_OFF_GH

t

PD_ON_GH

PD_OFF_GL

t

PD_ON_GL

t

PD_DSBL#_F

PWM_ON_MIN

VCIN

F

TRI

TRI

DRV

and V

V

DSBL#

DSBL#

= 5 V, TA = 25 °C)

CIN

= 0 V, no switching, V

= 5 V, no switching, V

V

= 5 V, fS = 300 kHz, D = 0.1 - 525 -

DSBL#

fS = 300 kHz, D = 0.1 - 10 15

f

S

V

DSBL#

V

DSBL#

No load, see Fig. 4

MIN. TYP. MAX.

= FLOAT - 10 -

PWM

= FLOAT - 300 -

PWM

= 1 MHz, D = 0.1 - 35 -

= 0 V, no switching - 15 -

= 5 V, no switching - 55 -

IF = 2 mA 0.4 V

3.4 3.8 4.2

0.72 0.9 1.1

V

= FLOAT - 2.3 -

PWM

0.9 1.15 1.38

33.33.6

- 225 -

- 325 -

V

= 5 V - - 350

PWM

= 0 V - - -350

V

PWM

2.3 2.45 2.7

0.72 0.9 1.1

V

= FLOAT - 1.8 -

PWM

0.9 1.15 1.38

1.95 2.2 2.45

- 250 -

- 300 -

V

= 3.3 V - - 225

PWM

= 0 V - - -225

V

PWM

-30-

- 130 -

-15-

-10-

-13-

-10-

Fig. 5 - 15 -

30 - -

Vishay Siliconix

LIMITS

UNIT

μAV

mA

μA

V

mV

μA

V

mV

μA

ns

S20-0486-Rev. E, 29-Jun-2020

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ELECTRICAL SPECIFICATIONS

(DSBL# = ZCD_EN# = 5 V, V

PARAMETER SYMBOL TEST CONDITION

DSBL# ZCD_EN# INPUT

DSBL# logic input voltage

ZCD_EN# logic input voltage

PROTECTION

Under voltage lockout V

Under voltage lockout hysteresis V
THWn flag set

THWn flag hysteresis
THWn output low V

Notes

(1)

Typical limits are established by characterization and are not production tested

(2)

Guaranteed by design

(2)

(2)

(2)

= 12 V, V

IN

V

IH_DSBL#

V

IL_DSBL#

V

IH_ZCD_EN#

V

IL_ZCD_EN#

UVLO_HYST

T

THWn_SET

T

THWn_CLEAR

T

THWn_HYST

OL_THWn

UVLO

DRV

and V

= 5 V, TA = 25 °C)

CIN

MIN. TYP. MAX.

Input logic high 2 - -

Input logic low - - 0.8

Input logic high 2 - -

Input logic low - - 0.8

V

rising, on threshold - 3.7 4.1

CIN

V

falling, off threshold 2.7 3.1 -

CIN

I

= 2 mA - 0.02 - V

THWn

SiC632, SiC632A

Vishay Siliconix

LIMITS

- 575 - mV

- 160 -

- 135 -

-25-

UNIT

V

V

°CTHWn flag clear

DETAILED OPERATIONAL DESCRIPTION

PWM Input with Tri-State Function

The PWM input receives the PWM control signal from the VR
controller IC. The PWM input is designed to be compatible
with standard controllers using two state logic (H and L) and
advanced controllers that incorporate tri-state logic (H, L
and tri-state) on the PWM output. For two state logic, the
PWM input operates as follows. When PWM is driven above
V

PWM_TH_R

turned on. When PWM input is driven below V
high side is turned off and the low side is turned on. For
tri-state logic, the PWM input operates as previously stated
for driving the MOSFETs when PWM is logic high and logic
low. However, there is a third state that is entered as the
PWM output of tri-state compatible controller enters its high
impedance state during shutdown. The high impedance
state of the controller’s PWM output allows the SiC632 and
SiC632A to pull the PWM input into the tri-state region (see
definition of PWM logic and tri-state, Fig. 4). If the PWM
input stays in this region for the tri-state hold-off period,
tTSHO, both high side and low side MOSFETs are turned
off. The function allows the VR phase to be disabled without
negative output voltage swing caused by inductor ringing
and saves a Schottky diode clamp. The PWM and tri-state
regions are separated by hysteresis to prevent false
triggering. The SiC632A incorporates PWM voltage
thresholds that are compatible with 3.3 V logic and the
SiC632 thresholds are compatible with 5 V logic.

Disable (DSBL#)

In the low state, the DSBL# pin shuts down the driver IC and
disables both high side and low side MOSFETs. In this state,
standby current is minimized. If DSBL# is left unconnected,
an internal pull-down resistor will pull the pin to C
shut down the IC.

the low side is turned off and the high side is

GND

the

and

PWM_TH_F

Diode Emulation Mode (ZCD_EN#)

When ZCD_EN# pin is driven below V

IL_ZCD_EN#

. diode
emulation mode is enabled. If the PWM signal switches
below V

TH_PWM_F

then the LS MOSFET is under control of
the ZCD (zero crossing detect) comparator. If, after the
internal blanking delay, the inductor current becomes less
than or = 0 the low side is turned off. Light load efficiency is
improved by avoiding discharge of output capacitors. If both
high side and low side MOSFETs are required to be turned
off, regardless of inductor current, the PWM input should be
tri-stated.

Thermal Shutdown Warning (THWn)

The THWn pin is an open drain signal that flags the presence
of excessive junction temperature. Connect with a
maximum of 20 k, to V

. An internal temperature sensor

CIN

detects the junction temperature. The temperature
threshold is 160 °C. When this junction temperature is
exceeded the THWn flag is set. When the junction
temperature drops below 135 °C the device will clear the
THWn signal. The SiC632 and SiC632A do not stop
operation when the flag is set. The decision to shutdown
must be made by an external thermal control function.

Voltage Input (V

)

IN

This is the power input to the drain of the high side power
MOSFET. This pin is connected to the high power
intermediate BUS rail.



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5

Document Number: 62992

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DISB#

20K

V

SWH

V

SWH

GL

+

-

GL

+

-

ZCD_EN#

Thermal monitor

& warning

UVLO

V

CIN

PWM logic

control &

state

machine

Anti-cross

conduction

control

logic

BOOT

THWn

V

IN

PWM

C

GND

V

CIN

V

ref

= 1 V

V

ref

= 1 V

P

GND

PHASE

V

DRV

V

DRV

P

GND

SiC632, SiC632A

Vishay Siliconix

Switch Node (V

The switch node, V

and PHASE)

SWH

, is the circuit power stage output.

SWH

This is the output applied to the power inductor and output
filter to deliver the output for the buck converter. The PHASE
pin is internally connected to the switch node V

SWH

. This pin
is to be used exclusively as the return pin for the BOOT
capacitor. A 20 k resistor is connected between GH
(the high side gate) and PHASE to provide a discharge path
for the HS MOSFET in the event that V

goes to zero while

CIN

VIN is still applied.

Ground Connections (C

P

(power ground) should be externally connected

GND

to C

(signal ground). The layout of the printed circuit

GND

board should be such that the inductance separating C
and P

is minimized. Transient differences due to

GND

GND

and P

GND

)

GND

inductance effects between these two pins should not
exceed 0.5 V

, V

Control and Drive Supply Voltage Input (V

V

is the bias supply for the gate drive control IC. V

CIN

DRV

CIN

)

DRV

is
the bias supply for the gate drivers. It is recommended to
separate these pins through a resistor. This creates a low
pass filtering effect to avoid coupling of high frequency gate
drive noise into the IC.









FUNCTIONAL BLOCK DIAGRAM

Bootstrap Circuit (BOOT)

The internal bootstrap diode and an external bootstrap
capacitor form a charge pump that supplies voltage to the
BOOT pin. An integrated bootstrap diode is incorporated so
that only an external capacitor is necessary to complete the
bootstrap circuit. Connect a boot strap capacitor with one
leg tied to BOOT pin and the other tied to PHASE pin.

Shoot-Through Protection and Adaptive Dead Time

The SiC632 and SiC632A have an internal adaptive logic to
avoid shoot through and optimize dead time. The shoot
through protection ensures that both high side and low side
MOSFETs are not turned on at the same time. The adaptive
dead time control operates as follows. The high side and low
side gate voltages are monitored to prevent the MOSFET
turning on from tuning on until the other MOSFET's gate
voltage is sufficiently low (< 1 V). Built in delays also ensure
that one power MOSFET is completely off, before the other
can be turned ON. This feature helps to adjust dead time as
gate transitions change with respect to output current and
temperature.

Under Voltage Lockout (UVLO)

During the start up cycle, the UVLO disables the gate
drive holding high side and low side MOSFET gates low
until the supply voltage rail has reached a point at which
the logic circuitry can be safely activated. The SiC632,
SiC632A also incorporates logic to clamp the gate drive
signals to zero when the UVLO falling edge triggers the
shutdown of the device. As an added precaution, a 20 k
resistor is connected between GH (the high side gate) and
PHASE to provide a discharge path for the HS MOSFET.

Fig. 3 - SiC632 and SiC632A Functional Block Diagram

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Document Number: 62992

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PWM

DSBL#

GH

GL

DSBL#Low to GH Falling Propagation Delay

t

DSBL# Low to GL Falling Propagation Delay

PWM

DSBL#

GH

GL

t

Disable

DEVICE TRUTH TABLE

DSBL# ZCD_EN# PWM GH GL

Open X X L L

LXXLL

HLLL

HLHHL

HLTri-stateLL

HHL LH

HHHHL

HHTri-stateL L

PWM TIMING DIAGRAM

SiC632, SiC632A

Vishay Siliconix

H, I

> 0 A

L

L, I

< 0 A

L

VTH_PWM_R

VTH_PWM_F

PWM

GL

GH

t

PD_OFF _GL

t

PD_ON_GH

VTH_TRI_F

VTH_TRI_R

DSBL# PROPAGATION DELAY

t

TSHO

t

PD_ON_GL

t

PD_OFF _GH

t

PD_TRI_R

Fig. 4 - Definition of PWM Logic and Tri-state

t

PD_TRI_R

t

TSHO

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Fig. 5 - DSBL# Falling Propagation Delay

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SiC632, SiC632A

62

66

70

74

78

82

86

90

94

0 5 10 15 20 25 30 35 40 45 50

Efciency (%)

Output Current, I

OUT

(A)

Complete converter efciency
P

IN

= [(VINx IIN) + 5 V x (I

VDRV

+ I

VCIN

)]

P

OUT

= V

OUT

x I

OUT

, measured at output capacitor

1 MHz

750 kHz

500 kHz

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

200 300 400 500 600 700 800 900 1000 1100

Power Loss, P

L

(W)

Switching Frequency, fs (KHz)

I

OUT

= 25A

62

66

70

74

78

82

86

90

94

98

0 5 10 15 20 25 30 35 40 45 50

Efciency (%)

Output Current, I

OUT

(A)

Complete converter efciency
P

IN

= [(VINx IIN) + 5 V x (I

VDRV

+ I

VCIN

)]

P

OUT

= V

OUT

x I

OUT

, measured at output capacitor

1 MHz

750 kHz

500 kHz

15

20

25

30

35

40

45

50

55

0 153045607590105120135150

Output Current, I

OUT

(A)

PCB Temperature, T

PCB

(°C)

1 MHz

500 kHz

0.0

2.0

4.0

6.0

8.0

10.0

12.0

14.0

16.0

0 5 10 15 20 25 30 35 40 45

Power Loss, P

L

(W)

Output Current, I

OUT

(A)

750 kHz

1 MHz

500 kHz

62

66

70

74

78

82

86

90

94

0 5 10 15 20 25 30 35 40 45 50

Efciency (%)

Output Current, I

OUT

(A)

Complete converter efciency
P

IN

= [(VINx IIN) + 5 V x (I

VDRV

+ I

VCIN

)]

P

OUT

= V

OUT

x I

OUT

, measured at output capacitor

1 MHz

500 kHz

750 kHz

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ELECTRICAL CHARACTERISTICS

Test condition: VIN = 13 V, DSBL# = V
natural convection cooling (All power loss and normalized power loss curves show SiC632 and SiC632A losses only unless otherwise stated)

DRV

= V

= 5 V, ZCD_EN# = 5 V, V

CIN

OUT

= 1 V, L

= 250 nH (DCR = 0.32 m), TA = 25 °C,

OUT

Vishay Siliconix

Fig. 6 - Efficiency vs. Output Current (V

= 12.6 V)

IN

Fig. 7 - Power Loss vs. Switching Frequency (V

= 12.6 V)

IN

Fig. 9 - Safe Operating Area

Fig. 10 - Power Loss vs. Output Current (V

= 12.6 V)

IN

Fig. 8 - Efficiency vs. Output Current (V

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= 9 V)

IN

For technical questions, contact: [e-mail]

8

Fig. 11 - Efficiency vs. Output Current (V

= 19 V)

IN

Document Number: 62992

SiC632, SiC632A

2.6

2.8

3.0

3.2

3.4

3.6

3.8

4.0

-60 -40 -20 0 20 40 60 80 100 120 140

Control Logic Supply Voltage, V

CIN

(V)

Temperature (°C)

V

UVLO_FALLING

V

UVLO_RISING

4.2

0.40

0.75

1.10

1.45

1.80

2.15

2.50

2.85

3.20

-60 -40 -20 0 20 40 60 80 100 120 140

Control Logic Supply Voltage, V

PWM

(V)

Temperature (°C)

V

TRI_TH_R

V

TRI_TH_F

V

TRI

V

TH_PWM_R

V

TH_PWM_F

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

-60 -40 -20 0 20 40 60 80 100 120 140

Control Logic Supply Voltage, V

PWM

(V)

Temperature (°C)

V

TRI_TH_R

V

TRI_TH_F

V

TRI

V

TH_PWM_R

V

TH_PWM_F

0.40

0.75

1.10

1.45

1.80

2.15

2.50

2.85

3.20

4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5

PWM Threshold Voltage, V

PWM

(V)

Driver Supply Voltage, V

CIN

(V)

V

TH_PWM_F

V

TH_PWM_R

V

TRI_TH_F

V

TRI_TH_R

V

www.vishay.com

ELECTRICAL CHARACTERISTICS

Test condition: VIN = 13 V, DSBL# = V
natural convection cooling (All power loss and normalized power loss curves show SiC632 and SiC632A losses only unless otherwise stated)

DRV

= V

= 5 V, ZCD_EN# = 5 V, V

CIN

OUT

= 1 V, L

0.40

= 250 nH (DCR = 0.32 m), TA = 25 °C,

OUT

Vishay Siliconix

Fig. 12 - UVLO Threshold vs. Temperature

0.35

(V)

0.30

F

IF= 2 mA

0.25

0.20

0.15

0.10

0.05

BOOT Diode Forward Voltage, V

0.00

-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)

Fig. 15 - Boot Diode Forward Voltage vs. Temperature

TRI

Fig. 13 - PWM Threshold vs. Temperature (SiC632A)

Fig. 14 - PWM Threshold vs. Temperature (SiC632)

S20-0486-Rev. E, 29-Jun-2020

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Fig. 16 - PWM Threshold vs. Driver Supply Voltage (SiC632A)

5.00

4.50

(V)

4.00

PWM

3.50

3.00

2.50

2.00

1.50

1.00

PWM Threshold Voltage, V

0.50

0

4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5

Fig. 17 - PWM Threshold vs. Driver Supply Voltage (SiC632)

9

For technical questions, contact: [e-mail]

V

TRI

V

TRI_TH_R

V

TH_PWM_F

Driver Supply Voltage, V

V

TH_PWM_R

V

TRI_TH_F

(V)

CIN

Document Number: 62992

SiC632, SiC632A

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

-60 -40 -20 0 20 40 60 80 100 120 140

DSBL# Threshold Voltage, V

DSBL#

(V)

Temperature (°C)

V

IL_DSBL#

V

IH_DSBL#

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5

DSBL# Threshold Voltage, V

DSBL#

(V)

Driver Supply Voltage, V

CIN

(V)

V

IH_DSBL#

V

IL_DSBL#

10.0

10.1

10.2

10.3

10.4

10.5

10.6

10.7

10.8

-60 -40 -20 0 20 40 60 80 100 120 140

DSBL# Pull-Down Current, I

DSBL#

(uA)

Temperature (°C)

0.60

0.80

1.00

1.20

1.40

1.60

1.80

2.00

2.20

4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5

ZCD_EN# Threshold Voltage, V

ZCD_EN#

(V)

Driver Supply Voltage, V

CIN

(V)

V

IH_ZCD_EN#_R

V

IL_ZCD_EN#_F

www.vishay.com

ELECTRICAL CHARACTERISTICS

Test condition: VIN = 13 V, DSBL# = V
natural convection cooling (All power loss and normalized power loss curves show SiC632 and SiC632A losses only unless otherwise stated)

DRV

= V

= 5 V, ZCD_EN# = 5 V, V

CIN

OUT

= 1 V, L

= 250 nH (DCR = 0.32 m), TA = 25 °C,

OUT

Vishay Siliconix

Fig. 18 - DSBL# Threshold vs. Temperature

Fig. 19 - DSBL# vs. Driver Input Voltage

Fig. 20 - DSBL# Pull-Down Current vs. Temperature

S20-0486-Rev. E, 29-Jun-2020

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Fig. 21 - ZCD_EN# Threshold vs. Driver Supply Voltage

80

70

(V)

60

VCIN

& I

50

VDVR

40

30

20

10

Driver Supply Current, I

0

-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)

Fig. 22 - Driver Shutdown Current vs. Temperature

390

380

(V)

370

VCIN

& I

360

VDVR

350

V

340

330

320

Driver Supply Current, I

310

-60 -40 -20 0 20 40 60 80 100 120 140

Temperature (°C)

Fig. 23 - Driver Supply Current vs. Temperature

10

For technical questions, contact: [e-mail]

PWM

V

DSBL#

= FLOAT

Document Number: 62992

= 0 V

www.vishay.com

V

IN

V

SWH

P

GND

V

IN

plane

P

GND

plane

PGND Plane

VSWH

Snubber

V

SWH

P

GND

plane

C

GND

C

VCIN

C

VDRV

P

G

N
D

PCB LAYOUT RECOMMENDATIONS

Step 1: VIN/GND Planes and Decoupling

Step 3: V

CIN/VDRV

SiC632, SiC632A

Vishay Siliconix

Input Filter

1. Layout VIN and P

planes as shown above

GND

2. Ceramic capacitors should be placed right between V
and P

, and very close to the device for best

GND

decoupling effect

3. Difference values / packages of ceramic capacitors
should be used to cover entire decoupling spectrum e.g.
1210, 0805, 0603, and 0402

4. Smaller capacitance value, closer to device V

pin(s)

IN

- better high frequency noise absorbing

Step 2: V

SWH

Plane

1. The V

IN

2. C

3. C

CIN/VDRV

very close to IC. It is recommended to connect two caps
separately

cap should be placed between pin 3 and pin 4

VCIN

(C

of driver IC) to achieve best noise filtering

GND

cap should be placed between pin 28 (P

VDRV

input filter ceramic cap should be placed

of

GND

driver IC) and pin 29 to provide maximum instantaneous
driver current for low side MOSFET during switching
cycle

4. For connecting C

analog ground, it is recommended

VCIN

to use large plane to reduce parasitic inductance

Step 4: BOOT Resistor and Capacitor Placement

Cboot

Rboot

1. Connect output inductor to DrMOS with large plane to
lower the resistance

2. If any snubber network is required, place the
components as shown above and the network can be
placed at bottom

S20-0486-Rev. E, 29-Jun-2020

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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

1. These components need to be placed very close to IC,
right between PHASE (pin 7) and BOOT (pin 5)

2. To reduce parasitic inductance, chip size 0402 can be
used

11

For technical questions, contact: [e-mail]

Document Number: 62992

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VIN plane

P

GND

plane

V

SWH

P

GND

V

IN

C

GND

V

SWH

P

GND

C

GND

Step 5: Signal Routing

C

GND

C

GND

P

GND

1. Route the PWM / ZCD_EN# / DSBL# / THWn signal
traces out of the top left corner next DrMOS pin 1

2. PWM signal is very important signal, both signal and
return traces need to pay special attention of not letting
this trace cross any power nodes on any layer

3. It is best to “shield” traces form power switching nodes,
e.g. V

4. GL (pin 27) has been connected with GL pad internally
and does not need to connect externally



Step 6: Adding Thermal Relief Vias

, to improve signal integrity

SWH

SiC632, SiC632A

Vishay Siliconix

1. Thermal relief vias can be added on the V
pads to utilize inner layers for high current and thermal
dissipation

2. To achieve better thermal performance, additional vias
can be put on VIN plane and P

3. V

pad is a noise source and not recommended to put

SWH

GND

plane

vias on this plane

4. 8 mil drill for pads and 10 mils drill for plane can be the
optional via size. Vias on pad may drain solder during
assembly and cause assembly issue. Please consult
with the assembly house for guideline



Step 7: Ground Connection

1. It is recommended to make single connection between
C

GND

and P

and this connection can be done on top

GND

layer

2. It is recommended to make the whole inner 1 layer (next
to top layer) ground plane and separate them into C
and P

GND

plane

3. These ground planes provide shielding between noise
source on top layer and signal trace on bottom layer

and P

IN

GND

GND







S20-0486-Rev. E, 29-Jun-2020

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12

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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Document Number: 62992

SiC632, SiC632A

V

OUT

P

GND

V

IN

www.vishay.com

Multi-Phases VRPower PCB Layout

Following is an example for 6 phase layout. As can be seen, all the VRPower stages are lined in X-direction compactly with
decoupling caps next to them. The inductors are placed as close as possible to the SiC632 and SiC632A to minimize the PCB
copper loss. Vias are applied on all PADs (VIN, P
performance are excellent. Large copper planes are used for all the high current loops, such as VIN, V
copper planes are duplicated in other layers to minimize the inductance and resistance. All the control signals are routed from
the SiC632 and SiC632A to a controller placed to the north of the power stage through inner layers to avoid the overlap of high
current loops. This achieves a compact design with the output from the inductors feeding a load located to the south of the
design as shown in the figure.

GND

, C

) of the SiC632 and SiC632A to ensure that both electrical and thermal

GND

Vishay Siliconix

, V

OUT

and P

GND

SWH

. These

V

P

IN

GND

Fig. 24 - Multi - Phase VRPower Layout Top View

V

OUT

Fig. 25 - Multi - Phase VRPower Layout Bottom View

S20-0486-Rev. E, 29-Jun-2020

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

13

For technical questions, contact: [e-mail]

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Document Number: 62992

SiC632, SiC632A

www.vishay.com

PRODUCT SUMMARY

Part number SiC632 SiC632A

Description

Input voltage min. (V) 4.5 4.5

Input voltage max. (V) 24 24

Continuous current rating max. (A) 50 50

Switch frequency max. (kHz) 1500 1500

Enable (yes / no) Yes Yes

Monitoring features - -

Protection UVLO, THDN UVLO, THDN

Light load mode ZCD ZCD

Pulse-width modulation (V) 5 3.3

Package type PowerPAK MLP55-31L PowerPAK MLP55-31L

Package size (W, L, H) (mm) 5.0 x 5.0 x 0.75 5.0 x 5.0 x 0.75

Status code 2 2

Product type VRPower (DrMOS) VRPower (DrMOS)

Applications Computer, industrial, networking Computer, industrial, networking

50 A power stage, 4.5 V

with ZCD mode

to 24 VIN, 5 V PWM

IN

50 A power stage, 4.5 VIN to 24 VIN, 3.3 V

Vishay Siliconix

PWM with ZCD mode

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?62992

S20-0486-Rev. E, 29-Jun-2020

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

.

14

For technical questions, contact: [e-mail]

Document Number: 62992

www.vishay.com

by marking

E

Pin 1 dot

Top view

D

MLP55-31L

(5 mm x 5 mm)

E2- 1

Bottom view

Side view

D2- 3 D2- 2

E2- 2

A

0.10 C A

2x

0.10 C B

2x

0.08 C

C

A

A2

A1

B

K7

56

D2- 1

E2- 3

D2-4

E2-4

K8

L

K3

K10

K1

K2

K4

K5

K6

K9

D2-5

K11

K12

F1

F2

K13

8x

1

8

1

16

23

31

24

15

9

8

0.10 C

3

0.10

M

CAB

0.05 C

F3

e/25x

b

31x

b1

31x

e3e2

e1/3x

M

PowerPAK® MLP55-31L Case Outline

Package Information

Vishay Siliconix

Revision: 21-Aug-17

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

DIM.

MIN. NOM. MAX. MIN. NOM. MAX.

MILLIMETERS INCHES

A 0.70 0.75 0.80 0.027 0.029 0.031

A1 0.00 - 0.05 0.000 - 0.002

A2 0.20 ref. 0.008 ref.

b 0.20 0.25 0.30 0.078 0.098 0.011

b1 0.15 0.20 0.25 0.006 0.008 0.010

D 4.90 5.00 5.10 0.193 0.196 0.200

e 0.50 BSC 0.019 BSC

e1 3.50 BSC 0.138 BSC

e2 1.50 BSC 0.060 BSC

e3 1.00 BSC 0.040 BSC

E 4.90 5.00 5.10 0.193 0.196 0.200

L 0.35 0.40 0.45 0.013 0.015 0.017

D2-1 0.98 1.03 1.08 0.039 0.041 0.043

D2-2 0.98 1.03 1.08 0.039 0.041 0.043

D2-3 1.87 1.92 1.97 0.074 0.076 0.078

D2-4 0.30 BSC 0.012 BSC

D2-5 1.05 1.10 1.15 0.041 0.043 0.045

E2-1 1.27 1.32 1.37 0.050 0.052 0.054

E2-2 1.93 1.98 2.03 0.076 0.078 0.080

E2-3 3.75 3.80 3.85 0.148 0.150 0.152

E2-4 0.45 BSC 0.018 BSC

F1 0.15 0.20 0.25 0.006 0.008 0.010

F2 0.20 ref. 0.008 ref.

F3 0.15 ref. 0.006 ref.

For technical questions, contact: [e-mail]

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

1

Document Number: 64909

www.vishay.com

Package Information

Vishay Siliconix

DIM.

K1 0.67 BSC 0.026 BSC

K2 0.22 BSC 0.008 BSC

K3 1.25 BSC 0.049 BSC

K4 0.10 BSC 0.004 BSC

K5 0.38 BSC 0.015 BSC

K6 0.12 BSC 0.005 BSC

K7 0.40 BSC 0.016 BSC

K8 0.40 BSC 0.016 BSC

K9 0.40 BSC 0.016 BSC

K10 0.85 BSC 0.033 BSC

K11 0.40 BSC 0.016 BSC

K12 0.40 BSC 0.016 BSC

K13 0.75 BSC 0.030 BSC

ECN: T17-0423-Rev. F, 21-Aug-17
DWG: 6025

Notes

1. Use millimeters as the primary measurement

2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994

3. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip

4. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body

5. Exact shape and size of this feature is optional

6. Package warpage max. 0.08 mm

7. Applied only for terminals

MIN. NOM. MAX. MIN. NOM. MAX.

MILLIMETERS INCHES

Revision: 21-Aug-17

For technical questions, contact: [e-mail]

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

2

Document Number: 64909

1.32

(E2-2)

1.98

(E2-3)

(L)

0.4

www.vishay.com

Top side transparent view

(not bottom view)

(D2-4)

1.03

1.03

(E3)

3.4

0.45

1

0.5 (e)

8

31

9

(D2-1)

(D2-2)

Recommended Land Pattern

®

MLP55-31L

1

0.35

0.15

5

8

0.58 0.5

0.3

0.35

(D2-5)

1.05

(D3) 0.3

(K2) 0.22

(K1) 0.67

(D2-3)

1.92

PowerPAK

24

23

4.2

(E2-1)

(b)

0.25

16

15

0.4

(L)

Land pattern for MLP55-31L

5

2.15

1.6

0.85

2.02

3.05

1.35

1.15

1.75

0.18

0.5

0.75

31

1.42

0.42.08

9

0.5

0.5

1.13

0.3

0.33

0.07

0.35

0.35

0.65

PAD Patt er n

Vishay Siliconix

0.57

0.3

1

24

15

0.75

0.75

0.33

23

0.3

3.5

16

0.65

0.3

All dimensions in millimeters

31

1

32

33

8

9

33

24

23

35

16

15

Component for MLP55-31L

Land pattern for MLP55-31L

Revision: 18-Oct-2019

1

Document Number: 66944

For technical questions, contact: [e-mail]

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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Legal Disclaimer Notice

www.vishay.com

Vishay

Disclaimer

ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.

Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.

Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
purpose, non-infringement and merchantability.

Statements regarding the suitability of products for certain types of applications are based on Vishay's knowledge of typical
requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements
about the suitability of products for a particular application. It is the customer's responsibility to validate that a particular product
with the properties described in the product specification is suitable for use in a particular application. Parameters provided in
datasheets and / or specifications may vary in different applications and performance may vary over time. All operating
parameters, including typical parameters, must be validated for each customer application by the customer's technical experts.
Product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited
to the warranty expressed therein.

Hyperlinks included in this datasheet may direct users to third-party websites. These links are provided as a convenience and
for informational purposes only. Inclusion of these hyperlinks does not constitute an endorsement or an approval by Vishay of
any of the products, services or opinions of the corporation, organization or individual associated with the third-party website.
Vishay disclaims any and all liability and bears no responsibility for the accuracy, legality or content of the third-party website
or for that of subsequent links.

Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please
contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by
any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.

© 2022 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED

Revision: 01-Jan-2022

1

Document Number: 91000