Vishay SST4117, SST4118, SST4119, 2N4117A, 2N4118A Schematics

...
2N/PN/SST4117A Series
Vishay Siliconix
N-Channel JFETs
2N4117A PN4117A SST4117 2N4118A PN4118A SST4118 2N4119A PN4119A SST4119
Part Number V
4117 0.6 to 1.8 40 70 30
4118 1 to 3 40 80 80
4119 2 to 6 40 100 200
FEATURES BENEFITS APPLICATIONS
D Ultra-Low Leakage: 0.2 pA D Very Low Current/Voltage Operation D Ultrahigh Input Impedance D Low Noise
GS(off)
(V) V
(BR)GSS
Min (V) gfs Min (mS)
I
DSS
Min (mA)
D Insignificant Signal Loss/Error Voltage
with High-Impedance Source
D Low Power Consumption (Battery) D Maximum Signal Output, Low Noise D High Sensitivity to Low-Level Signals
D High-Impedance Transducer
Amplifiers
D Smoke Detector Input D Infrared Detector Amplifier D Precision Test Equipment
DESCRIPTION
The 2N/PN/SST4117A series of n-channel JFETs provide ultra-high input impedance. These devices are specified with a 1-pA limit and typically operate at 0.2 pA. This makes them perfect choices for use as high-impedance sensitive front-end amplifiers.
TO-206AF
(TO-72)
S
1
23
D
Top View 2N4117A 2N4118A 2N4119A
C
4
G
D
S
G
TO-226AA
(TO-92)
1
2
3
Top View PN4117A PN4118A PN4119A
The hermetically sealed TO-206AF package allows full military processing per MIL-S-19500 (see Military Information). The TO-226A (TO-92) plastic package provides a low-cost option. The TO-236 (SOT-23) package provides surface-mount capability. Both the PN and SST series are available in tape-and-reel for automated assembly (see Packaging Information).
TO-236
(SOT-23)
1
D
G
3
S
2
Top View SST4117 (T7)* SST4118 (T8)* SST4119 (T9)*
*Marking Code for TO-236
For applications information see AN105.
Document Number: 70239 S-41231—Rev. G, 28-Jun-04
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2N/PN/SST4117A Series
V
VGS = 10 V
S
VDS = 10 V, VGS = 0 V
Common-Source
Common-Source
f = 1 MHz
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Gate-Source/Gate-Drain Voltage −40V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Forward Gate Current 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead Temperature (
Power Dissipation (case 25_C) :
Storage Temperature : (2N Prefix) 65 to 175_C. . . . . . . . . . . . . . . . . . .
(PN, SST Prefix) −55 to 150_C. . . . . . . . . . . . .
Operating Junction Temperature :
(2N Prefix) 55 to 175_C. . . . . . . . . . . . . . . . . . .
(PN, SST Prefix) −55 to 150_C. . . . . . . . . . . . .
Notes a. Derate 2 mW/_C above 25_C b. Derate 2.8 mW/_C above 25_C
SPECIFICATIONS (TA = 25_C UNLESS OTHERWISE NOTED)
Parameter Symbol Test Conditions TypaMin Max Min Max Min Max Unit
Static
Gate-Source Breakdown Voltage
Gate-Source Cutoff Voltage V
Saturation Drain Current I
Gate Reverse Current I
Gate Operating Current
Drain Cutoff Current
Gate-Source Forward Voltage
b
b
b
Dynamic
Common-Source Forward Transconductance
Common-Source Output Conductance
Common-Source Input Capacitance
Common-Source Reverse Transfer Capacitance
Equivalent Input Noise Voltage
Notes a. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. NT b. This parameter not registered with JEDEC.
b
V
(BR)GSS
GS(off)
DSS
GSS
I
D(off)
V
GS(F)
g
g
C
C
e
IG = 1 mA , VDS = 0 V
VDS = 10 V, ID = 1 nA
VDS = 10 V, VGS = 0 V
VGS = 20 V
V
= 0 V
DS
VGS = 20 V
V
= 0 V
DS
= 150_C
T
A
VGS = 10 V
VDS = 0 V
VGS = 10 V
V
= 0 V
DS
= 100_C
T
A
I
G
VDG = 15 V, ID = 30 mA
2N
PN 0.2 1 1 1
SST 0.2 10 10 10
PN/SST 0.03 2.5 2.5 2.5 nA
VDS = 10 V, VGS = 8 V 0.2
IG = 1 mA , VDS = 0 V 0.7 V
fs
os
V
= 10 V, VGS = 0 V
D
f = 1 kHz
2N/PN 1.2 3 3 3
iss
rss
n
VDS = 10 V
VGS = 0 V
f = 1 MHz
VDS = 10 V, VGS = 0 V
f = 1 kHz
SST 1.2
2N/PN 0.3 1.5 1.5 1.5
SST 0.3
1
/16” from case for 10 sec.) 300_C. . . . . . . . . . . . . . . . . . .
(2N Prefix) (PN, SST Prefix)
a
b
300 mW. . . . . . . . . . . . . . . . . . . . . .
350 mW. . . . . . . . . . . . . . . .
Limits
4117 4118 4119
70
40 40 40
0.6 1.8 1 3 2 6
90
30
0.2 1 1 1 pA
0.4 2.5 2.5 2.5 nA
0.2
210
70
3 5 10
15
240
80
200
600
mA
pA
pA
250
80
100
330
mS
pF
nV
Hz
V
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Document Number: 70239
S-41231—Rev. G, 28-Jun-04
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