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IRL640S, SiHL640S
Vishay Siliconix
Power MOSFET
PRODUCT SUMMARY
VDS (V) 200
R
()V
DS(on)
Q
max. (nC) 66
g
Q
(nC) 9.0
gs
Q
(nC) 38
gd
Configuration Single
D2PAK (TO-263)
= 5 V 0.18
GS
D
FEATURES
• Surface mount
• Available in tape and reel
• Dynamic dV/dt rating
• Repetitive avalanche rated
• Logic-level gate drive
•R
• Fast switching
• Material categorization: for definitions of
Note
*
specified at VGS = 4 V and 5 V
DS(on)
compliance please see www.vishay.com/doc?99912
Thi s datasheet pro vi des information about parts that are
RoHS-compliant and / or parts that are non-RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details.
G
DESCRIPTION
Third generation power MOSFETs from Vishay provide the
D
G
S
N-Channel MOSFET
S
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The D2PAK is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible
on-resistance in any existing surface mount package. The
D2PAK is suitable for high current applications because of
its low internal connection resistance and can dissipate up
to 2.0 W in a typical surface mount application.
ORDERING INFORMATION
Package D2PAK (TO-263) D2PAK (TO-263) D2PAK (TO-263)
Lead (Pb)-free and Halogen-free SiHL640S-GE3 SiHL640STRL-GE3
Lead (Pb)-free
IRL640SPbF IRL640STRLPbF
SiHL640S-E3 SiHL640STL-E3
a
a
a
SiHL640STRR-GE3
IRL640STRRPbF
SiHL640STR-E3
a
a
a
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage V
Gate-Source Voltage V
T
= 25 °C
Continuous Drain Current V
Pulsed Drain Current
a
at 5.0 V
GS
C
= 100 °C 11
C
DS
± 10
GS
I
D
IDM 68
Linear Derating Factor 1.0
Linear Derating Factor (PCB mount)
Single Pulse Avalanche Energy
Repetitive Avalanche Current
Repetitive Avalanche Energy
Maximum Power Dissipation T
Maximum Power Dissipation (PCB mount)
Peak Diode Recovery dV/dt
Operating Junction and Storage Temperature Range T
Soldering Temperature
d
e
b
a
a
= 25 °C
e
c
C
TA = 25 °C 3.1
E
AS
I
AR
E
AR
P
D
dV/dt 5.0 V/ns
, T
J
stg
for 10 s 300
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
= 50 V, starting TJ = 25 °C, L = 3.0 mH, Rg = 25 , IAS = 17 A (see fig. 12).
b. V
DD
17 A, dI/dt 150 A/μs, VDD VDS, TJ 150 °C.
c. I
SD
d. 1.6 mm from case.
e. When mounted on 1” square PCB (FR-4 or G-10 material).
S16-0763-Rev. D, 02-May-16
1
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
200
17
0.025
580 mJ
10 A
13 mJ
125
-55 to +150
Document Number: 91306
Available
Available
V
AT
W/°C
W
°C
Page 2
IRL640S, SiHL640S
D
S
G
S
D
G
www.vishay.com
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Maximum Junction-to-Ambient R
Maximum Junction-to-Ambient
(PCB mount)
a
Maximum Junction-to-Case (Drain) R
thJA
R
thJA
thJC
--62
--40
--1.0
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage V
V
Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 1 mA - 0.27 - V/°C
DS
Gate-Source Threshold Voltage V
Gate-Source Leakage I
Zero Gate Voltage Drain Current I
Drain-Source On-State Resistance R
Forward Transconductance g
DS
GS(th)
V
GSS
DSS
V
DS(on)
fs
V
Dynamic
Input Capacitance C
Reverse Transfer Capacitance C
Total Gate Charge Q
Gate-Drain Charge Q
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t
Internal Drain Inductance L
iss
- 400 -
oss
- 120 -
rss
g
--9.0
gs
--38
gd
d(on)
r
-44-
d(off)
-52-
f
D
V
Between lead,
6 mm (0.25") from
package and center of
Internal Source Inductance L
S
die contact
VGS = 0, ID = 250 μA 200 - - V
VDS = VGS, ID = 250 μA 1.0 - 2.0 V
= ± 10 V - - ± 100 nA
GS
VDS = 200 V, VGS = 0 V - - 25
= 160 V, VGS = 0 V, TJ = 125 °C - - 250
V
DS
= 5.0 V ID = 10 A
GS
= 4.0 V ID = 8.5 A
GS
VDS = 50 V, ID = 10 A
b
b
b
VGS = 0 V,
V
= 25 V,
DS
f = 1.0 MHz, see fig. 5
= 17 A, VDS = 160 V,
I
= 5.0 V
GS
V
R
= 4.6 , RD = 5.7 , see fig. 10
g
D
see fig. 6 and 13
= 100 V, ID = 17 A,
DD
b
b
Vishay Siliconix
°C/W
- - 0.18
- - 0.27
16 - - S
- 1800 -
--66
-8.0-
-83-
-4.5-
-7.5-
μA
pFOutput Capacitance C
nC Gate-Source Charge Q
ns
nH
Gate Input Resistance R
g
f = 1 MHz, open drain 0.3 - 1.2
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current I
Pulsed Diode Forward Current
a
Body Diode Voltage V
Body Diode Reverse Recovery Time t
Body Diode Reverse Recovery Charge Q
Forward Turn-On Time t
S
I
SM
SD
rr
rr
on
MOSFET symbol
showing the
integral reverse
p - n junction diode
TJ = 25 °C, IS = 17 A, VGS = 0 V
TJ = 25 °C, IF = 17 A, dI/dt = 100 A/μs
b
--17
--68
--2.0V
- 310 470 ns
b
-3.24.8μC
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
A
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width 300 μs; duty cycle 2 %.
S16-0763-Rev. D, 02-May-16
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
For technical questions, contact: hvm@vishay.com
2
Document Number: 91306
Page 3
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
IRL640S, SiHL640S
Vishay Siliconix
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 2 - Typical Output Characteristics, T
= 150 °C
C
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
S16-0763-Rev. D, 02-May-16
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Document Number: 91306
Page 4
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IRL640S, SiHL640S
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
S16-0763-Rev. D, 02-May-16
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Document Number: 91306
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Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
R
D
V
GS
R
g
D.U.T.
5 V
+
-
V
DS
V
DD
IRL640S, SiHL640S
Vishay Siliconix
Fig. 10a - Switching Time Test Circuit
V
DS
90 %
10 %
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig. 10b - Switching Time Waveforms
S16-0763-Rev. D, 02-May-16
5
Document Number: 91306
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Page 6
IRL640S, SiHL640S
R
g
I
AS
0.01 W
t
p
D.U.T.
L
V
DS
+
-
V
DD
5 V
Var y t
p
to obtain
required I
AS
www.vishay.com
t
V
DS
I
AS
Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms
Vishay Siliconix
V
DS
p
V
DD
5 V
V
G
Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit
S16-0763-Rev. D, 02-May-16
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Q
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
Q
G
GS
Q
GD
12 V
V
GS
50 kΩ
0.2 µF
3 mA
Charge
Current sampling resistors
6
For technical questions, contact: hvm@vishay.com
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
0.3 µF
+
V
D.U.T.
I
G
DS
-
I
D
Document Number: 91306
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IRL640S, SiHL640S
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
D.U.T.
+
-
R
g
Driver gate drive
P.W.
+
-
Period
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
• dV/dt controlled by R
• Driver same type as D.U.T.
I
controlled by duty factor “D”
•
SD
• D.U.T. - device under test
-
D =
g
Period
P.W.
+
+
V
DD
-
= 10 Va
V
GS
D.U.T. l
Reverse
recovery
current
D.U.T. V
Re-applied
voltage
Inductor current
Note
a. V
waveform
SD
Body diode forward
waveform
DS
Body diode forward drop
Ripple ≤ 5 %
= 5 V for logic level devices
GS
current
dI/dt
Diode recovery
dV/dt
V
DD
I
SD
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91306
S16-0763-Rev. D, 02-May-16
.
7
Document Number: 91306
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Page 8
TO-263AB (HIGH VOLTAGE)
(Datum A)
34
E
L1
4
D
L2
4
C
1
B
B
C
3
2
B
B
Package Information
Vishay Siliconix
A
A
5
H
Detail A
B
A
c2
Gauge
plane
0° to 8°
L
L3
L4
Detail “A”
Rotated 90° CW
scale 8:1
H
B
Seating plane
A1
2 x e
Lead tip
2 x b2
2 x b
0.010 A B
MM
Plating
(c)
Section B - B and C - C
c
± 0.004 B
5
b1, b3
(b, b2)
Scale: none
M
Base
metal
c1
A
E
D1
4
5
E1
View A - A
4
MILLIMETERS INCHES MILLIMETERS INCHES
DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.
A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 -
A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420
b 0.51 0.99 0.020 0.039 E1 6.22 - 0.245 -
b1 0.51 0.89 0.020 0.035 e 2.54 BSC 0.100 BSC
b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625
b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110
c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066
c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070
c2 1.14 1.65 0.045 0.065 L3 0.25 BSC 0.010 BSC
D 8.38 9.65 0.330 0.380 L4 4.78 5.28 0.188 0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
Document Number: 91364 www.vishay.com
Revision: 15-Sep-08 1
Page 9
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Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
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Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of
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particular product with the properties described in the product specification is suitable for use in a particular application.
Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s
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including but not limited to the warranty expressed therein.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
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© 2017 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED
Revision: 08-Feb-17
1
Document Number: 91000
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