Vishay IRFR010, SiHFR010 Data Sheet

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IRFR010, SiHFR010

Vishay Siliconix

Power MOSFET

PRODUCT SUMMARY

VDS (V) 50

R

()V

DS(on)

Q

(Max.) (nC) 10

g

Q

(nC) 2.6

gs

Q

(nC) 4.8

gd

Configuration Single

DPAK

(TO-252)

D

S

G

= 10 V 0.20

GS

G

N-Channel MOSFET

FEATURES

• Low Drive Current

• Surface Mount

• Fast Switching

• Ease of Paralleling

• Excellent Temperature Stability

• Material categorization: For definitions of compliance
please see www.vishay.com/doc?99912

D

DESCRIPTION

The power MOSFET technology is the key to Vishay’s
advanced line of power MOSFET transistors. The efficient
geometry and unique processing of this latest “State of the
Art” design achieves: very low on-state resistance
combined with high transconductance; superior reverse
energy and diode recovery dV/dt capability.

The power MOSFET transistors also feature all of the well
established advantages of MOSFET’S such as voltage

S

control, very fast switching, ease of paralleling and
temperature stability of the electrical parameters.

Surface mount packages enhance circuit performance by
reducing stray inductances and capacitance. The DPAK
(TO-252) surface mount package brings the advantages of
power MOSFET’s to high volume applications where PC
Board surface mounting is desirable. The surface mount
option IRFR9012, SiHFR9012 is provided on 16 mm tape.
The straight lead option IRFU9012, SiHFU9012 of the device
is called the IPAK (TO-251).

They are well suited for applications where limited heat
dissipation is required such as, computers and peripherals,
telecommunication equipment, dc-to-dc converters, and a
wide range of consumer products.

ORDERING INFORMATION

Package DPAK (TO-252)

Lead (Pb)-free

IRFR010PbF

SiHFR010-E3

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage V

Gate-Source Voltage V

T

= 25 °C

Continuous Drain Current V

Pulsed Drain Current

Avalanche Current

Linear Derating Factor 0.20 W/°C

Maximum Power Dissipation T

Peak Diode Recovery dV/dt

Operating Junction and Storage Temperature Range T

Soldering Recommendations (Peak Temperature)

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. V

= 25 V, starting TJ = 25 °C, L = 100 μH, Rg = 25 .

DD

 8.2 A, dI/dt  130 A/μs, VDD  40 V, TJ  150 °C.

c. I

SD

d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).

S13-0167-Rev. B, 04-Feb-13

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a

b

c

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at 10 V

GS

d

C

T

= 100 °C 5.2

C

= 25 °C P

C

for 10 s 300

1

DS

± 20

GS

I

D

IDM 33

I

AS

D

dV/dt 2.0 V/ns

, T

J

stg

50

8.2

1.5

25 W

- 55 to + 150

Document Number: 91420

V

A

°C

IRFR010, SiHFR010

D

S

G

S

D

G

www.vishay.com

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

Maximum Junction-to-Ambient R

Maximum Junction-to-Case (Drain) R

thJA

thCS

thJC

- - 110

-1.7-

--5.0

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-Source Breakdown Voltage V

Gate-Source Threshold Voltage V

Gate-Source Leakage I

Zero Gate Voltage Drain Current I

Drain-Source On-State Resistance R

Forward Transconductance g

DS

GS(th)

V

GSS

DSS

VGS = 10 V ID = 4.6 A

DS(on)

fs

Dynamic

Input Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Gate-Drain Charge Q

Turn-On Delay Time t

Rise Time t

Turn-Off Delay Time t

Fall Time t

Internal Drain Inductance L

iss

- 150 -

oss

-29-

rss

g

-1.82.6

gs

-3.24.8

gd

d(on)

r

-1218

d(off)

-2335

f

D

Between lead,
6 mm (0.25") from
package and center of

Internal Source Inductance L

S

die contact

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current I

Pulsed Diode Forward Current

a

Body Diode Voltage V

Body Diode Reverse Recovery Time t

Body Diode Reverse Recovery Charge Q

Forward Turn-On Time t

S

I

SM

SD

rr

rr

on

MOSFET symbol
showing the

integral reverse
p - n junction diode

TJ = 25 °C, IF = 7.3 A, dI/dt = 100 A/μs

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width  300 μs; duty cycle  2 %.

VGS = 0 V, ID = 250 μA 50 - - V

VDS = VGS, ID = 250 μA 2.0 - 4.0 V

= ± 20 V - - ± 500 nA

GS

VDS = 50 V, VGS = 0 V - - 250

V

= 40 V, VGS = 0 V, TJ = 125 °C - - 1000

DS

b

VDS  50 V, ID = 3.6 A 2.1 3.1 - S

VGS = 0 V,

V

= 25 V,

DS

f = 1.0 MHz, see fig. 10

= 7.3 A, VDS = 40 V,

I

= 10 V

V

GS

V

R

= 24 , RD = 3.3 , see fig. 10

g

TJ = 25 °C, IS = 8.2 A, VGS = 0 V

D

see fig. 6 and 13

= 25 V, ID = 7.3 A,

DD

c

b

b

b

b

Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

Vishay Siliconix

°C/WCase-to-Sink R

- 0.16 0.20 

- 250 -

-6.710

-1117

-3350

-4.5-

-7.5-

--8.2

--33

--1.6V

41 86 190 ns

0.15 0.33 0.78 μC

μA

pFOutput Capacitance C

nC Gate-Source Charge Q

ns

nH

A

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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

IRFR010, SiHFR010

Vishay Siliconix

Fig. 1 - Typical Output Characteristics

Fig. 2 - Typical Output Characteristics

Fig. 3 - Typical Transfer Characteristics

Fig. 4 - Normalized On-Resistance vs. Temperature

S13-0167-Rev. B, 04-Feb-13

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IRFR010, SiHFR010

Vishay Siliconix

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

Fig. 7 - Typical Source-Drain Diode Forward Voltage

Fig. 8 - Maximum Safe Operating Area

S13-0167-Rev. B, 04-Feb-13

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Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

R

D

V

GS

R

G

D.U.T.

10 V

+

-

V

DS

V

DD

V

DS

90 %

10 %

V

GS

t

d(on)

t

r

t

d(off)

t

f

Fig. 9 - Maximum Drain Current vs. Case Temperature

IRFR010, SiHFR010

Vishay Siliconix

Fig. 10a - Switching Time Test Circuit

Fig. 10 - Breakdown Voltage vs. Temperature

Fig. 10b - Switching Time Waveforms

S13-0167-Rev. B, 04-Feb-13

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Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

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R

G

I

AS

0.01 Ω

t

p

D.U.T

L

V

DS

+

-

V

DD

10 V

Var y t

p

to obtain

required I

AS

Q

GS

Q

GD

Q

G

V

G

Charge

V

GS

IRFR010, SiHFR010

Vishay Siliconix

V

DS

t

p

V

DS

I

AS

V

DD

Fig. 12a - Unclamped Inductive Test Circuit

Fig. 12c - Typical Transconductance vs. Drain Current

Fig. 12b - Unclamped Inductive Waveforms

S13-0167-Rev. B, 04-Feb-13

Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

Current regulator

Same type as D.U.T.

50 kΩ

0.2 µF

12 V

V

GS

3 mA

Current sampling resistors

6

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0.3 µF

+

V

D.U.T.

I

G

I

DS

-

D

Document Number: 91420

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P.W.

Period

dI/dt

Diode recovery

dV/dt

Ripple ≤ 5 %

Body diode forward drop

Re-applied
voltage

Reverse
recovery
current

Body diode forward

current

V

GS

= 10 Va

I

SD

Driver gate drive

D.U.T. l

SD

waveform

D.U.T. V

DS

waveform

Inductor current

D =

P.W.

Period

+

-

+

+

+

-

-

-

Peak Diode Recovery dV/dt Test Circuit

V

DD

• dV/dt controlled by R

g

• Driver same type as D.U.T.

•

I

SD

controlled by duty factor “D”

• D.U.T. - device under test

D.U.T.

Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance

current transformer

R

g

Note

a. V

GS

= 5 V for logic level devices

V

DD

IRFR010, SiHFR010

Vishay Siliconix

Fig. 14 - For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91420

S13-0167-Rev. B, 04-Feb-13

.

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Package Information

Vishay Siliconix

TO-252AA Case Outline

E

b3

L3

A

C2

DIM. MIN. MAX. MIN. MAX.

MILLIMETERS INCHES

A 2.18 2.38 0.086 0.094

A1 - 0.127 - 0.005

b 0.64 0.88 0.025 0.035

D

H

b2 0.76 1.14 0.030 0.045

b3 4.95 5.46 0.195 0.215

C 0.46 0.61 0.018 0.024

C2 0.46 0.89 0.018 0.035

L4

L5

L

D 5.97 6.22 0.235 0.245

D1 4.10 - 0.161 -

E 6.35 6.73 0.250 0.265

b

e1

b2

e

C

A1

E1 4.32 - 0.170 -

H 9.40 10.41 0.370 0.410

e 2.28 BSC 0.090 BSC

e1 4.56 BSC 0.180 BSC

gage plane height (0.5 mm)

L 1.40 1.78 0.055 0.070

L3 0.89 1.27 0.035 0.050

D1

L4 - 1.02 - 0.040

L5 1.01 1.52 0.040 0.060

ECN: T16-0236-Rev. P, 16-May-16

E1

DWG: 5347

Notes

• Dimension L3 is for reference only.

Revision: 16-May-16

1

Document Number: 71197

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RECOMMENDED MINIMUM PADS FOR DPAK (TO-252)

0.224

(5.690)

Application Note 826

Vishay Siliconix

0.243
(6.180)

Return to Index

Return to Index

0.420
(10.668)

0.180

(4.572)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.087

0.090

0.055

(1.397)

(2.202)

(2.286)

APPLICATION NOTE

Document Number: 72594 www.vishay.com
Revision: 21-Jan-08 3

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Document Number: 91000