Vishay IRFP460B, SiHG460B Data Sheet

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TO-247AC
G
D
S
IRFP460B, SiHG460B
Vishay Siliconix
D Series Power MOSFET
PRODUCT SUMMARY
VDS (V) at TJ max. 550
R
max. at 25 °C ()VGS = 10 V 0.25
DS(on)
Q
max. (nC) 170
g
Q
(nC) 14
gs
Q
(nC) 28
gd
Configuration Single
G
N-Channel MOSFET
FEATURES
•Optimal Design
- Low Area Specific On-Resistance
- Low Input Capacitance (C
iss
)
- Reduced Capacitive Switching Losses
- High Body Diode Ruggedness
- Avalanche Energy Rated (UIS)
• Optimal Efficiency and Operation
D
- Low Cost
- Simple Gate Drive Circuitry
- Low Figure-of-Merit (FOM): Ron x Q
g
- Fast Switching
• Material categorization: For definitions of compliance please see www.vishay.com/doc?99912
Note
* Lead (Pb)-containing terminations are not RoHS-compliant.
S
Exemptions may apply.
APPLICATIONS
• Consumer Electronics
- Displays (LCD or Plasma TV)
• Server and Telecom Power Supplies
- SMPS
• Industrial
- Welding
- Induction Heating
- Motor Drives
• Battery Chargers
•SMPS
- Power Factor Correction (PFC)
ORDERING INFORMATION
Package TO-247AC Lead (Pb)-free IRFP460BPbF
Lead (Pb)-free and Halogen-free SiHG460B-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage V
Gate-Source Voltage AC (f > 1 Hz) 30
= 25 °C
T
Continuous Drain Current (T
Pulsed Drain Current Linear Derating Factor 2.2 W/°C Single Pulse Avalanche Energy Maximum Power Dissipation P Operating Junction and Storage Temperature Range T Drain-Source Voltage Slope T Reverse Diode dV/dt Soldering Recommendations (Peak Temperature) for 10 s 300
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
= 50 V, starting TJ = 25 °C, L = 10 mH, Rg = 25 , IAS = 7.5 A.
b. V
DD
c. 1.6 mm from case.
ID, starting TJ = 25 °C.
d. I
SD
S12-0812-Rev. B, 16-Apr-12
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
= 150 °C) VGS at 10 V
J
a
b
d
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
C
= 100 °C 13
C
= 125 °C
J
1
DS
V
GS
I
D
IDM 62
E
AS
D
, T
J
stg
dV/dt
500
± 20
20
281 mJ 278 W
- 55 to + 150 °C 24
0.36
c
Document Number: 91502
V Gate-Source Voltage
AT
V/ns
°C
S
D
G
IRFP460B, SiHG460B
www.vishay.com
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient R
Maximum Junction-to-Case (Drain)
thJA
R
thJC
-40
-0.45
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage V
V
Temperature Coefficient
DS
Gate-Source Threshold Voltage (N) V
Gate-Source Leakage I
Zero Gate Voltage Drain Current I
Drain-Source On-State Resistance R
Forward Transconductance g
Dynamic
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Effective output capacitance, energy
a
related
Effective output capacitance, time
b
related
Total Gate Charge Q
Gate-Drain Charge Q
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t
Gate Input Resistance R
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current I
Pulsed Diode Forward Current I
Diode Forward Voltage V
Reverse Recovery Time t
Reverse Recovery Charge Q
Reverse Recovery Current I
Notes
a. C b. C
is a fixed capacitance that gives the same energy as C
oss(er)
is a fixed capacitance that gives the same charging time as C
oss(tr)
DS
V
DS/TJ
GS(th)
V
GSS
DSS
V
DS(on)
fs
iss
- 152 -
oss
-13-
rss
C
o(er)
C
o(tr)
g
-28-
gd
d(on)
r
- 117 176
d(off)
- 56 112
f
g
S
MOSFET symbol showing the integral reverse
SM
SD
rr
rr
RRM
p - n junction diode
VGS = 0 V, ID = 250 μA 500 - - V
Reference to 25 °C, I
= 250 μA
D
VDS = VGS, ID = 250 μA 2 - 4 V
= ± 20 V - - ± 100 nA
GS
VDS = 500 V, VGS = 0 V - - 1
= 400 V, VGS = 0 V, TJ = 125 °C - - 10
V
DS
= 10 V ID = 10 A - 0.2 0.25
GS
VDS = 50 V, ID = 10 A - 12 - S
VGS = 0 V,
V
= 100 V,
DS
f = 1 MHz
VGS = 0 V,
V
= 0 V to 400 V
DS
V
= 10 V ID = 10 A, VDS = 400 V
GS
= 400 V, ID = 10 A,
V
DD
V
= 10 V, Rg = 9.1
GS
f = 1 MHz, open drain - 1.8 -
TJ = 25 °C, IS = 10 A, VGS = 0 V - - 1.2 V
TJ = 25 °C, IF = IS = 10 A,
dI/dt = 100 A/μs, V
while VDS is rising from 0 % to 80 % VDS.
oss
while VDS is rising from 0 % to 80 % VDS.
oss
= 20 V
R
Vishay Siliconix
°C/W
-0.56-
- 3094 -
- 131 -
- 189 -
- 85 170
-2450
-3162
--20
--80
- 437 - ns
-5.9-μC
-25-A
V/°C
μA
pF
nC Gate-Source Charge Qgs -14-
ns
A
S12-0812-Rev. B, 16-Apr-12
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
2
Document Number: 91502
11 V
0
20
40
60
80
VDS, Drain-to-Source Voltage (V)
I
D
, Drain-to-Source Current (A)
0 5 10 15 20 25 30
TJ = 25 °C
TOP 15 V
14 V 13 V 12 V 11 V 10 V
9 V 8 V 7 V 6 V
BOTTOM 5 V
11 V
0
10
20
30
40
VDS, Drain-to-Source Voltage (V)
I
D
, Drain-to-Source Current (A)
0 5 10 15 20 25 30
TJ = 150 °C
TOP 15 V
14 V 13 V 12 V 11 V 10 V
9 V 8 V 7 V 6 V
BOTTOM 5 V
TJ, Junction Temperature (°C)
R
DS(on)
, Drain-to-Source
- 60 - 40 - 20020 40 60 80 100 120
140
160
On Resistance (Normalized)
0
0.5
1
1.5
2
2.5
3
VGS = 10 V
ID = 10 A
ġ
ġ
ġ
ġ
ġ
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
IRFP460B, SiHG460B
Vishay Siliconix
Fig. 1 - Typical Output Characteristics
Fig. 2 - Typical Output Characteristics
80
TJ = 25 °C
60
40
TJ = 150 °C
Fig. 4 - Normalized On-Resistance vs. Temperature
10 000
C
10
iss
C
oss
C
rss
V
= 0 V, f = 1 MHz
GS
= Cgs + Cgd, Cds Shorted
C
iss
= C
C
rss
gd
C
= Cds + C
oss
gd
1000
100
Capacitance (pF)
1
0 100 200 300 400 500
VDS, Drain-to-Source Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
24
VDS = 400 V V
20
DS
V
DS
16
12
= 250 V = 100 V
S12-0812-Rev. B, 16-Apr-12
20
, Drain-to-Source Current (A)
D
I
0
Fig. 3 - Typical Transfer Characteristics
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
0 5 10 15 20
VGS, Gate-to-Source Voltage (V)
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
25
3
8
, Gate-to-Source Voltage (V)
4
GS
V
0
0306090
120
150 180
Qg, Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Document Number: 91502
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0.1
1
10
100
VSD, Source-Drain Voltage (V)
I
SD
, Reverse Drain Current (A)
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
ġ
ġ
ġ
VGS = 0 V
TJ = 25 °C
TJ = 150 °C
VDS, Drain-to-Source Voltage (V)
I
D
, Drain Current (A)
0.1
1
10
100
1000
1 10 100 1000
* V
GS
> minimum VGS at which R
DS(on)
is specied
Operation in this area limited by R
DS(on)
BVDSS Limited
TC = 25 °C T
J
= 150 °C
Single Pulse
100 μs
1 ms
10 ms
Limited by R
DS(on)
*
TJ, Case Temperature (°C)
I
D
, Drain Current (A)
25 50 75 100 125 150
20
16
12
8
4
0
TJ, Junction Temperature (°C)
V
DS
, Drain-to-Source
- 60 0 160
Brakdown Voltage (V)
- 40 - 20 20 40 60 80 100 120 140
475
500
525
550
575
600
625
0.01
0.1
1
0.0001 0.001 0.01 0.1 1
Normalized Effective Transient
Thermal Impedance
Pulse Time (s)
Duty Cycle = 0.5
0.2
0.1
0.02
0.05
Single Pulse
IRFP460B, SiHG460B
Vishay Siliconix
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10 - Temperature vs. Drain-to-Source Voltage
S12-0812-Rev. B, 16-Apr-12
Fig. 11 - Normalized Thermal Transient Impedance, Junction-to-Case
4
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Document Number: 91502
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Pulse width 1 µs Duty factor 0.1 %
R
D
V
GS
R
G
D.U.T.
10 V
+
-
V
DS
V
DD
90 %
10 %
t
d(on)
t
r
t
d(off)
t
f
Q
GS
Q
GD
Q
G
V
G
Charge
10 V
IRFP460B, SiHG460B
Vishay Siliconix
Fig. 12 - Switching Time Test Circuit
V
DS
V
GS
Fig. 13 - Switching Time Waveforms
Var y tp to obtain required I
AS
R
G
10 V
Fig. 16 - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
50 kΩ
0.2 µF
12 V
V
GS
V
L
DS
D.U.T
I
AS
t
p
0.01 Ω
+
V
DD
-
Fig. 17 - Gate Charge Test Circuit
0.3 µF
D.U.T.
3 mA
I
G
Current sampling resistors
I
D
+
V
DS
-
Fig. 14 - Unclamped Inductive Test Circuit
Fig. 15 - Unclamped Inductive Waveforms
S12-0812-Rev. B, 16-Apr-12
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
V
DS
t
p
V
DS
I
AS
V
DD
5
Document Number: 91502
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
www.vishay.com
IRFP460B, SiHG460B
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
D.U.T.
+
-
R
g
Driver gate drive
P.W.
+
-
Period
Circuit layout considerations
Low stray inductance
Ground plane
Low leakage inductance
current transformer
dV/dt controlled by R
Driver same type as D.U.T.
I
controlled by duty factor “D”
SD
D.U.T. - device under test
-
D =
g
P.W.
Period
+
+
V
DD
-
V
= 10 Va
GS
D.U.T. l
Reverse recovery current
D.U.T. V
Re-applied voltage
Inductor current
Note
a. V
waveform
SD
Body diode forward
waveform
DS
Body diode forward drop
Ripple 5 %
= 5 V for logic level devices
GS
current
dI/dt
Diode recovery
dV/dt
V
DD
I
SD
Fig. 18 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91502
S12-0812-Rev. B, 16-Apr-12
.
6
Document Number: 91502
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
www.vishay.com
0.10 AC
M M
E
E/2
(2)
(4)
R/2
B
2 x R
S
D
See view B
2 x e
b4
3 x b
2 x b2
L
C
L1
1
2
3
Q
D
A
A2
A
A
A1
C
Ø k BD
M M
A
ØP
(Datum B)
ØP1
D1
4
E1
0.01 BD
M M
View A - A
Thermal pad
D2
DDE E
C
C
View B
(b1, b3, b5)
Base metal
c1
(b, b2, b4)
Section C - C, D - D, E - E
(c)
Planting
4
3
5
7
4
4
4
Lead Assignments
1. Gate
2. Drain
3. Source
4. Drain
Package Information
Vishay Siliconix
TO-247AC (High Voltage)
MILLIMETERS INCHES MILLIMETERS INCHES
DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.
A 4.58 5.31 0.180 0.209 D2 0.51 1.30 0.020 0.051 A1 2.21 2.59 0.087 0.102 E 15.29 15.87 0.602 0.625 A2 1.17 2.49 0.046 0.098 E1 13.72 - 0.540 -
b 0.99 1.40 0.039 0.055 e 5.46 BSC 0.215 BSC b1 0.99 1.35 0.039 0.053 Ø k 0.254 0.010 b2 1.53 2.39 0.060 0.094 L 14.20 16.25 0.559 0.640 b3 1.65 2.37 0.065 0.093 L1 3.71 4.29 0.146 0.169 b4 2.42 3.43 0.095 0.135 N 7.62 BSC 0.300 BSC b5 2.59 3.38 0.102 0.133 Ø P 3.51 3.66 0.138 0.144
c 0.38 0.86 0.015 0.034 Ø P1 - 7.39 - 0.291 c1 0.38 0.76 0.015 0.030 Q 5.31 5.69 0.209 0.224
D 19.71 20.82 0.776 0.820 R 4.52 5.49 0.178 0.216 D1 13.08 - 0.515 - S 5.51 BSC 0.217 BSC
ECN: X13-0103-Rev. D, 01-Jul-13 DWG: 5971
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Contour of slot optional.
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body.
4. Thermal pad contour optional with dimensions D1 and E1.
5. Lead finish uncontrolled in L1.
6. Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154").
7. Outline conforms to JEDEC outline TO-247 with exception of dimension c.
8. Xian and Mingxin actually photo.
Revision: 01-Jul-13
Document Number: 91360
1
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Disclaimer
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Revision: 13-Jun-16
1
Document Number: 91000
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