Power MOSFET
IRFP460A, SiHFP460A
Vishay Siliconix
PRODUCT SUMMARY
VDS (V) 500
R
(Ω)V
DS(on)
Q
(Max.) (nC) 105
g
Q
(nC) 26
gs
Q
(nC) 42
gd
Configuration Single
TO-247
= 10 V 0.27
GS
D
FEATURES
• Low Gate Charge Qg Results in Simple Drive
Requirement
• Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
• Fully Characterized Capacitance and Avalanche Voltage
and Current
• Effective C
• Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
• Switch Mode Power Supply (SMPS)
• Uninterruptable Power Supply
G
S
D
G
N-Channel MOSFET
S
• High Speed Power Switching
TYPICAL SMPS TOPOLOGIES
• Full Bridge
• PFC Boost
ORDERING INFORMATION
Package TO-247
Lead (Pb)-free
SnPb
IRFP460APbF
SiHFP460A-E3
IRFP460A
SiHFP460A
Specified
oss
Available
RoHS*
COMPLIANT
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage V
Gate-Source Voltage V
T
= 25 °C
Continuous Drain Current V
Pulsed Drain Current
a
at 10 V
GS
C
= 100 °C 13
C
DS
± 30
GS
I
D
IDM 80
Linear Derating Factor 2.2 W/°C
Single Pulse Avalanche Energy
Repetitive Avalanche Current
Repetitive Avalanche Energy
Maximum Power Dissipation T
Peak Diode Recovery dV/dt
b
a
a
= 25 °C P
c
C
Operating Junction and Storage Temperature Range T
E
AS
I
AR
E
AR
D
dV/dt 3.8 V/ns
, T
J
stg
Soldering Recommendations (Peak Temperature) for 10 s 300
Mounting Torque 6-32 or M3 screw
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting T
c. I
SD
= 25 °C, L = 4.3 mH, Rg = 25 Ω, IAS = 20 A (see fig. 12).
J
≤ 20 A, dI/dt ≤ 125 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91234 www.vishay.com
S09-1284-Rev. B, 13-Jul-09 1
500
20
960 mJ
20 A
28 mJ
280 W
- 55 to + 150
d
10 lbf · in
1.1 N · m
V
AT
°C
IRFP460A, SiHFP460A
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient R
Maximum Junction-to-Case (Drain) R
thJA
thCS
thJC
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage V
Temperature Coefficient ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.61 -
V
DS
Gate-Source Threshold Voltage V
Gate-Source Leakage I
Zero Gate Voltage Drain Current I
Drain-Source On-State Resistance R
Forward Transconductance g
Dynamic
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Output Capacitance C
Effective Output Capacitance C
Total Gate Charge Q
Gate-Drain Charge Q
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current I
Pulsed Diode Forward Current
a
Body Diode Voltage V
Body Diode Reverse Recovery Time t
Body Diode Reverse Recovery Charge Q
Forward Turn-On Time t
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
c. C
eff. is a fixed capacitance that gives the same charging time as C
oss
DS
GS(th)
V
GSS
DSS
VGS = 10 V ID = 12 A
DS(on)
fs
iss
- 480 -
oss
-18-
rss
oss
eff. VDS = 0 V to 400 V
oss
g
--26
gs
--42
gd
d(on)
r
-45-
d(off)
-39-
f
S
I
SM
SD
rr
rr
on
V
V
GS
V
GS
R
MOSFET symbol
showing the
integral reverse
p - n junction diode
TJ = 25 °C, IF = 20 A, dI/dt = 100 A/µs
-40
0.24 -
°C/WCase-to-Sink, Flat, Greased Surface R
-0.45
VGS = 0 V, ID = 250 µA 500 - -
VDS = VGS, ID = 250 µA 2.0 - 4.0 V
= ± 30 V - - ± 100 nA
GS
VDS = 500 V, VGS = 0 V - - 25
= 400 V, VGS = 0 V, TJ = 125 °C - - 250
DS
VDS = 50 V, ID = 12 A
VGS = 0 V,
V
= 25 V,
DS
f = 1.0 MHz, see fig. 5
= 1.0 V, f = 1.0 MHz 4430
V
DS
= 0 V
V
= 400 V, f = 1.0 MHz 130
DS
b
b
c
--0.27Ω
11 - -
- 3100 -
140
- - 105
= 20 A, VDS = 400 V,
I
= 10 V
D
see fig. 6 and 13
b
-18-
V
= 250 V, ID = 20 A,
DD
= 4.3 Ω, RD = 13 Ω, see fig. 10
G
G
TJ = 25 °C, IS = 20A, VGS = 0 V
b
D
S
b
-55-
--20
--80
--1.8V
- 480 710 ns
b
-5.07.5µC
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
while VDS is rising from 0 % to 80 % VDS.
oss
V
V/°C
µA
S
pF
nC Gate-Source Charge Q
ns
A
www.vishay.com Document Number: 91234
2 S09-1284-Rev. B, 13-Jul-09
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
IRFP460A, SiHFP460A
Vishay Siliconix
, Drain-to-Source Current (A)
D
I
91234_01
2
10
10
To p
Bottom
V
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
4.5 V
GS
1
0.1
0.1
1
VDS, Drain-to-Source Voltage (V)
Fig. 1 - Typical Output Characteristics
2
10
10
To p
Bottom
V
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
4.5 V
GS
4.5 V
20 µs Pulse Width
T
= 25 °C
C
10
2
10
150 °C
10
25 °C
1
, Drain-to-Source Current (A)
D
I
91234_03
0.1
5.0 6.0 7.0 8.0 9.04.0
V
Gate-to-Source Voltage (V)
,
GS
2
10
20 µs Pulse Width
= 50 V
V
DS
Fig. 3 - Typical Transfer Characteristics
3.0
I
= 20 A
D
V
= 10 V
GS
2.5
2.0
1.5
(Normalized)
1.0
0.5
, Drain-to-Source On Resistance
DS(on)
0.0
R
91234_04
- 60 - 40 - 20 0 20 40
T
Junction Temperature (°C)
,
J
60
80 100
120
Fig. 4 - Normalized On-Resistance vs. Temperature
140 160
, Drain-to-Source Current (A)
D
I
91234_02
20 µs Pulse Width
= 150 °C
T
1
1
V
Drain-to-Source Voltage (V)
,
DS
C
10 10
Fig. 2 - Typical Output Characteristics
4.5 V
2
Document Number: 91234 www.vishay.com
S09-1284-Rev. B, 13-Jul-09 3
IRFP460A, SiHFP460A
Vishay Siliconix
5
10
4
10
3
10
2
10
Capacitance (pF)
V
= 0 V, f = 1 MHz
GS
= Cgs + Cgd, Cds Shorted
C
iss
= C
C
rss
gd
C
= Cds + C
oss
gd
C
iss
C
oss
10
C
rss
91234_05
1
1
10
V
Drain-to-Source Voltage (V)
,
DS
2
10
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
20
ID = 20 A
V
= 400 V
16
V
12
V
DS
= 100 V
= 250 V
DS
DS
2
10
10
150 °C
25 °C
1
, Reverse Drain Current (A)
SD
I
91234_07
0.1
0.2
0.80.60.4
VSD, Source-to-Drain Voltage (V)
1.0
3
10
V
= 0 V
GS
1.2 1.4 1.6
Fig. 7 - Typical Source-Drain Diode Forward Voltage
3
10
Operation in this area limited
by R
DS(on)
2
10
µs
10
8
4
, Gate-to-Source Voltage (V)
GS
V
91234_06
0
0
40
20
QG, Total Gate Charge (nC)
For test circuit
see figure 13
8060
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
100
, Drain Current (A)
D
I
91234_08
10
TC = 25 °C
= 150 °C
T
J
Single Pulse
1
10
2
10
VDS, Drain-to-Source Voltage (V)
Fig. 8 - Maximum Safe Operating Area
100 µs
1 ms
10 ms
10
3
4
10
www.vishay.com Document Number: 91234
4 S09-1284-Rev. B, 13-Jul-09
IRFP460A, SiHFP460A
Vishay Siliconix
R
D.U.T.
D
+
V
-
DD
V
DS
V
20
GS
R
G
15
10
, Drain Current (A)
D
I
5
0
25 1501251007550
91234_09
TC, Case Temperature (°C)
Fig. 9 - Maximum Drain Current vs. Case Temperature
1
)
thJC
Thermal Response (Z
91234_11
10
10
0.1
-2
-3
10
D = 0.5
0.2
0.1
0.05
0.02
0.01
-5
Single Pulse
(Thermal Response)
-4
10
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
-3
10
-2
10
t1, Rectangular Pulse Duration (S)
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
V
DS
90 %
10 %
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig. 10b - Switching Time Waveforms
P
DM
t
1
t
1/t2
thJC
2
+ T
C
Notes:
1. Duty Factor, D = t
2. Peak Tj = PDM x Z
0.1 1
V
DS
R
V
G
20 V
15 V
t
p
DS
L
D.U.T.
I
AS
0.01 Ω
t
p
Driver
+
V
A
DD
-
I
AS
Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms
Document Number: 91234 www.vishay.com
S09-1284-Rev. B, 13-Jul-09 5
IRFP460A, SiHFP460A
Vishay Siliconix
2400
2000
To p
Bottom
I
D
8.9 A
13 A
20 A
1600
1200
800
400
, Single Pulse Avalanche Energy (mJ)
0
AS
E
91234_12c
25 150
50
Starting T
, Junction Temperature (°C)
J
10075
125
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Q
10 V
V
Q
GS
G
G
Q
GD
Charge
Fig. 13a - Basic Gate Charge Waveform
, Avalanche Voltage (V)
DSav
V
91234_12d
620
600
580
560
540
020
4
, Avalanche Current (A)
I
AV
128
16
Fig. 12d - Typical Drain-to-Source Voltage vs.
Avalanche Current
Current regulator
Same type as D.U.T.
50 kΩ
0.2 µF
12 V
V
GS
0.3 µF
D.U.T.
3 mA
I
G
Current sampling resistors
I
D
+
V
DS
-
Fig. 13b - Gate Charge Test Circuit
www.vishay.com Document Number: 91234
6 S09-1284-Rev. B, 13-Jul-09
IRFP460A, SiHFP460A
Peak Diode Recovery dV/dt Test Circuit
Vishay Siliconix
D.U.T.
+
-
R
G
Driver gate drive
P.W.
+
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
-
• dV/dt controlled by R
• Driver same type as D.U.T.
• I
controlled by duty factor "D"
SD
• D.U.T. - device under test
Period
-
D =
G
P.W.
Period
+
+
V
DD
-
V
= 10 V*
GS
waveform
SD
Body diode forward
current
waveform
DS
Body diode forward drop
Ripple ≤ 5 %
= 5 V for logic level devices
GS
Diode recovery
dV/dt
dI/dt
V
DD
I
SD
Reverse
recovery
current
Re-applied
voltage
D.U.T. I
D.U.T. V
Inductor current
* V
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91234
.
Document Number: 91234 www.vishay.com
S09-1284-Rev. B, 13-Jul-09 7
www.vishay.com
0.10 AC
M M
E
E/2
(2)
(4)
R/2
B
2 x R
S
D
See view B
2 x e
b4
3 x b
2 x b2
L
C
L1
1
2
3
Q
D
A
A2
A
A
A1
C
Ø k BD
M M
A
ØP
(Datum B)
ØP1
D1
4
E1
0.01 BD
M M
View A - A
Thermal pad
D2
DDE E
C
C
View B
(b1, b3, b5)
Base metal
c1
(b, b2, b4)
Section C - C, D - D, E - E
(c)
Planting
4
3
5
7
4
4
4
Lead Assignments
1. Gate
2. Drain
3. Source
4. Drain
Package Information
Vishay Siliconix
TO-247AC (High Voltage)
MILLIMETERS INCHES MILLIMETERS INCHES
DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.
A 4.58 5.31 0.180 0.209 D2 0.51 1.30 0.020 0.051
A1 2.21 2.59 0.087 0.102 E 15.29 15.87 0.602 0.625
A2 1.17 2.49 0.046 0.098 E1 13.72 - 0.540 -
b 0.99 1.40 0.039 0.055 e 5.46 BSC 0.215 BSC
b1 0.99 1.35 0.039 0.053 Ø k 0.254 0.010
b2 1.53 2.39 0.060 0.094 L 14.20 16.25 0.559 0.640
b3 1.65 2.37 0.065 0.093 L1 3.71 4.29 0.146 0.169
b4 2.42 3.43 0.095 0.135 N 7.62 BSC 0.300 BSC
b5 2.59 3.38 0.102 0.133 Ø P 3.51 3.66 0.138 0.144
c 0.38 0.86 0.015 0.034 Ø P1 - 7.39 - 0.291
c1 0.38 0.76 0.015 0.030 Q 5.31 5.69 0.209 0.224
D 19.71 20.82 0.776 0.820 R 4.52 5.49 0.178 0.216
D1 13.08 - 0.515 - S 5.51 BSC 0.217 BSC
ECN: X13-0103-Rev. D, 01-Jul-13
DWG: 5971
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Contour of slot optional.
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outermost extremes of the plastic body.
4. Thermal pad contour optional with dimensions D1 and E1.
5. Lead finish uncontrolled in L1.
6. Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154").
7. Outline conforms to JEDEC outline TO-247 with exception of dimension c.
8. Xian and Mingxin actually photo.
Revision: 01-Jul-13
Document Number: 91360
1
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Disclaimer
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Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
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including but not limited to the warranty expressed therein.
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Revision: 13-Jun-16
1
Document Number: 91000
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