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TO-247AC
G
D
S
IRFP240
Vishay Siliconix
Power MOSFET
G
N-Channel MOSFET
PRODUCT SUMMARY
VDS (V) 200
R
(Ω)V
DS(on)
Q
(max.) (nC) 70
g
Q
(nC) 13
gs
Q
(nC) 39
gd
Configuration Single
= 10 V 0.18
GS
D
FEATURES
• Dynamic dV/dt rating
• Repetitive avalanche rated
• Isolated central mounting hole
Available
Available
• Fast switching
• Ease of paralleling
• Simple drive requirements
S
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
Note
*
Thi s datasheet provi des informat io n about parts that are
RoHS-compliant and / or parts that are non RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details
DESCRIPTION
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The TO-247AC package is preferred for
commercial-industrial applications where higher power
levels preclude the use of TO-220AB devices. The
TO-247AC is similar but superior to the earlier TO-218
package because its isolated mounting hole. It also provides
greater creepage distances between pins to meet the
requirements of most safety specifications.
ORDERING INFORMATION
Package TO-247AC
Lead (Pb)-free IRFP240PbF
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-source voltage V
Gate-source voltage V
T
= 25 °C
Continuous drain current V
Pulsed drain current
a
at 10 V
GS
C
= 100 °C 12
C
DS
± 20
GS
I
D
IDM 80
Linear derating factor 1.2 W/°C
Single pulse avalanche energy
Repetitive avalanche current
Repetitive avalanche energy
Maximum power dissipation T
Peak diode recovery dV/dt
Operating junction and storage temperature range T
Soldering recommendations (peak temperature)
Mounting torque
b
a
a
= 25 °C P
c
C
d
for 10 s 300
E
AS
I
AR
E
AR
D
dV/dt 5.0 V/ns
, T
J
stg
6-32 or M3 screw
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
= 50 V, starting TJ = 25 °C, L = 1.9 mH, Rg = 25 Ω, IAS = 20 A (see fig. 12)
b. V
DD
c. I
≤ 18 A, dI/dt ≤ 150 A/μs, VDD ≤ VDS, TJ ≤ 150 °C
SD
d. 1.6 mm from case
S22-0046, Rev. C, 24-Jan-2021
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200
20
510 mJ
20 A
15 mJ
150 W
-55 to +150
d
10 lbf · in
1.1 N · m
Document Number: 91210
V
AT
°C
Page 2
D
S
G
S
D
G
IRFP240
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THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL TYP. MAX. UNIT
Maximum junction-to-ambient R
Maximum junction-to-case (drain) R
thJA
thCS
thJC
-40
0.24 -
-0.83
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-source breakdown voltage V
V
temperature coefficient ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.29 - V/°C
DS
Gate-source threshold voltage V
Gate-source leakage I
Zero gate voltage drain current I
Drain-source on-state resistance R
Forward transconductance g
DS
GS(th)
VGS = ± 20 V - - ± 100 nA
GSS
DSS
DS(on)
fs
Dynamic
Input capacitance C
Reverse transfer capacitance C
Total gate charge Q
Gate-drain charge Q
Turn-on delay time t
Rise time t
Turn-off delay time t
Fall time t
Internal drain inductance L
Internal source inductance L
iss
-400-
oss
-130-
rss
g
--13
gs
--39
gd
d(on)
r
d(off)
-36-
f
D
S
Drain-Source Body Diode Characteristics
Continuous source-drain diode current I
Pulsed diode forward current
a
Body diode voltage V
Body diode reverse recovery time t
Body diode reverse recovery charge Q
Forward turn-on time t
S
I
SM
SD
rr
rr
on
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %
VGS = 0 V, ID = 250 μA 200 - - V
VDS = VGS, ID = 250 μA 2.0 - 4.0 V
VDS = 200 V, VGS = 0 V - - 25
= 160 V, VGS = 0 V, TJ = 125 °C - - 250
V
DS
VGS = 10 V ID = 12 A
VDS = 50 V, ID = 12 A
b
b
VGS = 0 V,
V
= 25 V,
DS
f = 1.0 MHz, see fig. 5
= 18 A, VDS = 160 V,
I
V
GS
= 10 V
D
see fig. 6 and 13
b
= 100 V, ID = 18 A,
V
DD
R
= 9.1 Ω, RD = 5.4 Ω,
-45-
g
see fig. 10
b
Between lead,
6 mm (0.25") from
package and center of
die contact
MOSFET symbol
showing the
integral reverse
p - n junction diode
TJ = 25 °C, IS = 20 A, VGS = 0 V
TJ = 25 °C, IF = 18 A, dI/dt = 100 A/μs
b
b
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Vishay Siliconix
°C/WCase-to-sink, flat, greased surface R
- - 0.18 Ω
6.9 - - S
- 1300 -
--70
-14-
-51-
-5.0-
-13-
--20
--80
--2.0V
- 300 610 ns
-3.47.1μC
μA
pFOutput capacitance C
nC Gate-source charge Q
ns
nH
A
S22-0046, Rev. C, 24-Jan-2021
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Document Number: 91210
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
IRFP240
Vishay Siliconix
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 2 - Typical Output Characteristics, T
= 150 °C
C
Fig. 4 - Normalized On-Resistance vs. Temperature
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 3 - Typical Transfer Characteristics
S22-0046, Rev. C, 24-Jan-2021
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Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
3
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Page 4
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Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
R
D
V
GS
R
G
D.U.T.
10 V
+
-
V
DS
V
DD
V
DS
90 %
10 %
V
GS
t
d(on)
t
r
t
d(off)
t
f
IRFP240
Vishay Siliconix
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10a - Switching Time Test Circuit
Fig. 10b - Switching Time Waveforms
S22-0046, Rev. C, 24-Jan-2021
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Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
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Document Number: 91210
Page 5
R
G
I
AS
0.01 Ω
t
p
D.U.T
L
V
DS
+
-
V
DD
10 V
Var y tp to obtain
required I
AS
Q
GS
Q
GD
Q
G
V
G
Charge
10 V
IRFP240
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V
DS
I
AS
Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms
Vishay Siliconix
V
DS
t
p
V
DD
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
0.2 µF
12 V
V
GS
0.3 µF
D.U.T.
3 mA
I
G
Current sampling resistors
I
D
Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit
S22-0046, Rev. C, 24-Jan-2021
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Document Number: 91210
+
V
DS
-
Page 6
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P.W.
Period
dI/dt
Diode recovery
dV/dt
Ripple ≤ 5 %
Body diode forward drop
Re-applied
voltage
Reverse
recovery
current
Body diode forward
current
V
GS
= 10 Va
I
SD
Driver gate drive
D.U.T. l
SD
waveform
D.U.T. V
DS
waveform
Inductor current
D =
P.W.
Period
+
-
+
+
+
-
-
-
Peak Diode Recovery dV/dt Test Circuit
V
DD
• dV/dt controlled by R
g
• Driver same type as D.U.T.
•
I
SD
controlled by duty factor “D”
• D.U.T. - device under test
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
R
g
Note
a. V
GS
= 5 V for logic level devices
V
DD
IRFP240
Vishay Siliconix
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91210
S22-0046, Rev. C, 24-Jan-2021
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.
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Document Number: 91210
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VERSION 1: FACILITY CODE = 9
Package Information
Vishay Siliconix
TO-247AC (High Voltage)
MILLIMETERS MILLIMETERS
DIM. MIN. NOM. MAX. NOTES DIM. MIN. NOM. MAX. NOTES
A 4.83 5.02 5.21 D1 16.46 16.76 17.06 5
A1 2.29 2.41 2.55 D2 0.56 0.66 0.76
A2 1.17 1.27 1.37 E 15.50 15.70 15.87 4
b 1.12 1.20 1.33 E1 13.46 14.02 14.16 5
b1 1.12 1.20 1.28 E2 4.52 4.91 5.49 3
b2 1.91 2.00 2.39 6 e 5.46 BSC
b3 1.91 2.00 2.34 L 14.90 15.15 15.40
b4 2.87 3.00 3.22 6, 8 L1 3.96 4.06 4.16 6
b5 2.87 3.00 3.18 Ø P 3.56 3.61 3.65 7
c 0.40 0.50 0.60 6 Ø P1 7.19 ref.
c1 0.40 0.50 0.56 Q 5.31 5.50 5.69
D 20.40 20.55 20.70 4 S 5.51 BSC
Notes
(1)
Package reference: JEDEC® TO247, variation AC
(2)
All dimensions are in mm
(3)
Slot required, notch may be rounded
(4)
Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the
outermost extremes of the plastic body
(5)
Thermal pad contour optional with dimensions D1 and E1
(6)
Lead finish uncontrolled in L1
(7)
Ø P to have a maximum draft angle of 1.5° to the top of the part with a maximum hole diameter of 3.91 mm
(8)
Dimension b2 and b4 does not include dambar protrusion. Allowable dambar protrusion shall be 0.1 mm total in excess of b2 and b4
dimension at maximum material condition
Revision: 31-Oct-2022
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Document Number: 91360
Page 8
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0.10 AC
M M
E
E/2
(2)
(4)
R/2
B
2 x R
S
D
See view B
2 x e
b4
3 x b
2 x b2
L
C
L1
1
2
3
Q
D
A
A2
A
A
A1
C
Ø k BD
M M
A
ØP
(Datum B)
ØP1
D1
4
E1
0.01 BD
M M
View A - A
Thermal pad
D2
DDE E
C
C
View B
(b1, b3, b5)
Base metal
c1
(b, b2, b4)
Section C - C, D - D, E - E
(c)
Planting
4
3
5
7
4
4
4
Lead Assignments
1. Gate
2. Drain
3. Source
4. Drain
VERSION 2: FACILITY CODE = Y
Package Information
Vishay Siliconix
MILLIMETERS MILLIMETERS
DIM. MIN. MAX. NOTES DIM. MIN. MAX. NOTES
A 4.58 5.31 D2 0.51 1.30
A1 2.21 2.59 E 15.29 15.87
A2 1.17 2.49 E1 13.72 -
b 0.99 1.40 e 5.46 BSC
b1 0.99 1.35 Ø k 0.254
b2 1.53 2.39 L 14.20 16.25
b3 1.65 2.37 L1 3.71 4.29
b4 2.42 3.43 Ø P 3.51 3.66
b5 2.59 3.38 Ø P1 - 7.39
c 0.38 0.86 Q 5.31 5.69
c1 0.38 0.76 R 4.52 5.49
D 19.71 20.82 S 5.51 BSC
D1 13.08 -
Notes
(1)
Dimensioning and tolerancing per ASME Y14.5M-1994
(2)
Contour of slot optional
(3)
Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outermost extremes of the plastic body
(4)
Thermal pad contour optional with dimensions D1 and E1
(5)
Lead finish uncontrolled in L1
(6)
Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154")
(7)
Outline conforms to JEDEC outline TO-247 with exception of dimension c
Revision: 31-Oct-2022
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Document Number: 91360
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c1
c
b, b2, b4
Plating
Base metal
b1, b3, b5
0.01 M
DB
E1
D1
P
A
P1
D2
K
A2
D
A
A1
C
b2
b
b4
e
L
C
L1
D
S
R
Q
N
R/2
E
B
M
M
DB
M
0.10 MCAM
VERSION 3: FACILITY CODE = N
Package Information
Vishay Siliconix
MILLIMETERS MILLIMETERS
DIM. MIN. MAX. DIM. MIN. MAX.
A 4.65 5.31 D2 0.51 1.35
A1 2.21 2.59 E 15.29 15.87
A2 1.17 1.37 E1 13.46 -
b 0.99 1.40 e 5.46 BSC
b1 0.99 1.35 k 0.254
b2 1.65 2.39 L 14.20 16.10
b3 1.65 2.34 L1 3.71 4.29
b4 2.59 3.43 N 7.62 BSC
b5 2.59 3.38 P 3.56 3.66
c 0.38 0.89 P1 - 7.39
c1 0.38 0.84 Q 5.31 5.69
D 19.71 20.70 R 4.52 5.49
D1 13.08 - S 5.51 BSC
ECN: E22-0452-Rev. G, 31-Oct-2022
DWG: 5971
Notes
(1)
Dimensioning and tolerancing per ASME Y14.5M-1994
(2)
Contour of slot optional
(3)
Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outermost extremes of the plastic body
(4)
Thermal pad contour optional with dimensions D1 and E1
(5)
Lead finish uncontrolled in L1
(6)
Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154")
Revision: 31-Oct-2022
3
Document Number: 91360
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Disclaimer
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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to the warranty expressed therein.
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