IRFIB5N65A, SiHFIB5N65A
Power MOSFET
Vishay Siliconix
PRODUCT SUMMARY
VDS (V) 650
(Ω)V
R
DS(on)
Q
(Max.) (nC) 48
g
Q
(nC) 12
gs
Q
(nC) 19
gd
Configuration Single
TO-220 FULLPAK
= 10 V 0.93
GS
D
FEATURES
• Low Gate Charge Qg Results in Simple Drive
Requirement
• Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
• Fully Characterized Capacitance and Avalanche Voltage
and Current
• Compliant to RoHS directive 2002/95/EC
APPLICATIONS
• Switch Mode Power Supply (SMPS)
• Uninterruptible Power Supply
G
• High Speed Power Switching
• High Voltage Isolation = 2.5 kV
TYPICAL SMPS TOPOLOGIES
S
D
G
N-Channel MOSFET
S
• Single Transistor Flyback
• Single Transistor Forward
ORDERING INFORMATION
Package TO-220 FULLPAK
Lead (Pb)-free
SnPb
IRFIB5N65APbF
SiHFIB5N65A-E3
IRFIB5N65A
SiHFIB5N65A
(t = 60 s, f = 60 Hz)
RMS
Available
RoHS*
COMPLIANT
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage V
Gate-Source Voltage V
Continuous Drain Current
Continuous Drain Current T
Pulsed Drain Current
e
VGS at 10 V
a
T
= 25 °C
C
= 100 °C 3.2
C
DS
± 30
GS
I
D
IDM 21
Linear Derating Factor 0.48 W/°C
Single Pulse Avalanche Energy
Repetitive Avalanche Current
Repetitive Avalanche Energy
Maximum Power Dissipation T
Peak Diode Recovery dV/dt
Operating Junction and Storage Temperature Range T
Soldering Recommendations (Peak Temperature)
b
a
a
= 25 °C P
c
d
C
for 10 s 300
E
AS
I
AR
E
AR
D
dV/dt 2.8 V/ns
, T
J
stg
Mounting Torque 6-32 or M3 screw
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting T
c. I
SD
d. 1.6 mm from case.
= 25 °C, L = 24 mH, RG = 25 Ω, IAS = 5.2 A (see fig. 12).
J
≤ 5.2 A, dI/dt ≤ 90 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
e. Drain current limited by maximum junction temperature.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91174 www.vishay.com
S09-0518-Rev. B, 13-Apr-09 1
650
V
5.1
A
325 mJ
5.2 A
6mJ
60 W
- 55 to + 150
°C
10 lbf · in
1.1 N · m
IRFIB5N65A, SiHFIB5N65A
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient R
Maximum Junction-to-Case (Drain) R
thJA
thJC
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage V
Temperature Coefficient ΔVDS/TJ Reference to 25 °C, ID = 1 mA
V
DS
Gate-Source Threshold Voltage V
Gate-Source Leakage I
Zero Gate Voltage Drain Current I
Drain-Source On-State Resistance R
Forward Transconductance g
Dynamic
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Output Capacitance C
Effective Output Capacitance C
Total Gate Charge Q
Gate-Drain Charge Q
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current I
Pulsed Diode Forward Current
a
Body Diode Voltage V
Body Diode Reverse Recovery Time t
Body Diode Reverse Recovery Charge Q
Forward Turn-On Time t
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
c. C
eff. is a fixed capacitance that gives the same charging time as C
oss
d. t = 60 s, f = 60 Hz.
DS
GS(th)
V
GSS
DSS
VGS = 10 V ID = 3.1 A
DS(on)
fs
iss
- 177 -
oss
-7.0-
rss
oss
eff. VDS = 0 V to 520 V
oss
g
--12
gs
--19
gd
d(on)
r
-34-
d(off)
-18-
f
S
V
V
GS
V
GS
MOSFET symbol
showing the
integral reverse
I
SM
SD
rr
rr
on
p - n junction diode
TJ = 25 °C, IF = 5.2 A, dI/dt = 100 A/µs
-65
-2.1
°C/W
VGS = 0 V, ID = 250 µA 650 - - V
d
- 670 - mV/°C
VDS = VGS, ID = 250 µA 2.0 - 4.0 V
= ± 30 V - - ± 100 nA
GS
VDS = 650 V, VGS = 0 V - - 25
= 520 V, VGS = 0 V, TJ = 125 °C - - 250
DS
b
- - 0.93 Ω
VDS = 50 V, ID = 3.1 A 3.9 - - S
VGS = 0 V,
V
= 25 V,
DS
f = 1.0 MHz, see fig. 5
= 1.0 V, f = 1.0 MHz - 1912 -
V
DS
= 0 V
V
= 520 V, f = 1.0 MHz - 48 -
DS
c
- 1417 -
-84-
--48
= 5.2 A, VDS = 400 V
I
= 10 V
D
see fig. 6 and 13
b
-14-
V
= 325 V, ID = 5.2 A
DD
R
= 9.1 Ω, RD = 62 Ω,
G
see fig. 10
b
G
TJ = 25 °C, IS = 5.2 A, VGS = 0 V
D
S
b
-20-
--5.2
--21
--1.5V
- 493 739 ns
b
-2.13.2µC
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
while VDS is rising from 0 % to 80 % VDS.
oss
µA
pF
nC Gate-Source Charge Q
ns
A
www.vishay.com Document Number: 91174
2 S09-0518-Rev. B, 13-Apr-09
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
100
10
1
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
100
IRFIB5N65A, SiHFIB5N65A
Vishay Siliconix
10
1
°
T = 150 C
J
°
T = 25 C
J
D
I , Drain-to-Source Current (A)
20µs PULSE WIDTH
0.1
4.5V
0.1 1 10 100
V , Drain-to-Source Voltage (V)
DS
°
T = 25 C
J
Fig. 1 - Typical Output Characteristics
100
10
1
D
I , Drain-to-Source Current (A)
0.1
VGS
TOP
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM
4.5V
4.5V
20µs PULSE WIDTH
T = 150 C
1 10 100
V , Drain-to-Source Voltage (V)
DS
°
J
Fig. 2 - Typical Output Characteristics
D
I , Drain-to-Source Current (A)
V = 100V
DS
0.1
4.0 5.0 6.0 7.0 8.0 9.0
V , Gate-to-Source Voltage (V)
GS
20µs PULSE WIDTH
Fig. 3 - Typical Transfer Characteristics
3.0
2.5
2.0
1.5
(Normalized)
1.0
0.5
DS(on)
R , Drain-to-Source On Resistance
0.0
5.2A
I =
D
V =
GS
-60 -40 -20 0 20 40 60 80 100 120 140 160
T , Junction Temperature ( C)
J
°
Fig. 4 - Normalized On-Resistance vs. Temperature
10V
Document Number: 91174 www.vishay.com
S09-0518-Rev. B, 13-Apr-09 3
IRFIB5N65A, SiHFIB5N65A
Vishay Siliconix
2000
1600
1200
800
V = 0V, f = 1MHz
GS
C = C + C , C SHORTED
iss gs gd ds
C = C
rss gd
C = C + C
oss ds gd
iss
oss
C, Capacitance (pF)
400
0
1 10 100 1000
rss
V , Drain-to-Source Voltage (V)
DS
A
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
20
I =
5.2A
D
V = 520V
DS
V = 325V
16
DS
V = 130V
DS
100
10
°
T = 150 C
J
1
°
T = 25 C
SD
I , Reverse Drain Current (A)
0.1
0.2 0.4 0.6 0.8 1.0 1.2
V ,Source-to-Drain Voltage (V)
SD
J
V = 0 V
GS
Fig. 7 - Typical Source-Drain Diode Forward Voltage
100
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
10us
12
8
4
GS
V , Gate-to-Source Voltage (V)
FOR TEST CIRCUIT
0
0 10 20 30 40 50
Q , Total Gate Charge (nC)
G
SEE FIGURE
13
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
10
1
D
I , Drain Current (A)I , Drain Current (A)
°
= 25 C
C
T T= 150 C
Single Pulse
0.1
10 100 1000 10000
°
J
V , Drain-to-Source Voltage (V)
DS
100us
1ms
10ms
Fig. 8 - Maximum Safe Operating Area
www.vishay.com Document Number: 91174
4 S09-0518-Rev. B, 13-Apr-09
6.0
A
5.0
IRFIB5N65A, SiHFIB5N65A
Vishay Siliconix
R
D.U.T.
D
+
V
DD
-
V
DS
V
GS
R
G
4.0
3.0
2.0
D
I , Drain Current (A)
1.0
0.0
25 50 75 100 125 150
T , Case Temperature ( C)
C
°
Fig. 9 - Maximum Drain Current vs. Case Temperature
10
thJC
D = 0.50
1
0.20
0.10
0.05
0.1
0.02
Thermal Response (Z )
0.01
SINGLE PULSE
(THERMAL RESPONSE)
0.01
0.00001 0.0001 0.001 0.01 0.1 1 10
t , Rectangular Pulse Duration (s)
1
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
V
DS
90 %
10 %
V
GS
t
d(on)tr
t
d(off)tf
Fig. 10b - Switching Time Waveforms
P
DM
t
1
t
2
Notes:
1. Duty factor D = t / t
2. Peak T =P x Z + T
1 2
J DM thJC C
V
DS
15 V
V
DS
R
G
20 V
L
D.U.T.
I
AS
0.01 Ω
t
p
Driver
+
V
A
DD
-
Fig. 12a - Unclamped Inductive Test Circuit
I
AS
Fig. 12b - Unclamped Inductive Waveforms
t
p
Document Number: 91174 www.vishay.com
S09-0518-Rev. B, 13-Apr-09 5
IRFIB5N65A, SiHFIB5N65A
Vishay Siliconix
800
TOP
I
D
2.3A
3.3A
600
BOTTOM
400
200
AS
E , Single Pulse Avalanche Energy (mJ)
0
25 50 75 100 125 150
Starting T , Junction Temperature ( C)
J
5.2A
°
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
800
780
760
Q
G
10 V
Q
GS
V
G
Q
GD
Charge
Fig. 13a - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
50 kΩ
0.2 µF
12 V
V
GS
0.3 µF
D.U.T.
3 mA
I
G
Current sampling resistors
+
V
DS
-
I
D
740
DSav
720
V , Avalanche Voltage (V)
700
0123456
I , Avalanche Current (A)
av
A
Fig. 13b - Gate Charge Test Circuit
Fig. 12d - Typical Drain-to Source Voltage vs. Avalanche
Current
www.vishay.com Document Number: 91174
6 S09-0518-Rev. B, 13-Apr-09
IRFIB5N65A, SiHFIB5N65A
Peak Diode Recovery dV/dt Test Circuit
Vishay Siliconix
D.U.T.
+
-
R
G
Driver gate drive
P.W.
+
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
-
• dV/dt controlled by R
• Driver same type as D.U.T.
• I
controlled by duty factor "D"
SD
• D.U.T. - device under test
Period
-
D =
G
P.W.
Period
+
+
V
DD
-
= 10 V*
V
GS
waveform
SD
Body diode forward
current
waveform
DS
Body diode forward drop
Ripple ≤ 5 %
= 5 V for logic level devices
GS
Diode recovery
dV/dt
dI/dt
V
DD
I
SD
Reverse
recovery
current
Re-applied
voltage
D.U.T. I
D.U.T. V
Inductor crurent
* V
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91174
.
Document Number: 91174 www.vishay.com
S09-0518-Rev. B, 13-Apr-09 7
Legal Disclaimer Notice
www.vishay.com
Vishay
Disclaimer
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RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
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including but not limited to the warranty expressed therein.
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Revision: 13-Jun-16
1
Document Number: 91000
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