Vishay IRFD9220, SiHFD9220 Data Sheet

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S
G
D
P-Channel MOSFET
HVMDIP
D
S
G
IRFD9220, SiHFD9220
Vishay Siliconix
Power MOSFET
PRODUCT SUMMARY
VDS (V) - 200
R
()V
DS(on)
Q
(Max.) (nC) 15
g
(nC) 3.2
Q
gs
Q
(nC) 8.4
gd
Configuration Single
= - 10 V 1.5
GS
FEATURES
• Dynamic dV/dt Rating
• Repetitive Avalanche Rated
• For Automatic Insertion
Available
RoHS*
COMPLIANT
•End Stackable
•P-Channel
• Fast Switching
• Ease of Paralleling
• Material categorization: For definitions of compliance please see www.vishay.com/doc?99912
Note
* Lead (Pb)-containing terminations are not RoHS-compliant.
Exemptions may apply.
DESCRIPTION
Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The 4 pin DIP package is a low cost machine-insertable case style which can be stacked in multiple combinations on standard 0.1" pin centers. The dual drain serves as a thermal link to the mounting surface for power dissipation levels up to 1 W.
ORDERING INFORMATION
Package HVMDIP
Lead (Pb)-free
SnPb
IRFD9220PbF SiHFD9220-E3 IRFD9220 SiHFD9220
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage V
Gate-Source Voltage V
= 25 °C
T
Continuous Drain Current V
Pulsed Drain Current
a
at - 10 V
GS
A
= 100 °C - 0.36
A
DS
± 20
GS
I
D
IDM - 4.5
Linear Derating Factor 0.0083 W/°C
Single Pulse Avalanche Energy
Avalanche Current
a
Repetitive Avalanche Energy
Maximum Power Dissipation T
Peak Diode Recovery dV/dt
Operating Junction and Storage Temperature Range T
b
a
= 25 °C P
c
A
E
AS
I
AR
E
AR
D
dV/dt - 5.0 V/ns
, T
J
stg
Soldering Recommendations (Peak Temperature) for 10 s 300
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. V
= - 50 V, starting TJ = 25 °C, L = 17.8 mH, Rg = 25 , IAS = - 3 A (see fig. 12).
DD
c. I
- 3.9 A, dI/dt 95 A/μs, VDD VDS, TJ 150 °C.
SD
S12-0617-Rev. D, 26-Mar-12
1
For technical questions, contact: hvm@vishay.com
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
- 200
- 0.56
80 mJ
- 0.56 A
0.10 mJ
1.0 W
- 55 to + 150
d
Document Number: 91141
V
AT
°C
IRFD9220, SiHFD9220
D
S
G
S
D
G
www.vishay.com
d. 1.6 mm from case.
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient R
thJA
- 120 °C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage V
V
Temperature Coefficient VDS/TJ Reference to 25 °C, ID = - 1 mA - - 0.22 - V/°C
DS
Gate-Source Threshold Voltage V
Gate-Source Leakage I
Zero Gate Voltage Drain Current I
Drain-Source On-State Resistance R
Forward Transconductance g
DS
GS(th)
V
GSS
DSS
VGS = - 10 V ID = - 0.34 A
DS(on)
fs
Dynamic
Input Capacitance C
Reverse Transfer Capacitance C
Total Gate Charge Q
Gate-Drain Charge Q
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t
Internal Drain Inductance L
Internal Source Inductance L
iss
- 110 -
oss
-33-
rss
g
--3.2
gs
--8.4
gd
d(on)
r
-7.3-
d(off)
-19-
f
D
S
VGS = 0 V, ID = - 250 μA - 200 - - V
VDS = VGS, ID = - 250 μA - 2.0 - - 4.0 V
= ± 20 V - - ± 100 nA
GS
VDS = - 200 V, VGS = 0 V - - - 100
V
= - 160 V, VGS = 0 V, TJ = 125 °C - - - 500
DS
b
VDS = - 50 V, ID = - 0.35 A
b
VGS = 0 V,
V
= - 25 V,
DS
f = 1.0 MHz, see fig. 5
= - 2.1 A, VDS = - 160 V,
I
= - 10 V
V
GS
V
R
= 18 , RD = 24 , see fig. 10
g
D
see fig. 6 and 13
= - 100 V, ID = - 3.9 A,
DD
b
b
Between lead, 6 mm (0.25") from package and center of die contact
Vishay Siliconix
--1.5
0.55 - - S
- 340 -
--15
-8.8-
-27-
-4.0-
-6.0-
μA
pFOutput Capacitance C
nC Gate-Source Charge Q
ns
nH
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current I
Pulsed Diode Forward Current
a
Body Diode Voltage V
Body Diode Reverse Recovery Time t
Body Diode Reverse Recovery Charge Q
S
MOSFET symbol showing the
integral reverse
I
SM
SD
rr
rr
p - n junction diode
TJ = 25 °C, IS = - 0.56 A, VGS = 0 V
b
TJ = 25 °C, IF = - 3.9 A, dI/dt = 100 A/μs
--- 0.56
--- 4.5
--- 6.3V
- 150 300 ns
b
- 0.97 2.0 μC
A
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width 300 μs; duty cycle  2 %.
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
For technical questions, contact: hvm@vishay.com
S12-0617-Rev. D, 26-Mar-12
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Document Number: 91141
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20 μs PULSE WIDTH T
A
= 25 °C
20 μs PULSE WIDTH T
A
= 150 °C
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
IRFD9220, SiHFD9220
Vishay Siliconix
Fig. 1 - Typical Output Characteristics, TA = 25 °C
Fig. 2 - Typical Output Characteristics, T
= 150 °C
A
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
S12-0617-Rev. D, 26-Mar-12
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Document Number: 91141
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TA = 25 °C T
J
= 150 °C
SINGLE PULSE
IRFD9220, SiHFD9220
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
S12-0617-Rev. D, 26-Mar-12
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Document Number: 91141
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, Drain Current (A)
Pulse width 1 µs Duty factor 0.1 %
R
D
V
GS
R
g
D.U.T.
- 10 V
+
-
V
DS
V
DD
V
GS
10 %
90 %
V
DS
t
d(on)
t
r
t
d(off)
t
f
Thermal Response (Z
thJA
)
t1, Rectangular Pulse Duration (s)t1, Rectangular Pulse Duration (s)
D
I
www.vishay.com
TA, Ambient Temperature (°C)
IRFD9220, SiHFD9220
Vishay Siliconix
Fig. 10 - Switching Time Test Circuit
Fig. 9 - Maximum Drain Current vs. Ambient Temperature
Fig. 12 - Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
Fig. 11 - Switching Time Waveforms
S12-0617-Rev. D, 26-Mar-12
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For technical questions, contact: hvm@vishay.com
Document Number: 91141
IRFD9220, SiHFD9220
R
g
I
AS
0.01 W
t
p
D.U.T.
L
V
DS
+
-
V
DD
- 10 V
Vary tp to obtain required I
AS
I
AS
V
DS
V
DD
V
DS
t
p
www.vishay.com
Fig. 13 - Unclamped Inductive Test Circuit Fig. 14 - Unclamped Inductive Waveforms
Vishay Siliconix
Fig. 15 - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
Q
- 10 V
Q
GS
V
G
G
Q
GD
Charge
12 V
V
GS
50 kΩ
0.2 µF
0.3 µF
- 3 mA
I
G
Current sampling resistors
D.U.T.
I
D
Fig. 16 - Basic Gate Charge Waveform Fig. 17 - Gate Charge Test Circuit
S12-0617-Rev. D, 26-Mar-12
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For technical questions, contact: hvm@vishay.com
Document Number: 91141
-
V
+
DS
www.vishay.com
P.W.
Period
dI/dt
Diode recovery
dV/dt
Body diode forward drop
Body diode forward
current
Driver gate drive
Inductor current
D =
P.W.
Period
+
-
-
-
-
+
+
+
Peak Diode Recovery dV/dt Test Circuit
dV/dt controlled by R
g
D.U.T. - device under test
D.U.T.
Circuit layout considerations
Low stray inductance
Ground plane
Low leakage inductance
current transformer
R
g
Compliment N-Channel of D.U.T. for driver
V
DD
I
SD
controlled by duty factor “D”
Note
Note
a. V
GS
= - 5 V for logic level and - 3 V drive devices
V
GS
= - 10 V
a
D.U.T. lSD waveform
D.U.T. V
DS
waveform
V
DD
Re-applied voltage
Ripple 5 %
I
SD
Reverse recovery current
IRFD9220, SiHFD9220
Vishay Siliconix
Fig. 18 - For P-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91141
S12-0617-Rev. D, 26-Mar-12
.
7
For technical questions, contact: hvm@vishay.com
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Document Number: 91141
HVM DIP (High voltage)
Package Information
Vishay Siliconix
0.248 [6.29]
0.240 [6.10]
0.043 [1.09]
0.035 [0.89]
0.094 [2.38]
0.086 [2.18]
0.017 [0.43]
0.013 [0.33]
0° to 15° 2 x
E min.
E max.
0.133 [3.37]
0.125 [3.18]
0.045 [1.14]
2 x
0.035 [0.89]
A
0.100 [2.54] typ.
L
0.197 [5.00]
0.189 [4.80]
0.160 [4.06]
0.140 [3.56]
0.024 [0.60]
0.020 [0.51]
0.180 [4.57]
0.160 [4.06]
4 x
INCHES MILLIMETERS
DIM. MIN. MAX. MIN. MAX.
A 0.310 0.330 7.87 8.38
E 0.300 0.425 7.62 10.79
L 0.270 0.290 6.86 7.36
ECN: X10-0386-Rev. B, 06-Sep-10 DWG: 5974
Note
1. Package length does not include mold flash, protrusions or gate burrs. Package width does not include interlead flash or protrusions.
Document Number: 91361 www.vishay.com Revision: 06-Sep-10 1
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Vishay
Disclaimer
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Revision: 13-Jun-16
1
Document Number: 91000
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