Vishay IRFD9010, SiHFD9010 Data Sheet

Power MOSFET

IRFD9010, SiHFD9010

Vishay Siliconix

PRODUCT SUMMARY

VDS (V) - 50

R

(Ω)V

DS(on)

Q

(Max.) (nC) 11

g

Q

(nC) 3.8

gs

Q

(nC) 4.1

gd

Configuration Single

HVMDIP

S

G

D

= - 10 V 0.50

GS

G

P-Channel MOSFET

FEATURES

• For Automatic Insertion

• Compact, End Stackable

•Fast Switching

• Low Drive Current

• Easy Paralleled

• Excellent Temperature Stability

• P-Channel Versatility

• Compliant to RoHS Directive 2002/95/EC

DESCRIPTION

The HVMDIP technology is the key to Vishay’s advanced

S

D

line of power MOSFET transistors. The efficient geometry
and unique processing of the HVMDIP design achieves
very low on-state resistance combined with high
transconductance and extreme device ruggedness.
The p-channel HVMDIPs are designed for application which
require the convenience of reverse polarity operation. They
retain all of the features of the more common n-channel
HVMDIPs such as voltage control, very fast switching, ease
of paralleling, and excellent temperature stability.
P-channels HVMDIPs are intended for use in power stages
where complementary symmetry with n-channel devices
offers circuit simplification. They are also very useful in drive
stages because of the circuit versatility offered by the
reverse polarity connection. Applications include motor
control, audio amplifiers, switched mode converters, control
circuits and pulse amplifiers.

ORDERING INFORMATION

Package HVMDIP

Lead (Pb)-free

SnPb

IRFD9010PbF

SiHFD9010-E3

IRFD9010

SiHFD9010

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage V

Gate-Source Voltage V

T

= 25 °C

Continuous Drain Current V

Pulsed Drain Current

Linear Derating Factor 0.01 W/°C

Inductive Current, Clamped L = 100 µH see fig. 14 I

Inductive Current, Unclamped (Avalanche Current) see fig. 15 I

Maximum Power Dissipation T

Operating Junction and Storage Temperature Range T

Soldering Recommendations (Peak Temperature) for 10 s 300

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. V

= - 25 V, starting TJ = 25 °C, L = 52 mH, Rg = 25 Ω, IAS = - 2.0 A (see fig. 12).

DD

≤ - 4.0 A, dI/dt ≤ 75 A/μs, VDD ≤ VDS, TJ ≤ 175 °C.

c. I

SD

d. 1.6 mm from case.

a

at - 10 V

GS

C

= 100 °C - 0.68

C

= 25 °C P

C

DS

± 20

GS

I

D

IDM - 8.8

LM

L

D

, T

J

stg

- 50

- 1.1

- 8.8

- 1.5

1W

- 55 to + 150

d

V

AT

A

°C

* Pb containing terminations are not RoHS compliant, exemptions may apply

Document Number: 91405 www.vishay.com
S10-0998-Rev. A, 26-Apr-10 1

IRFD9010, SiHFD9010

Vishay Siliconix

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT

Maximum Junction-to-Ambient R

thJA

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-Source Breakdown Voltage V

V

Temperature Coefficient ΔVDS/TJ Reference to 25 °C, ID = - 1 mA - - 0.091 - V/°C

DS

Gate-Source Threshold Voltage V

Gate-Source Leakage I

Zero Gate Voltage Drain Current I

On-State Drain Current I

Drain-Source On-State Resistance R

Forward Transconductance g

Dynamic

Input Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Gate-Drain Charge Q

Turn-On Delay Time t

Rise Time t

Turn-Off Delay Time t

Fall Time t

Internal Drain Inductance L

Internal Source Inductance L

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current I

Pulsed Diode Forward Current

a

Body Diode Voltage V

Body Diode Reverse Recovery Time t

Body Diode Reverse Recovery Charge Q

Forward Turn-On Time t

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %.

DS

GS(th)

V

GSS

DSS

V

D(on)

VGS = - 10 V ID = - 0.58 A

DS(on)

fs

iss

- 160 -

oss

-30-

rss

g

-2.53.8

gs

-2.74.1

gd

d(on)

r

-1320

d(off)

-3959

f

D

V

GS

V

GS

Between lead,
6 mm (0.25") from
package and center of

S

S

I

SM

SD

rr

rr

Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

on

die contact

MOSFET symbol
showing the

integral reverse
p - n junction diode

TJ = 25 °C, IF = - 4.7 A, dI/dt = 100 A/μs

- 120 °C/W

VGS = 0 V, ID = - 250 μA - 50 - - V

VDS = VGS, ID = - 250 μA - 2.0 - - 4.0 V

= ± 20 V - - ± 500 nA

GS

VDS = - 50 V, VGS = 0 V - - - 250

= - 40 V, VGS = 0 V, TJ = 125 °C - - - 1000

DS

= 10 V VDS > I

D(on)

x R

max. - 1.1 - - A

DS(on)

b

- 0.35 0.50 Ω

VDS = - 20 V, ID = - 2.4 A 1.7 2.5 - S

VGS = 0 V,

V

= - 25 V,

DS

f = 1.0 MHz, see fig. 5

- 240 -

-7.211

= - 4.7 A, VDS = 0.8 V

I

= - 10 V

D

see fig. 6 and 13

b

-6.19.2

V

= - 25 V, ID = - 4.7 A

DD

R

= 24 Ω, RD = 5.6 Ω,

g

see fig. 10

b

G

G

TJ = 25 °C, IS = - 0.7 A, VGS = 0 V

D

S

D

S

b

-4771

-4.0-

-6.0-

--- 1.1A

--- 8.8

--- 5.5V

33 75 160 ns

b

0.090 0.22 0.52 μC

μA

pFOutput Capacitance C

nC Gate-Source Charge Q

ns

nH

www.vishay.com Document Number: 91405
2 S10-0998-Rev. A, 26-Apr-10

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

IRFD9010, SiHFD9010

Vishay Siliconix

, Drain Current (A)

D

- I

, Drain Current (A)

D

- I

10

- 10 V

8

6

4

2

0

80 μs Pulse Width

- VGS, Drain-to-Source Voltage (V)

Fig. 1 - Typical Output Characteristics

10

80 μs Pulse Width

8

6

4

2

0

- VGS, Drain-to-Source Voltage (V)

Fig. 2 - Typical Output Characteristics

- 8 V

- 7 V

VGS = - 6 V

- 5 V

- 4 V

- 10 V

- 8 V

- 7 V

VGS = - 6 V

- 5 V

- 4 V

3.0

ID = - 4.7 V

2.4

1.8

1.2

(Normalized)

0.6

, Drain-to-Source on Resistance

DS(on)

0

2520151050

R

VGS = - 10 V

140120100806040200- 20- 40

160- 60

TJ, Junction Temperature (°C)

Fig. 4 - Normalized On-Resistance vs. Temperature

500

400

300

200

Capacitance (pF)

100

0

543210

VGS = 0 V, f = 1 MHz

= Cgs + Cgd, Cds Shorted

C

iss

= C

C

rss

gd

C

= Cds + C

oss

gd

C

iss

C

oss

C

rss

100101

- VGS, Drain-to-Source Voltage (V)

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

, Drain Current (A)

D

- I

0.001

10

80 μs Pulse Width

0.1

0.01

VDS = 2 x V

1

TJ = 150 °C

GS

TJ = 25 °C

- VGS, Drain-to-Source Voltage (V)

Fig. 3 - Typical Transfer Characteristics

1086430

20

ID = - 4.7 A

16

VDS = - 40 V

12

8

, Gate-to-Source Voltage (V)

4

GS

- V

0

For Test Circuit

See Figure 13

15129630

Qg, Total Gate Charge (nC)

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

Document Number: 91405 www.vishay.com
S10-0998-Rev. A, 26-Apr-10 3

IRFD9010, SiHFD9010

Vishay Siliconix

100

10

1

TJ = 150 °C

TJ = 25 °C

, Reverse Drain Current (A)

SD

- I

0.1

- VSD, Source-to-Drain Voltage (V)

Fig. 7 - Typical Source-Drain Diode Forward Voltage

, Drain Current (A)

D

- I

0.01

100

10

1

0.1

TC = 25 °C
T

J

Single Pulse

Operation in this Area Limited
by R

DS(on)

= 150 °C

10 μs
100 μs

1 ms

10 ms

100 ms

1 s

DC

- VDS, Drain-to-Source Voltage (V)

Fig. 8 - Maximum Safe Operating Area

2.0

1.6

1.2

0.8

, Drain Current (A)

D

- I

0.4

543210

0

150125100755025

TC, Case Temperature (°C)

Fig. 9 - Maximum Drain Current vs. Case Temperature

R

D.U.T.

D

-

+

V

DD

V

DS

V

GS

R

g

- 10 V

Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

Fig. 10a - Switching Time Test Circuit

100101

V

10 %

t

t

d(on)

GS

r

t

d(off)

t

f

90 %

V

DS

Fig. 10b - Switching Time Waveforms

www.vishay.com Document Number: 91405
4 S10-0998-Rev. A, 26-Apr-10

)

DthJC

Thermal Response (Z

1000

100

0.1

IRFD9010, SiHFD9010

Vishay Siliconix

0.5

0.2

0.1

10

0.05

0.02

0.01

1

Single Pulse
(Thermal Response)

Notes:

1. Duty Factor, D = t

2. Peak TJ = PDM x T

110

t1, Rectangular Pulse Duration (s)

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

P

DM

t

1

t

2

1/t2

+ T

thJC

C

1000.10.010.0010.00010.00001

I

AS

D.U.T

L

0.01 W

-

+

Var y tp to obtain
required I

AS

R

g

- 10 V

V

DS

t

p

Fig. 12a - Unclamped Inductive Test Circuit

I

AS

V

DS

V

t

p

V

DD

DS

Fig. 12b - Unclamped Inductive Waveforms

Q

- 10 V

Q

V

DD

GS

V

G

G

Q

GD

Charge

Fig. 13a - Basic Gate Charge Waveform

Current regulator

Same type as D.U.T.

50 kΩ

0.2 µF

12 V

0.3 µF

-

V

+

D.U.T.

V

GS

- 3 mA

I

G

Current sampling resistors

I

DS

D

Fig. 13b - Gate Charge Test Circuit

Document Number: 91405 www.vishay.com
S10-0998-Rev. A, 26-Apr-10 5

IRFD9010, SiHFD9010

Vishay Siliconix

Peak Diode Recovery dV/dt Test Circuit

D.U.T.

+

Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance

-

current transformer

+

-

R

g

• dV/dt controlled by R

• ISD controlled by duty factor "D"

• D.U.T. - device under test

Compliment N-Channel of D.U.T. for driver

Driver gate drive

P.W.

Period

-

D =

G

P.W.

Period

+

+

V

DD

-

Reverse
recovery
current

Re-applied
voltage

D.U.T. I

D.U.T. V

Inductor current

* V

waveform

SD

Body diode forward

current

waveform

DS

Body diode forward drop

Ripple ≤ 5 %

= - 5 V for logic level and - 3 V drive devices

GS

dI/dt

Diode recovery

dV/dt

Fig. 14 - For P-Channel

V

GS

V

DD

I

SD

= - 10 V*

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91405

.

www.vishay.com Document Number: 91405
6 S10-0998-Rev. A, 26-Apr-10

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

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including but not limited to the warranty expressed therein.

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Revision: 13-Jun-16

1

Document Number: 91000