Vishay IRFBF30S, SiHFBF30S Data Sheet

D2PAK (TO-263)

G

D

S

Power MOSFET

IRFBF30S, SiHFBF30S

Vishay Siliconix

PRODUCT SUMMARY

VDS (V) 900

R

()V

DS(on)

Q

(Max.) (nC) 78

g

Q

(nC) 10

gs

Q

(nC) 42

gd

Configuration Single

= 10 V 3.7

GS

D

FEATURES

• Halogen-free According to IEC 61249-2-21
Definition

• Dynamic dV/dt Rating

• Repetitive Avalanche Rated

•Fast Switching

• Ease of Paralleling

• Simple Drive Requirements

• Compliant to RoHS Directive 2002/95/EC

DESCRIPTION

Third generation MOSFETs from Vishay provide the
designer with the best combination of fast switching,

G

ruggedized device design, low on-resistance and
cost-effectiveness.

2

PAK (TO-263) package is universially preferred for all

The D
commercial-industrial applications at power dissipation

S

N-Channel MOSFET

levels to approximately 50 W. The low thermal resistance
and low package cost of the D
its wide acceptance throughout the industry.

ORDERING INFORMATION

Package D2PAK (TO-263)
Lead (Pb)-free and Halogen-free SiHFBF30S-GE3

Lead (Pb)-free

IRFBF30SPbF
SiHFBF30S-E3

2

PAK (TO-263) contribute to

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. V
c. I
d. 1.6 mm from case.

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage V

Gate-Source Voltage V

T

= 25 °C

Continuous Drain Current V

Pulsed Drain Current

a

at 10 V

GS

C

T

= 100 °C 2.3

C

DS

± 20

GS

I

D

IDM 14

Linear Derating Factor 1.0 W/°C

Single Pulse Avalanche Energy

Repetitive Avalanche Current

Repetitive Avalanche Energy

Maximum Power Dissipation T

Peak Diode Recovery dV/dt

Operating Junction and Storage Temperature Range T

b

a

a

= 25 °C P

c

C

E

AS

I

AR

E

AR

D

dV/dt 1.5 V/ns

, T

J

stg

Soldering Recommendations (Peak Temperature) for 10 s 300

= 50 V, starting TJ = 25 °C, L = 36 mH, Rg = 25 , IAS = 3.6 A (see fig. 12).

DD

 3.6 A, dI/dt  70 A/μs, VDD  600, TJ  150 °C.

SD

900

3.6

250 mJ

3.6 A

13 mJ

125 W

- 55 to + 150

d

V

A

°C

* Pb containing terminations are not RoHS compliant, exemptions may apply

Document Number: 91389

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S11-1055-Rev. C, 30-May-11 1

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

This document is subject to change without notice.

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IRFBF30S, SiHFBF30S

Vishay Siliconix

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT

Maximum Junction-to-Ambient R

a

Maximum Junction-to-Case (Drain) R

thJA

R

thJA

thJC

Note

a. When mounted on 1" square PCB (FR-4 or G-10 material).

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-Source Breakdown Voltage V

V

Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 1 mA - 1.1 - V/°C

DS

Gate-Source Threshold Voltage V

Gate-Source Leakage I

Zero Gate Voltage Drain Current I

Drain-Source On-State Resistance R

Forward Transconductance g

DS

GS(th)

V

GSS

DSS

VGS = 10 V ID = 2.2 A

DS(on)

fs

Dynamic

Input Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Gate-Drain Charge Q

Turn-On Delay Time t

Rise Time t

Turn-Off Delay Time t

Fall Time t

Internal Drain Inductance L

iss

- 320 -

oss

- 200 -

rss

g

--10

gs

--42

gd

d(on)

r

-90-

d(off)

-30-

f

D

V

Between lead,
6 mm (0.25") from
package and center of

Internal Source Inductance L

S

die contact

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current I

Pulsed Diode Forward Current

a

Body Diode Voltage V

Body Diode Reverse Recovery Time t

Body Diode Reverse Recovery Charge Q

Forward Turn-On Time t

S

I

SM

SD

rr

rr

on

MOSFET symbol
showing the
integral reverse
p - n junction diode

TJ = 25 °C, IF = 3.6 A, dI/dt = 100 A/μs

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width  300 μs; duty cycle  2 %.

www.vishay.com Document Number: 91389
2 S11-1055-Rev. C, 30-May-11

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

VGS = 0, ID = 250 μA 900 - - V

VDS = VGS, ID = 250 μA 2.0 - 4.0 V

VDS = 900 V, VGS = 0 V - - 100

V

= 720 V, VGS = 0 V, TJ = 125 °C - - 500

DS

VDS = 100 V, ID = 2.2 A

f = 1.0 MHz, see fig. 5

= 10 V

GS

V

= 450 V, ID = 3.6 A,

DD

R

= 12 , RD = 120 , see fig. 10

g

TJ = 25 °C, IS = 3.6 A, VGS = 0 V

Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

-62

-40

°C/WMaximum Junction-to-Ambient (PCB Mount)

-1.0

= ± 20 V - - ± 100 nA

GS

VGS = 0 V,

V

= 25 V,

DS

b

b

--3.7

2.3 - - S

- 1200 -

--78

= 3.6 A, VDS = 360 V,

I

D

see fig. 6 and 13

b

-14-

-25-

b

D

G

S

D

G

S

b

-4.5-

-7.5-

--3.6

--14

--1.8V

- 430 650 ns

b

-1.42.1μC

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μA

pFOutput Capacitance C

nC Gate-Source Charge Q

ns

nH

A

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

IRFBF30S, SiHFBF30S

Vishay Siliconix

Fig. 1 - Typical Output Characteristics, TC = 25 °C

Fig. 2 -Typical Output Characteristics, T

= 150 °C

C

Fig. 3 - Typical Transfer Characteristics

Fig. 4 - Normalized On-Resistance vs. Temperature

Document Number: 91389 www.vishay.com
S11-1055-Rev. C, 30-May-11 3

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

This document is subject to change without notice.

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IRFBF30S, SiHFBF30S

Vishay Siliconix

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

Fig. 7 - Typical Source-Drain Diode Forward Voltage

Fig. 8 - Maximum Safe Operating Area

www.vishay.com Document Number: 91389
4 S11-1055-Rev. C, 30-May-11

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

This document is subject to change without notice.

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V

DS

90 %

10 %

V

GS

t

d(on)

t

r

t

d(off)

t

f

R

g

I

AS

0.01 Ω

t

p

D.U.T

L

V

DS

+

-

V

DD

A

10 V

Var y tp to obtain
required I

AS

I

AS

V

DS

V

DD

V

DS

t

p

IRFBF30S, SiHFBF30S

Vishay Siliconix

R

D.U.T.

D

+

V

-

DD

V

DS

V

GS

R

g

10 V

Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

Fig. 10a - Switching Time Test Circuit

Fig. 9 - Maximum Drain Current vs. Case Temperature

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig. 10b - Switching Time Waveforms

Document Number: 91389 www.vishay.com
S11-1055-Rev. C, 30-May-11 5

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

This document is subject to change without notice.

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Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms

IRFBF30S, SiHFBF30S

D.U.T.

3 mA

V

GS

V

DS

I

G

I

D

0.3 µF

0.2 µF

50 kΩ

12 V

Current regulator

Current sampling resistors

Same type as D.U.T.

+

-

Vishay Siliconix

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Q

10 V

V

Q

GS

G

G

Q

GD

Charge

Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit

www.vishay.com Document Number: 91389
6 S11-1055-Rev. C, 30-May-11

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THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

P.W.

Period

dI/dt

Diode recovery

dV/dt

Ripple ≤ 5 %

Body diode forward drop

Re-applied
voltage

Reverse
recovery
current

Body diode forward

current

V

GS

= 10 Va

I

SD

Driver gate drive

D.U.T. l

SD

waveform

D.U.T. V

DS

waveform

Inductor current

D =

P.W.

Period

+

-

+

+

+

-

-

-

Peak Diode Recovery dV/dt Test Circuit

V

DD

• dV/dt controlled by R

g

• Driver same type as D.U.T.

•

I

SD

controlled by duty factor “D”

• D.U.T. - device under test

D.U.T.

Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance

current transformer

R

g

Note

a. V

GS

= 5 V for logic level devices

V

DD

IRFBF30S, SiHFBF30S

Vishay Siliconix

Fig. 9 - For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91389

Document Number: 91389 www.vishay.com
S11-1055-Rev. C, 30-May-11 7

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

.

This document is subject to change without notice.

www.vishay.com/doc?91000

RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead

0.420

(10.668)

0.635
(16.129)

0.355

AN826

Vishay Siliconix

(9.017)

Return to Index

0.135

(3.429)

0.200

(5.080)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.050

(1.257)

0.145

(3.683)

Document Number: 73397
11-Apr-05

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1

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

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Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
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including but not limited to the warranty expressed therein.

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Revision: 13-Jun-16

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Document Number: 91000