VISHAY IL410, IL4108 User Manual

IL410/ IL4108

i179030

1

2

3

6

5

4

MT2

MT1

NC

A

C

NC

*Zero Crossing Circuit

ZCC*

Vishay Semiconductors

Optocoupler, Phototriac Output, Zero Crossing, High dV/dt, Low
Input Current

Features

• High Input Sensitivity

•I

= 2.0 mA, PF = 1.0

FT

•I

= 5.0 mA, PF ≤ 1.0

FT

• 300 mA On-State Current

• Zero Voltage Crossing Detector

• 600/800 V Blocking Voltage

• High Static dV/dt 10 kV/µs

• Inverse Parallel SCRs Provide Commutating
dV/dt >10 kV/µs

• Very Low Leakage < 10 µA

• Isolation Test Voltage 5300 V

RMS

• Small 6-Pin DIP Package

• Lead-free component

• Component in accordance to RoHS 2002/95/EC
and WEEE 2002/96/EC

Agency Approvals

• UL1577, File No. E52744 System Code H or J,
Double Protection

• CSA 93751

• BSI IEC60950 IEC60065

• DIN EN 60747-5-2 (VDE0884)
DIN EN 60747-5-5 pending
Available with Option 1

• FIMKO

Applications

Solid-state relays
Industrial controls
Office equipment
Consumer appliances.

Description

The IL410/ IL4108 consists of a GaAs IRLED optically
coupled to a photosensitive zero crossing TRIAC net­work. The TRIAC consists of two inverse parallel con­nected monolithic SCRs. These three semi­conductors are assembled in a six pin dual in-line
package.

High input sensitivity is achieved by using an emitter
follower phototransistor and a cascaded SCR pre­driver resulting in an LED trigger current of less than

2.0 mA (DC).
The IL410/ IL4108 uses two discrete SCRs resulting

in a commutating dV/dt greater than 10 kV/µs. The
use of a proprietary dV/dt clamp results in a static dV/
dt of greater than 10 kV/µs. This clamp circuit has a
MOSFET that is enhanced when high dV/dt spikes
occur between MT1 and MT2 of the TRIAC. When
conducting, the FET clamps the base of the pho­totransistor, disabling the first stage SCR predriver.

The zero cross line voltage detection circuit consists
of two enhancement MOSFETS and a photodiode.
The inhibit voltage of the network is determined by the
enhancement voltage of the N-channel FET. The P­channel FET is enabled by a photocurrent source that
permits the FET to conduct the main voltage to gate
on the N-channel FET. Once the main voltage can
enable the N-channel, it clamps the base of the pho­totransistor, disabling the first stage SCR predriver.

The 600/800 V blocking voltage permits control of off­line voltages up to 240 VAC, with a safety factor of
more than two, and is sufficient for as much as
380 VAC.

The IL410/ IL4108 isolates low-voltage logic from
120, 240, and 380 VAC lines to control resistive,
inductive, or capacitive loads including motors, sole­noids, high current thyristors or TRIAC and relays.

Document Number 83627

Rev. 1.4, 26-Apr-04

www.vishay.com

1

IL410/ IL4108

Vishay Semiconductors

Order Information

Par t Remarks

IL410 600 V V

IL4108 800 V V

IL410-X006 600 V V

IL410-X007 600 V V

IL410-X009 600 V V

IL4108-X006 800 V V

IL4108-X007 800 V V

IL4108-X009 800 V V

For additional information on the available options refer to
Option Information.

Absolute Maximum Ratings

T

= 25 °C, unless otherwise specified

amb

Stresses in excess of the absolute Maximum Ratings can cause permanent damage to the device. Functional operation of the device is
not implied at these or any other conditions in excess of those given in the operational sections of this document. Exposure to absolute
Maximum Rating for extended periods of the time can adversely affect reliability.

, DIP-6

DRM

, DIP-6

DRM

, DIP-6 400 mil (option 6)

DRM

, SMD-6 (option 7)

DRM

, SMD-6 (option 9)

DRM

, DIP-6 400 mil (option 6)

DRM

, SMD-6 (option 7)

DRM

, SMD-6 (option 9)

DRM

Input

Paramete r Test condition Symbol Val ue Unit

Reverse voltage V

Forward current I

Surge current I

Power dissipation P

Derate from 25 °C 1.33 mW/°C

R

F

FSM

diss

6.0 V

60 mA

2.5 A

100 mW

Output

Paramete r Test condition Par t Symbol Val ue Unit

Peak off-state voltage IL410 V

IL4108 V

RMS on-state current I

Single cycle surge current 3.0 A

Total power dissipation P

Derate from 25 °C 6.6 mW/°C

DM

DM

TM

diss

600 V

800 V

300 mA

500 mW

Coupler

Paramete r Test condition Symbol Val ue Unit

Isolation test voltage (between
emitter and detector, climate per
DIN 500414, part 2, Nov. 74)

Pollution degree (DIN VDE

0109)

Creepage ≥ 7.0 mm

Clearance ≥ 7.0 mm

t = 1.0 min. V

ISO

5300 V

2

RMS

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Document Number 83627

Rev. 1.4, 26-Apr-04

IL410/ IL4108

Vishay Semiconductors

Parameter Test condition Symbol Value Unit

Comparative tracking index per
DIN IEC 112/VDE 0303 part 1,
group IIIa per DIN VDE 6110

Isolation resistance V

Storage temperature range T

Ambient temperature range T

Soldering temperature max. ≤ 10 sec. dip soldering

= 500 V, T

IO

V

= 500 V, T

IO

= 25 °C R

amb

= 100 °C R

amb

≥ 0.5 mm from case bottom

T

IO

IO

stg

amb

sld

Electrical Characteristics

T

= 25 °C, unless otherwise specified

amb

Minimum and maximum values are testing requirements. Typical values are characteristics of the device and are the result of engineering
evaluation. Typical values are for information only and are not part of the testing requirements.

Input

Parameter Test condition Symbol Min Ty p. Max Unit

Forward voltage I

Reverse current V

Input capacitance V

Thermal resistance, junction to
ambient

= 10 mA V

F

= 6.0 V I

R

= 0 V, f = 1.0 MHz C

F

F

R

IN

R

thja

≥ 175

12

≥ 10

11

≥ 10

- 55 to + 150 °C

- 55 to + 100 °C

260 °C

1.16 1.35 V

0.1 10 µA

25 pF

750 °C/W

Ω

Ω

Output

Parameter Test condition Par t Symbol Min Ty p. Max Unit

Off-state voltage I

Repetitive peak off-state voltage I

Off-state current V

On-state voltage I

On-state current PF = 1.0, V

Surge (non-repetitive), on-state
current

Trigger current 1 V

Trigger current 2 V

Trigger current temp. gradient ∆I

Inhibit voltage temp. gradient ∆V

Off-state current in inhibit state I

Holding current I

Latching current V

Zero cross inhibit voltage I

Turn-on time V

Turn-off time PF = 1.0, I

= 70 µA IL410 V

D(RMS)

IL4108 V

= 100 µA IL410 V

DRM

IL4108 V

= V

, T

D

DRM

I

= 0 mA

F

V

= V

D

DRM

= 300 mA V

T

= 100 °C,

amb

, IF = Rated I

T(RMS)

FT

= 1.7 V I

f = 50 Hz I

= 5.0 V I

D

= 220 V, f = 50 Hz,

OP

T

= 100 °C, tpF > 10 ms

J

∆I

= I

, V

F

FT1

DRM

= 2.2 V I

T

= Rated I

F

RM

FT

= VDM = V

D(RMS)

= 300 mA t

T

D(RMS)

D(RMS)

DRM

DRM

I

D(RMS)1

I

D(RMS)2

TM

TM

TSM

FT1

I

FT2

FT1

FT2

DINH

I

DINH

H

L

V

IH

t

on

off

/∆T

/∆T

/∆T

424 460 V

565 V

600 V

800 V

10 100 µA

1.7 3.0 V

j

j

j

7.0 14 µA/°C

7.0 14 µA/°C

-20 mV/°C

50 200 µA

65 500 µA

5.0 mA

15 25 V

35 µs

50 µs

200 µA

300 mA

3.0 A

2.0 mA

6.0 mA

Document Number 83627

Rev. 1.4, 26-Apr-04

www.vishay.com

3

IL410/ IL4108

iil410_01

400350300250200150100500

.001

.01

.1

1

IL - Load Current - mA(RMS)

Cs - Shunt Capacitance - µF

Cs(µF) = 0.0032 (µF)* 10^(0.0066IL (mA)

Ta = 25°C, PF = 0.3

IF = 2.0 mA

Vishay Semiconductors

Paramete r Test condition Par t Symbol Min Ty p. Max Unit

Critical rate of rise of off-state
voltage

Critical rate of rise of voltage at
current commutation

Critical rate of rise of on-state dI/dt

Thermal resistance, junction to
ambient

Coupler

Paramete r Test condition Symbol Min Ty p. Max Unit

Critical rate of rise of coupled
input/output voltage

Common mode coupling
capacitance

Capacitance (input-output) f = 1.0 MHz, V

Isolation resistance V

VD = 0.67 V

= 0.67 V

V

D

V

= 0.67 V

D

≤ 15 A/ms, TJ = 25 °C

dI/dt

crq

V

= 0.67 V

D

≤ 15 A/ms, TJ = 80 °C

dI/dt

crq

= 0 A, VRM = VDM = V

I

T

= 500 V, T

IO

V

= 500 V, T

IO

, TJ = 25 °C dV/dt

DRM

, TJ = 80 °C dV/dt

DRM

,

DRM

,

DRM

= 0 V C

IO

= 25 °C R

amb

= 100 °C R

amb

D(RMS)

dV/dt

dV/dt

dVIO/dt 10000 V/µs

C

CM

IO

IO

IO

10000 V/µs

cr

cr

crq

crq

cr

R

thja

5000 V/µs

10000 V/µs

5000 V/µs

8.0 A/µs

150 °C/W

0.01 pF

0.8 pF

≥ 10

≥ 10

12

11

Ω

Ω

Power Factor Considerations

A snubber isn’t needed to eliminate false operation of
the TRIAC driver because of the IL410/ IL4108’s high
static and commutating dV/dt with loads between 1.0
and 0.8 power factors. When inductive loads with
power factors less than 0.8 are being driven, include
a RC snubber or a single capacitor directly across the
device to damp the peak commutating dV/dt spike.
Normally a commutating dV/dt causes a turning-off
device to stay on due to the stored energy remaining
in the turning-off device.

But in the case of a zero voltage crossing optotriac,
the commutating dV/dt spikes can inhibit one half of
the TRIAC from turning on. If the spike potential
exceeds the inhibit voltage of the zero cross detection
circuit, half of the TRIAC will be held-off and not turn­on. This hold-off condition can be eliminated by using
a snubber or capacitor placed directly across the
optotriac as shown in Figure 1. Note that the value of
the capacitor increases as a function of the load cur­rent.

Figure 1. Shunt Capacitance vs. Load Current

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Document Number 83627

Rev. 1.4, 26-Apr-04