VIS VG4632321AQ-55, VG4632321AQ-5, VG4632321AQ-45, VG4632321AQ-45R, VG4632321AQ-7R Datasheet
...
Preliminary VG4632321A
0.3V
±
524,288x32x2-Bit
VIS
Overview
The VG4632321A SGRAM is a high-speed CMOS synchronous graphic RAM containing 32M bits. It is
internally configured as a dual 512K x 32 DRAM with a synchronous interface (all signals are registered on
the positive edge of the clock signal, CLK). Each of the 512K x 32 bit bank is organized as 2048 rows by 256
columns by 32 bits. Read and write accesses to the SGRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed sequence. Accesses begin
with the registration of a BankActivate command which is then followed by a Read or Write command.
The VG4632321A provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with
burst termination option. An Auto Precharge function may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy
to use. In addition, it features the write per bit and the masked block write functions.
By having a programmable Mode register and special mode register, the system can choose the best
suitable modes to maximize its performance. These devices are well suited for applications requiring high
memory bandwidth, and when combined with special graphics functions result in a device particularly well
suited to high performance graphics applications.
Features
• Fast access time from clock: 4.5/5/5.5/6/7ns
• Fast clock rate: 222/200/183/166/143MHz
• Fully synchronous operation
• Internal pipelined architecture
• Dual internal banks(512K x 32-bit x 2-bank)
• Programmable Mode and Special Mode registers
- CAS Latency: 1, 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst Read Single Write
- Load Color or Mask register
• Burst stop function
• Individual byte controlled by DQM0-3
• Block write and write-per-bit capability
• Auto Refresh and Self Refresh
• 2048 refresh cycles/32ms
• Single + 3.3V power supply
• Interface: LVTTL
• JEDEC 100-pin Plastic QFP package
CMOS Synchronous Graphic RAM
Pin Assignment (Top View)
V
DQ0
DQ1
DQ3
V
DDQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
V
DDQ
DQ16
DQ17
V
SSQ
DQ18
DQ19
V
DDQ
V
DD
V
SS
DQ20
DQ21
V
SSQ
DQ22
DQ23
V
DDQ
DQM0
DQM2
WE
CAS
RAS
CS
BS
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
29
30
DQ2
100
28
V
SSQ
A0
NC
DD
9596979899
NC
A3
A2
V
A1
DD
NCNCNC
NC
NC
91
929394
40
393837363534333231
NC
NC
NC
NC
NC
90
89
88
41
42
43
NC
NCNCNCNCNC
NC
DQ29
DQ30
DQ31
V
V
SSQ
SS
83
84
82
858687
81
80
DQ28
V
79
DDQ
78
DQ27
77
DQ26
76
V
SSQ
75
DQ25
74
DQ24
73
V
DDQ
72
DQ15
71
DQ14
70
V
SSQ
69
DQ13
68
DQ12
67
V
DDQ
66
V
SS
65
V
DD
64
DQ11
63
DQ10
62
V
SSQ
61
DQ9
60
DQ8
59
V
DDQ
58
NC
57
DQM3
56
DQM1
55
CLK
54
CKE
53
DSF
52
47
48
464544
A5A4VSSA10
NC
50
49
51
A8/AP
A7
A6
Key Specifications
VG4632321A -4.5/-5/-5.5/-6/-7
t
t
RAS
t
t
CK
AC
RC
Clock Cycle time(min.) 4.5/5/5.5/6/7 ns
Row Active time(min.) 40/40/40/42/42 ns
Access time from CLK(max.) 4/4.5/5/5.5/6 ns
Row Cycle time(min.) 55/55/56.5/60/62 ns
Document: Rev.1 Page 1
VIS
Block Diagram
Preliminary VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
CLK
CKE
CS
RAS
CAS
WE
DSF
A0
A7
A9
A10
BS
~
A8
CLOCK
BUFFER
COMMAND
DECODER
COLUMN
COUNTER
ADDRESS
BUFFER
REFRESH
COUNTER
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
SPECIAL
MODE
REGISTER
Column Decoder
Row Decoder
COLOR
REGISTER
MASK
REGISTER
2048 X 256 X 32
2048 X 256 X 32
CELL ARRAY
(BANK #0)
Sense Amplifier
Sense Amplifier
CELL ARRAY
(BANK #1)
DQs
BUFFER
DQM0~31
DQ0
|
DQ31
Row Decoder
Column Decoder
Document: Rev.1 Page 2
Preliminary VG4632321A
524,288x32x2-Bit
VIS
Table 1 shows the details for pin number, symbol, type, and description.
CMOS Synchronous Graphic RAM
Table 1. Pin Description of VG4632321A
Pin Num-
ber
55 CLK Input Clock: CLK is driven by the system clock. All SGRAM input signals are sampled on
54 CKE Input Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If CKE
29 BS Input Bank Select: BS defines to which bank the BankActivate, Read, Write, or Bank-
30-34,
45,47-51
28 CS Input Chip Select: CS enables (sampled LOW) and disables (sampled HIGH) the
27 RAS Input Row Address Strobe: The RAS signal defines the operation commands in
26 CAS Input Column Address Strobe: The CAS signal defines the operation commands in
25 WE Input Write Enable: The WE signal defines the operation commands in conjunction with
53 DSF Input Define Special Function: The DSF signal defines the operation commands in
Symbol Type Description
the positive edge of CLK. CLK also increments the internal burst counter and
control the output registers.
goes low synchronously with clock (set-up and hold time same as other inputs), the
internal clock is suspended from the next clock cycle and the state of output and
burst address is frozen as long as the CKE remains low. When both banks are in
the idle state, deactivating the clock controls the entry to the Power Down and Self
Refresh modes. CKE is synchronous except after the device enters Power Down
and Self Refresh modes, where CKE becomes asynchronous until after exiting the
same mode. The input buffers, including CLK, are disabled during Power Down
and Self Refresh modes providing low standby power.
Precharge command is being applied. BS is also used to program the 10th bit of
the Mode and Special Mode registers.
A0-A10 Input Address Inputs: A0-A10 are sampled during the BankActivate command (row
address A0-A10) and Read/Write command (column address A0-A7 with A8
defining Auto Precharge) to select one location out of the 512K available in the
respective bank. During a Precharge command, A8 is sampled to determine if both
banks are to be precharged (A8 = HIGH). The address inputs also provide the
op-code during a Mode Register Set or Special Mode Register Set command.
command decoder. All commands are masked when CS is sampled HIGH. CS
provides for external bank selection on systems with multiple banks. It is
considered part of the command code.
conjunction with the CAS and WE signals, and is latched at the positive edges of
CLK. When RAS and CS are asserted “LOW” and CAS is asserted “HIGH”, either
the BankActivate command or the Precharge command is selected by the WE
signal. When the WE is asserted “HIGH” the BankActivate command is selected
and the bank designated by BS is turned on to the active state. When the WE is
asserted "LOW", the Precharge command is selected and the bank designated by
BS is switched to the idle state after precharge operation.
conjunction with the RAS and WE signals, and it is latched at the positive edges of
CLK. When RAS is held “HIGH” and CS is asserted “LOW”, the column access is
started by asserting CAS “LOW”. Then, the Read or Write command is selected by
asserting WE “LOW” or “HIGH”.
the RAS and CAS signals, and it is latched at the positive edges of CLK. The WE
input is used to select the BankActivate or Precharge command and Read or Write
command.
conjunction with the RAS and CAS and WE signals, and it is latched at the positive
edges of CLK. The DSF input is used to select the masked write disable/enable
command and block write command, and the Special Mode Register Set cycle.
Document: Rev.1 Page 3
VIS
0.3V
±
Preliminary VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
23,56,24,57DQM0-
DQM3
97,98,100,
1,3,4,6,7,
60,61,63,
64,68,69,
71,72,9,
10,12,13,
17,18,20,
21,74,75,
77, 78,80,
81, 83, 84
30,36-45,
52,58,
86-95
2,8,14,22,
59,67,73,
79
5,11,19,
62,70,76,
82,99
15,35,65,96V
DQ0-
DQ31
NC - No Connect: These pins should be left unconnected.
V
DDQ
V
SSQ
DD
Input Data Input/Output Mask: DQM0-DQM3 are byte specific, nonpersistent I/O buffer
controls. The I/O buffers are placed in a high-z state when DQM is sampled HIGH.
Input data is masked when DQM is sampled HIGH during a write cycle. Output data
is masked (two-clock latency) when DQM is sampled HIGH during a read cycle.
DQM3 masks DQ31-DQ24, DQM2 masks DQ23-DQ16, DQM1 masks DQ15-DQ8,
and DQM0 masks DQ7-DQ0.
Input/
Output
Supply DQ Power: Provide isolated power to DQs for improved noise immunity.
Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
Supply
Data I/O: The DQ0-31 input and output data are synchronized with the positive
edges of CLK. The I/Os are byte-maskable during Reads and Writes. The DQs also
serve as column/byte mask inputs during Block Writes.
Power Supply: +3.3V
16,46,66,85V
Supply Ground
SS
Document: Rev.1 Page 4
Preliminary VG4632321A
524,288x32x2-Bit
VIS
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2
shows the truth table for the operation commands.
BankActivate & Masked Write Disable
BankActivate & Masked Write Enable
BankPrecharge Any H X X V L X L L H L L
PrechargeAll Any H X X X H X L L H L L
Write
Block Write Command
Write and AutoPrecharge
Block Write and AutoPrecharge
Read
Read and AutoPrecharge
Mode Register Set Idle H X X V L V L L L L L
Special Mode Register Set
No-Operation Any H X X X X X L H H H X
Burst Stop
Device Deselect Any H X X X X X H X X X X
AutoRefresh Idle H H X X X X L L L H L
SelfRefresh Entry Idle H L X X X X L L L H L
SelfRefresh Exit Idle
Clock Suspend Mode Entry Active H L X X X X X X X X X
Power Down Mode Entry
Clock Suspend Mode Exit Active L H X X X X X X X X X
Power Down Mode Exit Any
Data Write/Output Enable Active H X L X X X X X X X X
Data Write/Output Disable Active H X H X X X X X X X X
Note: 1. V = Valid X = Don’t Care L = Low level H = High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. The Special Mode Register Set is also available in Row Active State.
6. Power Down Mode can not entry in the burst operation.
When this command assert in the burst cycle, device state is clock suspend mode.
7. DQM0-3
CMOS Synchronous Graphic RAM
Table 2. Truth Table (Note(1), (2))
Command State CKEn-1 CKEn
(3)
Idle
(3)
Idle
(3)
Active
(3)
Active
(3)
Active
(3)
Active
(3)
Active
(3)
Active
(5)
Idle
(4)
Active
(SelfRefresh)
(6)
Any
(Power-
Down)
H X X V V V L L H H L
H X X V V V L L H H H
H X X V L V L H L L L
H X X V L V L H L L H
H X X V H V L H L L L
H X X V H V L H L L H
H X X V L V L H L H L
H X X V H V L H L H L
H X X X X V L L L L H
H X X X X X L H H L L
L H X X X X H X X X X
H L X X X X H X X X X
L H X X X X H X X X X
DQM
(7)
BS A8 A0-7
CS RAS CAS WE DSF
A9,
A10
L H H H X
L H H H L
L H H H L
Document: Rev.1 Page 5
Preliminary VG4632321A
524,288x32x2-Bit
VIS
Commands
1 BankActivate & Masked Write Disable command
(RAS = ”L”, CAS = ”H”, WE = ”H”, DSF = ”L”, BS = Bank, A0-A10 = Row Address)
The BankActivate command activates the idle bank designated by the BS (Bank Select) signal. By
latching the row address on A0 to A10 at the time of this command, the selected row access is initiated.
The read or write operation in the same bank can occur after a time delay of t
bank activation. A subsequent BankActivate command to a different row in the same bank can only be
issued after the previous active row has been precharged (refer to the following figure). The minimum
time interval between successive BankActivate commands to the same bank is defined by tRC(min.).
The SGRAM has two internal banks on the same chip and shares part of the internal circuitry to reduce
chip area, therefore it restricts the back-to-back activation of both banks. t
minimum time required between activating different banks. After this command is used, the Write
command and the Block Write command perform the no mask write operation.
CLK
CMOS Synchronous Graphic RAM
T0 T1 T2 T3 Tn+3 Tn+4 Tn+5 Tn+6
(min.) from the time of
RCD
(min.) specifies the
RRD
ADDRESS
COMMAND
: “H” or “L”
Bank A
Row Addr.
Bank A
Activate
RAS-CAS delay (t
NOP
RCD
)
NOP
Bank A
Col Addr.
R/W A with
AutoPrecharge
RAS Cycle time (tRC)
Bank A
Row Addr.
Bank B
Activate
AutoPrecharge
Begin
RAS-RAS delay time (t
NOP
RRD
)
NOP
BankActivate Command Cycle (Burst Length = n, CAS Latency = 3)
2 BankActivate & Masked Write Enable command (refer to the above figure)
(RAS = ”L”, CAS = ”H”, WE = ”H”, DSF = ”H”, BS = Bank, A0-A10 = Row Address)
The BankActivate command activates the idle bank designated by BS signal. After this command is
performed, the Write command and the Block Write command perform the masked write operation. In
the masked write and the masked block write functions, the I/O mask data that was stored in the write
mask register is used.
3 BankPrecharge command
(RAS = ”L”, CAS = ”H”, WE = ”L”, DSF = ”L”, BS = Bank, A8 = ”L”, A0-A7,A9,A10 = Don’t care)
The BankPrecharge command precharges the bank designated by BS signal. The precharged
bank is switched from the active state to the idle state. This command can be asserted anytime after
t
(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any
RAS
bank can be active is specified by t
any active bank within t
(max.). At the end of precharge, the precharged bank is still the idle state and
RAS
(max.). Therefore, the precharge function must be performed in
RAS
ready to be activated again.
Bank A
Row Addr.
Bank A
Activate
4 PrechargeAll command
(RAS = ”L”, CAS = ”H”, WE = ”L”, DSF = ”L”, BS = Don’t care, A8 = ”H”, A0-A7,A9,A10 = Don’t care)
The PrechargeAll command precharges both banks simultaneously. Even if both banks are not in
the active state, the PrechargeAll command can be issued. Both banks are then switched to the idle
state.
5 Read command
(RAS = ”H”, CAS = ”L”, WE = ”H”, DSF = ”L”, BS = Bank, A8 = ”L”, A0-A7 = Column Address, A9,A10 = Don’t
care)
Document: Rev.1 Page 6
VIS
in an active bank. The bank must be active for at least t
During read bursts, the valid data-out element from the starting column address will be available
following the CAS latency after the issue of Read command. Each subsequent data-out element will
be valid by the next positive clock edge (refer to the following figure). The DQs goes into
high-impedance at the end of the burst, unless other command was initiated. The burst length, burst
sequence, and CAS latency are determined by the mode register which is already prgrammed.A
full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue).
Preliminary VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
The Read command is used to read burst of data on consecutive clock cycles from an active row
(min.) before Read command is issued.
RCD
T6
NOP
3
DOUT A
2
3
CLK
COMMAND
CAS Iatency = 1
t
,DQ’s
CK1
CAS Iatency = 2
t
,DQ’s
CK2
CAS Iatency = 3
t
,DQ’s
CK3
T0
READ A
T1
NOP
DOUT A
T2
NOP
DOUT A
0
DOUT A
T3
NOP
DOUT A
1
DOUT A
0
DOUT A
T4
NOP
DOUT A
2
DOUT A
1
DOUT A
0
T5
NOP
3
DOUT A
2
DOUT A
1
Burst Read Operation (Burst Length = 4, CAS Latency = 1, 2, 3)
The read data appears on the DQs subjects to the values on the DQM inputs two clocks early (i.e.
DQM latency is two clocks for output buffers). A read burst without auto precharge function may be
interrupted by a subsequent Read or Write/Block Write command to the same bank or the other
active bank before the end of burst length. It may be interrupted by a BankPrecharge/PrechargeAll
command to the same bank too. The interrupt comes from Read command can occur on any clock
cycle following a previous Read command (refer to the following figure).
T0
T1
T2
T3
T4
T5
T6
T7 T8
NOP
T7 T8
NOP
CLK
COMMAND
CAS Iatency = 1
t
,DQ’s
CK1
CAS Iatency = 2
t
,DQ’s
CK2
CAS Iatency = 3
t
,DQ’s
CK3
READ A
READ B
DOUT A
NOP
DOUT B
0
DOUT A
NOP
DOUT B
0
DOUT B
0
DOUT A
NOP
DOUT B
1
DOUT B
0
DOUT B
0
NOP
DOUT B
2
DOUT B
1
DOUT B
0
NOP
3
DOUT B
DOUT B
3
2
2
1
Read Interrupted by a Read (Burst Length = 4, CAS Latency = 1, 2, 3)
The DQM inputs are used to avoid I/O contention on DQ pins when the interrupt comes from
Write/Block Write command. The DQMs must be asserted (High) at least two clocks prior to the
Write/Block Write command to suppress data-out on DQ pins. To guarantee DQ pins against the I/O
contention, a single cycle with high-impedance on DQ pins must occur between the last read data
and the Write/Block Write command (refer to the following three figures). If the data output of burst
read occurs at the second clock of burst write, the DQMs must be asserted (High) at least one clock
prior to the Write/Block Write command to avoid internal bus contention.
NOP
DOUT B
NOP
3
Document: Rev.1 Page 7
VIS
Preliminary VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
CLK
DQM
COMMAND
DQ’s
: “H” or “L”
CLK
DQM
COMMAND
T0
NOP
T0
NOP
T1
READ A
T2
NOP
T3
NOP
T4
NOP
DOUT A
0
Must be Hi-Z before
the Write Command
Read to Write interval (Burst Length
T1
NOP
T2
BANK A
ACTIVATE
T3
NOP
T4
1 Clk Interval
READ A
T5
NOP
°Ÿ
T5
WRITE A
T6
WRITE B
DINB
0
4, CAS Latency = 3)
T6
NOP
T7 T8
NOP
DINB
1
T7
NOP NOP
DINB
T8
NOP
2
CAS Iatency = 1
t
,DQ’s
CK1
CAS Iatency = 2
t
,DQ’s
CK2
: “H” or “L”
CLK
DQM
COMMAND
CAS Iatency = 1
t
,DQ’s
CK1
CAS Iatency = 2
t
,DQ’s
CK2
: “H” or “L”
T0
NOP
Must be Hi-Z before
the Write Command
Read to Write interval (Burst Length
T1
NOP
T2
READ A
T3
NOP
DOUT A
T4
NOP
0
Must be Hi-Z before
the Write Command
Read to Write interval (Burst Length
DIN A
DIN A
°Ÿ
T5
WRITE B
DIN B
DIN B
°Ÿ
0
0
0
DIN A
1
DIN A
1
4, CAS Latency = 1, 2)
T6
NOP
DIN B
DIN B
1
1
0
4, CAS Latency = 1, 2)
DIN A
T7
DIN A
NOP
DINB
DIN B
DIN A
2
2
2
2
DIN A
T8
NOP
DIN B
DIN B
3
3
3
3
A read burst without auto precharge function may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank. The following figure shows the optimum time that
BankPrecharge/PrechargeAll command is issued in different CAS latency.
Document: Rev.1 Page 8
VIS
Preliminary VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
T6
t
RP
NOP
3
DOUT A
2
T7
Bank
Row
Activate
3
T8
NOP
CLK
ADDRESS
COMMAND
CAS Iatency = 1
t
,DQ’s
CK1
CAS Iatency = 2
t
,DQ’s
CK2
CAS Iatency = 3
t
,DQ’s
CK3
T0
Bank
Col A
READ A
T1
NOP
DOUT A
T2
NOP
DOUT A
0
DOUT A
T3
NOP
DOUT A
1
DOUT A
0
DOUT A
T4
Bank(s)
Precharge
DOUT A
2
DOUT A
1
DOUT A1DOUT A
0
T5
NOP
3
DOUT A
2
Read to Precharge (CAS Latency = 1, 2, 3)
6 Read and AutoPrecharge command
(RAS = ”H”, CAS = ”L”, WE = ”H”, DSF = ”L”, BS = Bank, A8 = ”H”, A0-A7 = Column Address, A9,A10 = Don’t
care)
The Read and AutoPrecharge command automatically performs the precharge operation after the read
operation. Once this command is given, any subsequent command can not occur within a time delay of
{tRP(min.) + burst length}. At full-page burst, only read operation is performed in this command and the auto
precharge function is ignored.
7 Write command
(RAS = ”H”, CAS = ”L”, WE = ”L”, DSF = “L”, BS = Bank, A8 = ”L”, A0-A7 = Column Address, A9,A10 = Don’t
care)
The Write command is used to write burst of data on consecutive clock cycles from an active row in an
active bank. The bank must be active for at least t
(min.) before Write command is issued. During write
RCD
bursts, the first valid data-in element will be registered coincident with the Write command. Subsequent data
elements will be registered on each successive positive clock edge (refer to the following figure). The DQs
remains high-impedance at the end of the burst, unless other command was initiated. The burst length and
burst sequence are determined by the mode register which is already programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue).
T6
NOP
T7 T8
NOP
NOP
CLK
COMMAND
DQ0 - DQ3
T0
NOP
The first data element and the write
are registered on the same clock edge.
T1
WRITE A
DIN A
T2
NOP
DIN A
0
T3
NOP
DIN A
1
T4
NOP
DIN A
2
T5
NOP
don’t care
3
Extra data is masked.
Burst Write Operation (Burst Length = 4, CAS Latency = 1, 2, 3)
Any Write performed to a row that was opened via an BankAcitvate & Masked Write Enable command is a
masked write (Write-Per-Bit). Data is written to the 32 cells (bits) at the selected column location subject to the
data stored in the Mask register. The overall mask consists of the DQM inputs, which mask on a per-byte
basis, and the Mask register, which masks on a per-bit basis. This is shown in the following block diagram.
Document: Rev.1 Page 9
VIS
Preliminary VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
DSF
BankActivate
command
D
CK
MR7
MR6
MR5
MR4
MR3
MR2
Q
DQM0
DRAM
CELL
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
MR1
DQ0
MR0
0 = Masked
1 = Not Masked
Note: Only lower byte is shown. The operation is identical for other bytes.
Write Per Bit (I/O Mask) Block Diagram
A write burst without auto precharge function may be interrupted by a subsequent Write/Block
Write, BankPrecharge/PrechargeAll, or Read command before the end of burst length. The interrupt
comes from Write/Block Write command can occur on any clock cycle following the previous Write
command ( refer to the following figure).
T6
NOP
T7 T8
NOP
CLK
COMMAND
T0
NOP WRITE A
T1
1 Clk Interval
T2
WRITE B
T3
NOP
T4
NOP
T5
NOP
NOP
DQ’s
DIN A
DIN B
0
DIN B
0
DIN B
1
DIN B
2
3
Write Interrupted by a Write (Burst Length = 4, CAS Latency = 1, 2, 3)
The Read command that interrupts a write burst without auto precharge function should
be issued one cycle after the clock edge at which the last data-in element is registered. In
order to avoid data contention, input data must be removed from the DQs at least one clock
cycle before the first read data appears on the outputs (refer to the following figure). Once the
Read command is registered, the data inputs will be ignored, and writes will not be executed.
Document: Rev.1 Page 10
VIS
Preliminary VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
T6
NOP
DOUT B
2
DOUT B
1
0
DOUT B
T7 T8
3
DOUT B
2
DOUT B
1
NOP
CLK
COMMAND
CAS latency = 1
t
,DQ’s
CK1
CAS latency = 2
t
,DQ’s
CK2
CAS latency = 3
t
,DQ’s
CK3
T0
NOP
T1
WRITE A
DIN A
DIN A
DIN A
Input data for the write is masked
T2
READ B NOP
0
0
don’t care
don’t care
0
T3
NOP
DOUT B
don’t care
T4
DOUT B
0
DOUT B
T5
NOP
DOUT B
1
DOUT B
0
DOUT B
Input data must be removed from DQ’
cycle before the Read data appears on the outputs to avoid
data contention
Write Interrupted by a Read (Burst Length = 4, CAS Latency = 1, 2, 3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without auto precharge function should be issued m cycles after the clock edge at which the last data-in element
is registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the
DQM signals must be used to mask input data, starting with the clock edge following the last
data-in element and ending with the clock edge on which the BankPrecharge/PrechargeAll
command is entered (refer to the following figure).
NOP
3
DOUT B
2
s at least one clock
3
T0 T1 T2 T3 T4 T5 T6
CLK
DQM
t
RP
COMMAND
ADDRESS
DQ
:don’t care
WRITE NOP
BANK
COLn
DIN
n
NOP
DIN
n+1
t
WR
Precharge
BANK (S)
Write to Precharge
NOP
Activate
ROW
NOP
When Burst-Read and Single-Write mode is selected , the write burst length is 1 regardless of the
read burst length (refer to Figures 21 and 22 in Timing Waveforms).
8 Block Write command
(RAS = “H” , CAS = “L” , WE = “L”, DSF = “H” , BS =Bank , A8 = “L” , A3-A7 = Column Address, DQ0-DQ31
= Column Mask)
The block writes are non-burst accesses that write to eight column locations simultaneously. A single
data value, which was previously loaded in the Color register, is written to the block of eight consecutive
column locations addressed by inputs A3-A7. The information on the DQs which is registered coincident with
the Block Write command is used to mask specific column/byte combinations within the block . The mapping
of the DQ inputs to the column/byte combinations is shown in following table.
Document: Rev.1 Page 11
VIS
DQ
inputs
DQ0 0 0 0 0~7 DQ16 0 0 0 16~23
DQ1 0 0 1 0~7 DQ17 0 0 1 16~23
DQ2 0 1 0 0~7 DQ18 0 1 0 16~23
DQ3 0 1 1 0~7 DQ19 0 1 1 16~23
DQ4 1 0 0 0~7 DQ20 1 0 0 16~23
DQ5 1 0 1 0~7 DQ21 1 0 1 16~23
DQ6 1 1 0 0~7 DQ22 1 1 0 16~23
DQ7 1 1 1 0~7 DQ23 1 1 1 16~23
DQ8 0 0 0 8~15 DQ24 0 0 0 24~31
DQ9 0 0 1 8~15 DQ25 0 0 1 24~31
DQ10 0 1 0 8~15 DQ26 0 1 0 24~31
DQ11 0 1 1 8~15 DQ27 0 1 1 24~31
DQ12 1 0 0 8~15 DQ28 1 0 0 24~31
DQ13 1 0 1 8~15 DQ29 1 0 1 24~31
DQ14 1 1 0 8~15 DQ30 1 1 0 24~31
DQ15 1 1 1 8~15 DQ31 1 1 1 24~31
Preliminary VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
Column Address DQ Planes
A2 A1 A0 A2 A1 A0
Controlled
DQ
Inputs
Column Address DQ Planes
Controlled
The overall Block Write mask consists of a combination of the DQM inputs, the Mask register,
and the column/byte mask information, as shown in the following diagram. The DQM and Mask register masking operates as for normal Write command, with the exception that the mask information
is applied simultaneously to all eight columns. Therefore, in a Block Write, a given bit is written only if
a ”0” was registered for the corresponding DQM input, a ”1” was registered for the corresponding DQ
signal, and the corresponding bit in the Mask register is ”1”.
A block write access requires a time period of t
m NOP cycles, m equals (t
command. However, BankActivate or BankPrecharge commands to the other bank are allowed.
When following a Block Write with a BankPrecharge or PrechargeAll command to the same bank, t
must be met.
BWC-tCK
) /tCK rounded up to the next whole number, after the Block Write
to execute, so in general, there should be
BWC
BPL
Document: Rev.1 Page 12
VIS
Preliminary VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
Block of Columns
(selected by A3-A7 registered
coincident with Block Write command)
Row in Bank
(selected by A0-A10,
and BS registered
coincident with BankActivate
Command)
Column Mask
on the DQ
inputs
(registered
coincident
with Block
Write Command
BankActivate
command
Mask Register
(previously loaded
from corresponding
DQ inputs
Note: Only lower byte is shown. The operation is identical for other bytes.
DSF
D Q
CK
MR0
MR1
MR2
MR3
MR4
MR5
MR6
MR7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMO
CR0
CR1
CR2
CR3
CR4
CR5
CR6
CR7
Block-Write Masking Block Diagram
Document: Rev.1 Page 13
VIS
9 Write and AutoPrecharge command (refer to the following figure)
Preliminary VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
(RAS = “H” , CAS = “L” , WE = “L” , DSF=”L” , BS = Bank, A8 = ”H”, A0-A7 = Column Address,
A9,A10 = Don’t care)
The Write and AutoPrecharge command performs the precharge operation automatically after
the write operation. Once this command is given, any subsequent command can not occur within a
time delay of {burst length + tWR + tRP(min.)}. At full-page burst, only write operation is performed in
this command and the auto precharge function is ignored.
NOP
T2
T3
Write A
Auto Precharge
DIN A
DIN A
DIN A
T4
NOP
DIN A
0
DIN A
0
DIN A
0
T5
NOP
t
DAL
1
*
T6
NOP
t
DAL
T7
NOP
*
1
t
DAL
1
*
Begin AutoPrecharge
*
Bank can be reactivated at completion of t
CLK
COMMAND
CAS latency = 1
t
,DQ’s
ck1
CAS latency = 2
t
,DQ’s
ck2
CAS latency = 3
t
,DQ’s
ck3
T0
Bank A
Activate
t
DAL
T1
NOP
= t
+ t
WR
RP
Burst Write with Auto-Precharge (Burst Length = 2, CAS Latency = 1, 2, 3)
10 Block Write and AutoPrecharge command
(RAS = “H” , CAS = “L” , WE = “H”, DSF = “H” , BS = Bank , A8 = “H” , A3-A7 = Column Address,
A9,A10 = Don’t care DQ0-DQ31 = Column Mask)
The Block Write and AutoPrecharge command performs the precharge operation automatically after
the block write operation. Once this command is given, any subsequent command can not occur within a
time delay of {t
+ tRP (min.)}.
BPL
T8
NOP
DAL
11 Mode Register Set command
(RAS = “L” , CAS = ”L”, WE = “L” , DSF = “L” , BS , A0-A10 = Register Data)
The mode register stores the data for controlling the various operating modes of SGRAM. The Mode
Register Set command programs the values of CAS latency. Addressing Mode and Burst Length in the
Mode register to make SGRAM useful for variety of different applications. The default values of the Mode
Register after power-up are undefined, therefore this command must be issued at the power-up
sequence. The state of pins A0-A10 and BS in the same cycle is the data written in the mode register.
One clock cycle is required to complete the write in the mode register (refer to the following figure ). The
mode register contents can be changed using the same command and the clock cycle requirements during operation as long as both banks are in the idle state.
Document: Rev.1 Page 14
VIS
Preliminary VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
CLK
CKE
RAS
CAS
WE
DSF
T7
T8
T10T9
tCK2
T1
T2 T3 T4
Clock min
T0
CS
BS
T5 T6
A8
Address key
A0-A7,
A9,A10
DQM
t
DQ
Hi-Z
PrechargeAll
Mode Register Set Cycle (
RP
Mode Register
Set Command
Any
Command
CAS
Latency = 1, 2, 3)
The mode register is divided into various fields depending on functionality.
• Burst Length Field (A2~A0)
This field specifies the data length of column access using the A2~A0 pins and selects the
Burst Length to be 1, 2, 4, 8, or full page.
A2 A1 A0 Burst Length
0 0 0 1
0 0 1 2
0 1 0 4
0 1 1 8
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Full Page
Document: Rev.1 Page 15
Preliminary VG4632321A
≤
524,288x32x2-Bit
VIS
• Addressing Mode Select Field (A3)
The Addressing Mode can be one of two modes, Interleave Mode or Sequential Mode.
Sequential Mode supports burst length of 1, 2, 4, 8, or full page. But, lnterleave Mode only supports
burst length of 4 and 8.
A3 Addressing Mode
--- Addressing Sequence of Sequential Mode
An internal column address is performed by increasing the address from the column
address which is input to the device. The internal column address is varied by the Burst
Length as shown in the following table. When the value of column address, (n+m), in the
table is larger than 255, only the least significant 8 bits are effective.
Data n 0 1 2 3 4 5 6 7 - 255 256 257 -
Column Address n n+1 n+2 n+3 n+4 n+5 n+6 n+7 - n+255 n n+1 -
CMOS Synchronous Graphic RAM
0 Sequential
1 Interleave
2 words:
Burst Length
--- Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the
address bits in the sequence shown in following table.
Data n Column Address Burst Length
Data 0 A7 A6 A5 A4 A3 A2 A1 A0
Data 1 A7 A6 A5 A4 A3 A2 A1 A0
Data 2 A7 A6 A5 A4 A3 A2 A1 A0
Data 3 A7 A6 A5 A4 A3 A2 A1 A0
Data 4 A7 A6 A5 A4 A3 A2 A1 A0
Data 5 A7 A6 A5 A4 A3 A2 A1 A0
Data 6 A7 A6 A5 A4 A3 A2 A1 A0
Data 7 A7 A6 A5 A4 A3 A2 A1 A0
• CAS Latency Field (A6 ~ A4)
This field specifies the number of clock cycles from the assertion of the Read command
to the first read data. The minimum value of CAS Latency depends on the frequency of
CLK. And this value satisfying the following formula must be programmed into this field.
t
CAC (min)
CAS Latency x t
A6 A5 A4 CAS Latency
0 0 0 Reserved
0 0 1 1 clock
0 1 0 2 clocks
0 1 1 3 clocks
1 X X Reserved
4 words:
8 words:
Full Page: Column address is repeated until terminated.
4 Words
CK
8 Words
Document: Rev.1 Page 16
VIS
• Mode field (A8~A7)
A7 and A8 must be programmed to “00” in normal operation.
A8 A7 Test Mode
0 0 normal mode
0 1 Vendor Use Only
1 x Vendor Use Only
• Single Write Mode (A9)
This bit is used to select the write mode. When the A9 bit is “0”, Burst Read and Burst Write mode is
selected. When the A9 bit is ”1”, Burst Read and Single Write mode is Selected.
A9 Single Write Mode
0 Burst Read and Burst Write
1 Burst Read and Single Write
Preliminary VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
12 Special Mode Register Set command
(RAS = ”L”, CAS = ”L”, WE = ”L”, DSF = ”H”, BS, A0-A10 = Register Data)
The special mode register is used to load the Color and Mask registers, which are used in Block
Write and masked Write cycles. The control information being written to the Special Mode register is
applied to the address inputs and the data to be written to either the Color register or the Mask register is
applied to the DQs. When A6 is “high” during a Special Mode Register Set cycle, the Color register will be
loaded with the data on the DQs. Similarly, when A5 is “high” during a Special Mode Register Set cycle,
the Mask register will be loaded with the data on the DQs. A6 = A5 = 1 in the Special Mode Register Set
cycle is illegal.
Functions BS A10~A7 A6 A5 A4~A0
Leave Unchanged X X 0 0 X
Load Mask Register X X 0 1 X
Load Color Register X X 1 0 X
Illegal X X 1 1 X
One clock cycle is required to complete the write in the Special Mode register. This command can
be issued at the active state. As in write operation, this command accepts the data needed through DQ
pins. Therefore it should be attended not to induce bus contention.
13 No-Operation command
(RAS = ”H”, CAS = ”H”, WE = ”H”)
The No-Operation command is used to perform a NOP to SGRAM which is selected (CS is Low).
This prevents unwanted commands from being registered during idle or wait states.
14 Burst Stop command
(RAS = ”H”, CAS = ”H”, WE = ”L’, DSF = ”L”)
Burst Stop command is used to terminate either fixed-length or full-page bursts. This command is
only effective in a read/write burst without auto precharge function. The terminated read burst ends after
a delay equal to the CAS latency (refer to the following figure). The termination of a write burst is shown
in the following figure.
Document: Rev.1 Page 17
VIS
Preliminary VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
CLK
COMMAND
CAS Iatency = 1
t
,DQ’s
CK1
CAS Iatency = 2
t
,DQ’s
CK2
CAS Iatency = 3
t
,DQ’s
CK3
Termination of a Burst Write Operation (Burst Length > 4, CAS Latency = 1, 2, 3)
CLK
COMMAND
CAS latency = 1, 2, 3
DQ’s
NOP
T6
NOP
3
DOUT A
2
T6
NOP
3
T7 T8
NOP
T7 T8
NOP
NOP
NOP
T0
READ A
T0
NOP
T1
NOP
DOUT A
WRITE A
DIN A
T2
NOP
DOUT A
0
DOUT A
T1
T2
NOP
DIN A
0
T3
NOP
DOUT A
1
DOUT A
0
DOUT A
T3
NOP
DIN A
1
T4
Burst Stop
DOUT A
2
DOUT A
1
DOUT A
0
T4
Burst Stop
don’t care
2
Input data for the Write is masked.
T5
NOP
The burst ends after a delay equal to the CAS latency.
3
DOUT A
2
DOUT A
1
T5
Termination of a Burst Write Operation (Burst Length = X, CAS Latency = 1, 2, 3)
15 Device Deselect command
(CS = ”H”)
The Device Deselect command disables the command decoder so that the RAS, CAS, WE
and Address inputs are ignored, regardless of whether the CLK is enabled. This command is
similar to the No Operation command.
16 AutoRefresh command (refer to Figures 3 & 4 in Timing Waveforms)
(RAS = ”L”, CAS = ”L”, WE = ”H”, DSF = ”L”, CKE = ”H”, BS, A0-A10 = Don’t care)
The AutoRefresh command is used during normal operation of the SGRAM and is
analagous to CAS-before-RAS(CBR) Refresh in conventional DRAMs. This command is
non-persistent, so it must be issued each time a refresh is required. The addressing is generated
by the internal refresh controller. This makes the address bits a “don’t care” during an
AutoRefresh command. The internal refresh counter increments automatically on every auto
refresh cycle to all of the rows. The refresh operation must be performed 2048 times within
32ms. The time required to complete the auto refresh operation is specified by tRP(min.). To
provide the AutoRefresh command, both banks need to be in the idle state and the device is not
in power down mode (CKE is high in the previous cycle). This command must be followed by
NOPs until the auto refresh operations is completed. The precharge time requirement, tRP(min.)
must be met befor successive auto refresh operations are performed.
17 SelfRefresh Entry command (refer to Figure 5 in Timing Waveforms)
(RAS = ”L”, CAS = ”L”, WE = ”H”, DSF = ”L”, CKE = ”L”, BS, A0-A10 = Don’t care)
The SelfRefresh is another refresh mode available in the SGRAM. It is the preferred refresh
mode for data retention and low power operation. Once the SelfRefresh command is registered,
all the inputs to the SGRAM becomes “don’t care” with the exception of CKE, which must remain
LOW. The refresh addressing and timing is internally generated to reduce power comsumption.
The SGRAM may remain in SelfRefresh mode for an indefinite period. Once the SGRAM enters
the SelfRefresh mode , t
(min.) is required before exit from SelfRefresh mode. The
RAS
SelfRefresh mode is exited by restarting the external clock and then asserting high on CKE(SelfRefresh Exit command).
Document: Rev.1 Page 18
Preliminary VG4632321A
524,288x32x2-Bit
VIS
18 SelfRefresh Exit command (refer to Figure 5 in Timing Waveforms)
(CKE = ”H”, CS = ”H” or CKE = ”H”, RAS = ”H”, CAS = ”H”, WE = ”H”)
NOP or Device Deselect commands must be issued for tRC(min), because time is required for the
completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are performed during normal operation, a burst of 1024 auto refresh cycles should be completed just prior to
entering, and just after exiting the SelfRefresh mode.
19 Clock Suspend Mode Entry/PowerDown Mode Entry command (refer to Figures 6, 7, and 8 in Timing
Waveforms)
(CKE = ”L”)
sequent cycle by issuing this command (asserting CKE ”low”). The device operation is held intact
while CLK is suspended. On the other hand, when both banks are in the idle state, this command performs entry into the PowerDown mode. All input and output buffers (except the CKE buffer) are turned
off in the PowerDown mode. The device may not remain in the Clock Suspend or PowerDown state
longer than the refresh period (16ms) since the command does not perform any refresh operations.
20 Clock Suspend Mode Exit/PowerDown Mode Exit command (refer to Figures 6, 7, and 8 in Timing
Waveforms)
(CKE = ”H”)
the subsequent cycle by providing this command (asserting CKE “high”). When the device is in the
PowerDown mode, the device exits this mode and all disabled buffers are turned on to the active
state. t
mands can be issued after one clock cycle from the end of this command.
CMOS Synchronous Graphic RAM
The command is used to exit from the SelfRefresh mode. Once this command is registered,
When SGRAM operating the burst cycle, the internal CLK is suspended (masked) from the sub-
When the internal CLK has been suspended, the operation of the internal CLK is resumed from
(min.) is required when the device exit from the PowerDown mode. Any subsequent com-
PDE
21 Data Write/Output Enable, Data Mask/Output Disable command
(DQM = ”L”, ”H”)
During a write cycle, the DQM signal functions as Data Mask and can control every word of the
input data. During a read cycle, the DQM functions as the control of output buffers. DQM is also used
for device selection, byte selection and bus control in a memory system. DQM0 controls DQ0 to DQ7,
DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23, DQM3 controls DQ24 to DQ31, DQM
masks the DQ’s by a byte regardless that the corresponding DQ’s are in a state of write-per-bit masking or pixel masking. the byte control. The each DQM0-3 corresponds to DQ0-7, DQ8-15, DQ16-23,
DQ24-31.
Document: Rev.1 Page 19
Preliminary VG4632321A
524,288x32x2-Bit
VIS
Absolute Maximum Rating
Symbol Item Rating Unit
VIN, V
VDD, V
T
OPR
T
STG
T
SOLDER
P
I
OUT
Recommended D.C. Operating Conditions (Ta = 0~70°C)
Symbol Parameter Min. Typ. Max. Unit
V
DD
V
DDQ
V
IH
V
IL
CMOS Synchronous Graphic RAM
OUT
DDQ
D
Power Supply Voltage (for I/O Buffer) 3.0 3.3 3.6 V
LVTTL Input High Voltage 2.0 - VDD+ 0.3 V
LVTTL Input Low Voltage -0.3 - 0.8 V
Input, Output Voltage -0.3~VDD + 0.3 V
Power Supply Voltage -0.3~4.6 V
Operating Temperature 0~70 °C
Storage Temperature -55~150 °C
Soldering Temperature(10s) 260 °C
Power Dissipation 1 W
Short Circuit Output Current 50 mA
Power Supply Voltage 3.0 3.3 3.6 V
Capacitance (VDD = 3.3V, f = 1MHz, Ta = 25°C)
Symbol Parameter Min. Max. Unit
C
I
C
I/O
Note: These parameters are periodically sampled and are not 100% tested.
Input Capacitance - 5 pF
Input/Output Capacitance - 7 pF
Document: Rev.1 Page 20
Preliminary VG4632321A
±
t
t
()
≥
CKEV
IH
≥∞CKEV
≥
≤
CKEV
≤∞CKEV
≤
≤
CKEV
IH
≥
CKEV
IL
≤
≥
tRCtRC≥
CKE0.2V
≤
0VVINVDD≤≤
µ
0VV
≤≤
µ
524,288x32x2-Bit
VIS
CMOS Synchronous Graphic RAM
Recommended D.C. Operating Conditions (VDD = 3.3V 0.3V, Ta = 0 ~ 70°C)
-4.5 -5 -5.5 -6 -7 Unit Note
Description/test condition Symbol
Operating Current
RC
RCmin
Address changed once during t
, Outputs Open
CK(min)
.
Burst Length = 1, One bank active
Precharge Standby Current in non power-down
mode
t
= 15ns,
CK
CSVIH≥
,
(min)
(min)
Input signals are changed once during 30ns.
Precharge Standby Current in non power-down
mode
t
= ,
CK
,
CLKV
(min)
IH
IL
(max)
Input signals are stable
Precharge Standby Current in power-down
mode
t
=15ns,
CK
IL
(max)
I
I
DD2N
I
DD2NS
I
DD2P
Min. Max. Min. Max. Min. Max Min. Max. Min. Max.
DD1
230 220 210 200 180
45 45 45 45 45 3
20 20 20 20 20
2 2 2 2 2 3
3,4
mA
Precharge Standby Current in power-down
mode
t
= ,
CK
IL
(max)
,
CLKV
IL
(max)
Active Standby Current in non power down
mode
, t
(min)
= 15ns(Both Bank Active)
CK
Input signals are changed once during 30ns.
Active Standby Current in power-down mode
, t
CK =
15ns,
CS V
(max)
(Both Bank Active)
IH(min)
Operating Current (Page Burst, and All Bank
activated)
t
CCD
= t
CCD(min)
, Outputs Open,
Multi-bank interleave, gapless data
Refresh Current
(t
REF
= 32ms)
(min)
Self Refresh Current I
Operating Current (One Bank Block Write)
t
CK
= t
, Outputs Open, t
CK(min)
BWC
= t
BWC(min)
I
DD2PS
I
DD3N
I
DD3P
I
DD4
I
DD5
DD6
I
DD7
2 2 2 2 2
50 50 50 50 50 3
5 5 5 5 5
310 290 275 260 230 4,5
230 220 210 200 180 3
3.5 3.5 3.5 3.5 3.5
230 210 200 180 150
Parameter Description Min. Max. Unit Note
I
IL
Input Leakage Current
-5 5 A
(All other pins not under test = 0V)
I
OL
V
OH
Output Leakage Current
Output disable, ()
OUTVDDQ
LVTTL Output ”H” Level Voltage
(l
= -2mA)
OUT
-5 5 A
2.4 - V
Document: Rev.1 Page 21
VIS
Preliminary VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
V
OL
LVTTL Output ”L” Level Voltage
(l
= 2mA)
OUT
- 0.4 V
Document: Rev.1 Page 22
Preliminary VG4632321A
±
524,288x32x2-Bit
VIS
Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 3.3V0.3V, Ta = 0~70°C) (Note: 6, 7, 8, 9, 10) *** CL is CAS Latency.
symbol A.C. Parameter -4.5 -5 -5.5 -6 -7
t
RC
t
RCD
t
RP
t
RRD
t
RAS
t
WR
t
CK1
t
CK2
t
CK3
t
CH
t
CL
t
AC1
t
AC2
t
AC3
t
T
t
CCD
t
OH
t
LZ
t
HZ1
t
HZ2
t
HZ3
t
IS
t
IH
t
SRX
t
PDE
t
RSC
t
BWC
t
DAL2
t
DAL3
t
BPL
t
REF
Row cycle time 55 55 56.5 60 62
RAS to CAS delay 15 15 16.5 18 20 10
Precharge to refresh/row activate
command
Row activate to row activate delay 9 10 11 12 14 10
Row activate to precharge time 40 100K 40 100K 40 100K 42 100K 42 100K
Write recovery time 7 7 7 7 7
Clock cycle time
Clock high time 2 2 2 2 2.5
Clock low time 2 2 2 2 2.5
Access time from CLK
(positive edge)
Transition time of CLK (Rise and Fall) 0.5 10 0.5 10 0.5 10 0.5 10 0.5 10
CAS to CAS Delay time 1 1 1 1 1 CLK
Data output hold time 1.5 2 2 2 2
Data output low impedance 2 2 2 2 2
Data output high impedance(CL = 1) - - - - - - 2 5 3 6 9
Data output high impedance(CL = 2) - - - - - - 2 5 3 6 9
Data output high impedance(CL = 3) 2 4 2 4.5 2 4.5 2 5 3 5 9
Data/Address/Control Input setup time 1.5 1.5 1.5 1.5 2
Data/Address/Control Input hold time 0.8 0.8 1 1 1
Minimum CKE ”High”for Self-Refresh exit 1 1 1 1 1 CLK
Power Down Exit set-up time 4 4 4 5 5 ns
(Special) Mode Register Set Cycle time 2 2 2 2 2 CLK 10
Block Write Cycle time 1 1 1 1 1 CLK
Data-in to ACT (REF) Command (CL = 2) - - - 1clk+
Data-in to ACT (REF) Command (CL = 3) 1clk+
Block Write to Precharge command 1 1 1 1 1 CLK
Refresh time 32 32 32 32 32 ms
CMOS Synchronous Graphic RAM
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
15 15 16.5 18 20 10
CL* = 1 - - - 18 18
CL* = 2 - - - 8 9
CL* = 3 4.5 5 5.5 6 7
CL* = 1 - - - 17 17
CL* = 2 - - - 6 6
CL* = 3 4 4.5 5 5.5 6
1clk+
t
RP
1clk+
t
RP
t
RP
1clk+
t
RP
1clk+
t
RP
t
RP
1clk+
t
RP
unit note
10
ns
ns
ns
Document: Rev.1 Page 23
Preliminary VG4632321A
524,288x32x2-Bit
VIS
Note:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device.
2. All voltages are referenced to VSS.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum
value of tCK and tRC. Input signals are changed one time during tCK. Assume that there is only one read/write cycle
during tRC (min).
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Assume minimum column address update cycle t
6. Power-up sequence is described in Note 11.
7. A.C. Test Conditions
Reference Level of Output Signals 1.4V / 1.4V
CMOS Synchronous Graphic RAM
(min).
CCD
Output Load Reference to the Under Output Load (B)
Input Signal Levels 3.0V / 0.0V
Transition Time (Rise and Fall) of Input Signals 1ns
Reference Level of Input Signals 1.4V
3.3V
1.2K
Ω
ZO=50
Output
30pF
870
Ω
LVTTL D.C. Test Load (A)
8. Transition times are measured between VIH and VIL. Transition (rise and fall) of input signals are fixed slope (1 ns).
9. tHZ defines the time at which the outputs achieve the open circuit condition and are not reference levels.
10. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as
follows:
the number of clock cycles = specified value of timing/Clock cycle time (count fractions as a whole number)
Latency relationship to frequency (Unit : clock cycles)
-4.5 Version (Calculation with t
Clock period
(tCK)
30ns 2 1 1 2 1 1
20ns 3 1 1 2 1 1
15ns 4 1 1 3 1 1
10ns 6 2 1 4 1 2
4.5ns 13 4 2 9 2 4
t
55ns 15ns 9ns 40ns 9ns 15ns
CK
RC
= 4.5ns ~ 30ns)
t
RP
t
RRD
Output
LVTTL A.C. Test Load (B)
t
RAS
Ω
t
RSC
1.4V
50
30pF
t
RCD
Ω
Document: Rev.1 Page 24
VIS
Preliminary VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
-5 Version (Calculation with t
Clock period
(tCK)
t
RC
55ns 15ns 10ns 40ns 10ns 15ns
30ns 2 1 1 2 1 1
20ns 3 1 1 2 1 1
15ns 4 1 1 3 1 1
10ns 6 2 1 4 1 2
5ns 11 3 2 8 2 3
-5.5 Version (Calculation with t
Clock period
(tCK)
t
RC
56.5ns 16.5ns 11ns 40ns 11ns 16.5ns
30ns 2 1 1 2 1 1
20ns 3 1 1 2 1 1
15ns 4 2 1 3 1 2
10ns 6 2 2 4 2 2
5.5ns 11 3 2 8 2 3
-6 Version (Calculation with t
Clock period
(tCK)
t
RC
60ns 18ns 12ns 42ns 12ns 18ns
30ns 2 1 1 2 1 1
20ns 3 1 1 3 1 1
15ns 4 2 1 3 1 2
10ns 6 2 2 5 2 2
6ns 10 3 2 7 2 3
= 5ns ~ 30ns)
CK
= 5.5ns ~ 30ns)
CK
= 6ns ~ 30ns)
CK
t
RP
t
RP
t
RP
t
RRD
t
RRD
t
RRD
t
RAS
t
RAS
t
RAS
t
RSC
t
RSC
t
RSC
t
RCD
t
RCD
t
RCD
-7 Version (Calculation with t
Clock period
(tCK)
= 7ns ~ 30ns)
CK
t
RC
t
RP
t
RRD
t
RAS
t
RSC
t
RCD
62ns 20ns 14ns 42ns 14ns 20ns
30ns 3 1 1 2 1 1
20ns 4 1 1 3 1 1
15ns 5 2 1 3 1 2
10ns 7 2 2 5 2 2
7ns 10 3 2 6 2 3
11. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to VDD and V
(simultaneously) when all input signals are held “NOP”
DDQ
state and CKE = ”H”, DQM = ”H”. The CLK signal must be started at the same time.
2) After power-up, a pause of 200u secouds minimum is required. Then, it is recommended that
DQM is held “high” (VDD levels) to ensure DQ output to be in the high impedance.
3) Both banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 8 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of
the device. Sequence of 4 and 5 may be changed.
Document: Rev.1 Page 25
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