VIORE PDP4210EA Service Manual

PDP4210EA

Model:

SERVICE MANUAL

Safety Precaution

Technical Specifications

Block Diagram

Circuit Diagram

Basic Operations & Circuit Description

Main IC Specifications

Product Specification of PDP Module

Trouble Shooting Manual of PDP Module

Spare Part List

Exploded View

If you forget your V-Chip Password

Software Upgrade

This manual is the latest at the time of printing, and does not
include the modification which may be made after the printing,
by the constant improvement of product.

Safety Precaution

PRECAUTIONS DURING

SERVICING

1. In addition to safety, other parts and

assemblies are specified for conformance with

such regulations as those applying to spurious

radiation. These must also be replaced only

with specified replacements.

Examples: RF converters, tuner units, antenna

selection switches, RF cables, noise-blocking

capacitors, noise-blocking filters, etc.

2. Use specified internal Wiring. Note especially:

1) Wires covered with PVC tubing

2) Double insulated wires

3) High voltage leads

3. Use specified insulating materials for hazardous

live parts. Note especially:

1) Insulating Tape

2) PVC tubing

3) Spacers (insulating barriers)

4) Insulating sheets for transistors

5) Plastic screws for fixing micro switches

4. When replacing AC primary side components

(transformers, power cords, noise blocking

capacitors, etc.), wrap ends of wires securely

about the terminals before soldering.

5. Make sure that wires do not contact heat

generating parts (heat sinks, oxide metal film

resistors, fusible resistors, etc.)

6. Check if replaced wires do not contact sharply

edged or pointed parts.

7. Make sure that foreign objects (screws, solder

droplets, etc.) do not remain inside the set.

The lightning flash with arrowhead symbol,
within an equilateral triangle, is intended to
alert the user to the presence of uninsulated
“dangerous voltage” within the product’s enclo
sure that may be of sufficient magnitude to
constitute a risk of electric shock to persons.

The exclamation point within an equilateral
triangle is intended to alert the user to the
presence of important operating and
maintenance (servicing) instructions in the
literature accompanying the appliance.

CAUTION: TO REDUCE THE RISK OF
ELECTRIC SHOCK, DO NOT REMOVE COVER
(OR BACK). NO USER-SERVICEABLE PARTS
INSIDE. REFER SERVICING TO QUALIFIED
SERVICE PERSONNEL ONLY.

CAUTION

RISK OF ELECTRIC SHOCK

DO NOT OPEN

MAKE YOUR CONTRIBUTION

TO PROTECT THE

ENVIRONMENT

Used batteries with the ISO symbol

for recycling as well as small accumulators

(rechargeable batteries), mini-batteries (cells) and

starter batteries should not be thrown into the

garbage can.

Please leave them at an appropriate depot.

WARNING:

Before servicing this TV receiver, read the

SAFETY INSTRUCTION and PRODUCT

SAFETY NOTICE.

SAFETY INSTRUCTION

The service should not be attempted by anyone

unfamiliar with the necessary instructions on this

apparatus. The following are the necessary

instructions to be observed before servicing.

1. An isolation transformer should be connected in

the power line between the receiver and the

AC line when a service is performed on the

primary of the converter transformer of the set.

2. Comply with all caution and safety related

provided on the back of the cabinet, inside the

cabinet, on the chassis or picture tube.

3. To avoid a shock hazard, always discharge the

picture tube's anode to the chassis ground

before removing the anode cap.

4. Completely discharge the high potential voltage

of the picture tube before handling. The picture

tube is a vacuum and if broken, the glass will

explode.

PRODUCT SAFETY NOTICE

Many electrical and mechanical parts in this

apparatus have special safety-related

characteristics.

These characteristics are offer passed

unnoticed by visual spection and the protection

afforded by them cannot necessarily be obtained

by using replacement components rates for a

higher voltage, wattage, etc.

The replacement parts which have these

special safety characteristics are identified by

marks on the schematic diagram and on the parts

list.

Before replacing any of these components,

read the parts list in this manual carefully. The

use of substitute replacement parts which do not

have the same safety characteristics as specified

in the parts list may create shock, fire, or other

hazards.

9. Must be sure that the ground wire of the AC

inlet is connected with the ground of the

apparatus properly.

5. When replacing a MAIN PCB in the cabinet,

always be certain that all protective are

installed properly such as control knobs,

adjustment covers or shields, barriers, isolation

resistor networks etc.

6. When servicing is required, observe the original

lead dressing. Extra precaution should be given

to assure correct lead dressing in the high

voltage area.

7. Keep wires away from high voltage or high

tempera ture components.

8. Before returning the set to the customer,

always perform an AC leakage current check

on the exposed metallic parts of the cabinet,

such as antennas, terminals, screwheads,metal

overlay, control shafts, etc., to be sure the set

is safe to operate without danger of electrical

shock. Plug the AC line cord directly to the

AC outlet (do not use a line isolation

transformer during this check). Use an AC

voltmeter having 5K ohms volt sensitivity or

more in the following manner.

Connect a 1.5K ohm 10 watt resistor paralleled

by a 0.15µF AC type capacitor, between a

good earth ground (water pipe, conductor etc.,)

and the exposed metallic parts, one at a time.

Measure the AC voltage across the combination

of the 1.5K ohm resistor and 0.15 uF

capacitor. Reverse the AC plug at the AC

outlet and repeat the AC voltage measurements

for each exposed metallic part.

The measured voltage must not exceed 0.3V

RMS.

This corresponds to 0.5mA AC. Any value

exceeding this limit constitutes a potential

shock hazard and must be corrected

immediately.

The resistance measurement should be done

between accessible exposed metal parts and

power cord plug prongs with the power switch

"ON". The resistance should be more than

6M ohms.

Good earth ground
such as the water
pipe, conductor,
etc.

Place this probe
on each exposed
metallic part

AC VOLTMETER

AC Leakage Current Check

Technical Specifications

MODEL : PDP4210EA

42” Plasma Display

DATE FIRST ISSUED

ISSUE

1

RAISED BY

CHECKED BY

NUMBER OF PAGES

10

REVISIONS

ISSUED DATE DESCRIPTION RAISED BY :

SPECIFICATION AGREED : SIGNATURE DATE

R & D DEPARTMENT

COMMERCIAL DEPARTMENT

PRODUCTION DEPARTMENT

Q/A DEPARTMENT

CUSTOMER

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SPECIFICATION APPROVED :

.

SIGNATURE :

DATE :

NOTE :

Only documents stamped “Controlled Document” to be used for manufacture of production parts.

Technical Specifications

PDP4210EA

CONTINUATION PAGE

NUMBER

2 OF 10 PAGES

1. Standard Test Conditions

All tests shall be performed under the following conditions, unless otherwise specified.

1.1 Ambient light : 150ux (When measuring IB, the ambient luminance
≦0.1Cd/m2)

1.2 Viewing distance : 50cm in front of PDP

1.3 Warm up time : 30 minutes

1.4 PDP Panel facing : no restricted

1.5 Measuring Equipment : PC, Chroma 2225 signal generator (with Chroma digital
additional card) or equivalent, Minolta CA100 photometer

1.6 Magnetic field

: no restricted

1.7 Control settings : Brightness, Contrast, Tint, Color set at Center(50)

1.8 Power input : 110~120Vac,60Hz

1.9 Ambient temperature : 20°C ± 5°C (68°F ± 9°F)

1.10 Display mode : 31.5KHz/60Hz (Resolution 852 x 480)

1.11 Other conditions :

1.11.1 With image sticking protection of PDP module, the luminance will descend
by time on a same still screen and rapidly go down in 5 minutes. When

measuring the color tracking and luminance of a same still screen, be sure
to accomplish the measurement in one minute to ensure its accuracy.

1.11.2 Due to the structure of PDP, the extra-high-bright same screen should not

hold over 5 minutes for fear of branding on the panel.

Technical Specifications

PDP4210EA

CONTINUATION PAGE

NUMBER

3 OF 10 PAGES

ELECTRICAL CHARACTERISTICS

2. Power Input

2.1 Voltage : 110 ~120VAC

2.2 Input Current : 3.5A

2.3 Maximum Inrush Current : <30 A (FOR AC110V ONLY)

Test condition : Measured when switched off for at least 20 mins

2.4 Frequency : 60Hz(±3Hz)

2.5 Power Consumption : ≤ 330W

Test condition : full white display with maximum brightness and
contrast

2.6 Power Factor : Meets IEC1000-3-2

2.7 Withstanding voltage : 1.5kVac or 2.2kVdc for 1 sec

3. Display

3.1 Screen Size : 42” Plasma display

3.2 Aspect Ratio : 16:9

3.3 Pixel Resolution : 852x480

3.4 Peak Brightness : 1000 cd/m² (Panel module without filter)

3.5 Contrast Ratio (Dark room) : 3000:1 (Panel module without filter)

3.6 Viewing Angle : Over 160°

3.7 OSD language : English,Spaish,French

4. Signal

4.1 AV & Graphic input

4.1.1 TV standard : NTSC/ATSC

4.1.2 TV Tuning system : 181CH (for NTSC), 2~69CH (for ATSC)

4.1.3 CATV : 125CH (for NTSC)

4.1.4 Composite signal : AV

4.1.5 Y,C Signal : S-Video

4.1.6 Component signal : Y, Pb/Cb, Pr/Cr, HDTV compatible

4.1.7 Graphic I/P : Analog: D-sub 15pin detachable cable
Digital: DVI

4.1.8 PnP compatibility : DDC 1.0

4.1.9 I/P frequency : f

H

: 31.5kHz to 60kHz/fV: 56.25Hz to 75Hz (640x480

recommended)

Technical Specifications

PDP4210EA

CONTINUATION PAGE

NUMBER

4 OF 10 PAGES

4.2 Audio input

Audio I/P(L/Rx5) : 1 for DVI
1 for D-Sub
2 for YPbPr

1 for S-Video /AV

4.3 Audio output

Audio O/P(L/Rx1) : Monitor out(L/R)

SPDIF : Optical x 1

5. Environment

5.1 Operating environment

5.1.1 Temperature : 5º to 33°C

5.1.2 Relative humidity: 20% to 85%(non-condensing)

5.2 Storage and Transport

5.2.1 Temperature : -20°C to 60°C(-4º to 140°F)

5.2.2 Relative humidity: 5% to 95%

6. Panel Characteristics

6.1 Type : LG V6

6.2 Size : 42”, 1005mm(width)x597mm(height)x61mm(depth)±1
mm)

6.3 Aspect ratio : 16:9

6.4 Viewing angle : Over 160°

6.5 Resolution : 852x480

6.6 Weight : 14.8kg ±0.5 kg (Net)

6.7 Color : 16.77 million colors by combination of 8 bits R,G,B digital

6.8 Contrast : Average 60:1 (In a bright room with 150Lux at center)
Typical 3000:1 (In a dark room 1/25 White Window

pattern at center).

6.9 Peak brightness : Typical 1000cd/㎡ (1/25 White Window)

6.10 Color Coordinate Uniformity : Contrast; Brightness and Color control

at normal setting

Test Pattern : Full white pattern

Average of point A,B,C,D and E +/- 0.01

Technical Specifications

PDP4210EA

CONTINUATION PAGE

NUMBER

5 OF 10 PAGES

6.11 Color temperature : Contrast at center (50); Brightness center (50);

Color temperature set at Natural
x=0.285±0.02
y=0.293±0.02

6.12 Cell Defect Specifications
Subject to Panel supplier specification as appends.

7. Front Panel Control Button

7.1 CH Up / Down Button : Push the key to changing the channel up or down.

When selecting the item on OSD menu.
Volume Up/ Down Button : Push the key to increase the volume up or down.
When selecting the adjusting item on OSD menu
increase or decrease the data-bar.

Menu Button : Enter to the OSD menu.

Input Select Button : Push the key to select the input signals source.

7.2 Stand by Button : Switch on main power, or switch off to enter power
Saving modes.

7.3 Main Power Switch : Turn on or off the unit.

8. OSD Function

Full on screen display

Technical Specifications

PDP4210EA

CONTINUATION PAGE

NUMBER

6 OF 10 PAGES

9. Agency Approvals

Safety UL60950

Emissions FCC class B

10. Reliability

11.1 MTBF : 20,000 hours(Use moving picture signal at 25°C ambient)

11. Accessories : User manual x1, Remote control x1, Stand x1, Power cord x1,
Battery x 2.

13. Support the Signal Mode

A. VGA and DVI mode

B. HDTV Mode (YPbPr)

- When the signal received by the Display exceeds the allowed range, a warning message
“Main Not Support!” shall appear on the screen.

- You can confirm the input signal format from the on-screen.

NO. Resolution

Horizontal

Frequency

(KHz)

Vertical

Frequency

(Hz)

Dot Clock

Frequency

(MHz)
1 640 x 400 31.47 70.08 25.17
2 640 x 480 31.50 60.00 25.18
3 640 x 480 37.50 75.00 31.50
4 640 x 480 37.86 72.81 31.50
5 720 x 400 31.47 70.08 28.32
6 800 x 600 35.16 56.25 36.00
7 800 x 600 37.90 60.32 40.00
8 800 x 600 46.90 75.00 49.50
9 800 x 600 48.08 72.19 50.00
10 832 x 624 49.00 75.00 57.27
11

1024 x 768 48.40 60.00 65.00
12 1024 x 768 56.50 70.00 75.00
13 1024 x 768 60.00 75.00 78.75
14 1152 x 864 63.86 70.02 94.51
15 1152 x 864 67.52 75.02 108.03
16 1280 x 720 45.00 60.00 74.25
17 1280 x 960 60.02 60.02 108.04
18 1280 x 1024 64.00 60.01 108.00

NO. Resolution

Horizontal

Frequency

(KHz)

Vertical

Frequency

(Hz)

Dot Clock

Frequency

(MHz)
1 480i 15.734 59.94 13.50
2 480p(720x480) 31.468 59.94 27.00
3 576p(720x576) 31.25 50.00 27.00
4 720p(1280x720) 37.50 50.00 74.25
5 720p(1280x720) 45.00 60.00 74.25
6 1080i(1920x1080) 33.75 60.00 74.25

OF 10 PAGES

Technical Specifications

PDP4210EA

CONTINUATION PAGE

NUMBER

7

Remote Control

󱯎

Standby ( ): Press to turn on and off.

󱯐 Mute ( ): Press to mute the sound.

Press again to restore the sound.

󱯒 0~9 Number Buttons: Press 0~9 to
select a channel, and used to input the
password; the channel changes

after

2 seconds.
󱯔 EPG: Press to display EPG mode.
Press it again to exit EPG mode.
󱯖 Input: Press to select the signal
source, such as TV, AV, S-Video,
Component 1, Component 2, VGA,
DVI or DTV.
󱯘 DTV: Press to choose DTV directly.
󱯚 Dot: Press number buttons with it to
select the channels directly in DTV.
󱯜 VOL +/-: Press to adjust the volume.
󱯞 CH +/- : Press to select the channel
forward or backward.
󱯠 MTS: Press repeatedly to cycle through

the Multi-channel TV sound (MTS)
options: Mono, Stereo and SAP
(Second Audio Program).
󱯡 ◄,►,▲,▼, Enter: Press ◄,►,▲,
▼ to move the on-screen cursor. To

select an item, press Enter to confirm.
And it can also press ▲ or ▼ to
select channels, press ◄ or ► to
adjust the volume.

󱯢 Exit: Press this button to exit.
󱯣

Menu: Press to enter into the on-screen
setup menu, press again to exit.
󱯤 V-Chip: Press to select the child
protect mode.

󱯥 CCD: Press to select the Closed Caption mode.
󱯦 Freeze: Press to freeze the picture, press again to restore the picture.
󱯧 Display: Press to display the channel information and it disappear after 3 seconds.
󱯨 Favorite: Press repeatedly to cycle through the favorite channel list.
󱯩 Add/Erase: Press to add or delete favorite or dislike channels.
󱯪 S.Mode: Press repeatedly to cycle through the sound mode: Normal, News, Cinema,

Flat and User.
󱯫 PIC Size: Press repeatedly to cycle through the picture size that best corresponds your

viewing requirements: Normal, Full, Wide1, Wide2, Wide3, 4:3, No Scale and Panoramic.

(Continued on next page)

󱯎

󱯐

󱯒

󱯔

󱯖

󱯘

󱯚

󱯜

󱯞

󱯠

󱯡

󱯢

󱯣

󱯤

󱯥

󱯦 󱯧
󱯨

󱯩

󱯪

󱯫

󱯬

󱯭

󱯮

󱯯

󱯰
󱯲

󱯱
󱯳

Technical Specifications

PDP4210EA

CONTINUATION PAGE

NUMBER

8 OF 10 PAGES

Note: Press CH +/- on the remote control can turn on TV set from standby mode.

Insertion of Batteries:

-

Turn the remote control upside down, press and slide off the battery cover.

-

Insert two 1.5V (AAA) batteries into the compartment, take care to observe the  and 

markings indicated inside.

-

Replace the cover and slide in reverse until the lock snaps.

󱯬 P.Mode: Press repeatedly to cycle

through the picture mode: Normal,
V

ivid, Hi-Bright, User and Dark.

󱯭 System:

Press repeatedly to cycle
through the system options: AUTO,
and NTSC3.58.
󱯮 Recall: Press to return to previous
channel.
󱯯 Sleep: Press repeatedly until it
displays the time in minutes (5 Min,
10 Min, 15 Min, 30 Min, 60 Min, 90
Min, 120 Min and, OFF) that you
want the TV to remain on before
shutting off. To cancel sleep time,
press SLEEP repeatedly until sleep
OFF appears.
󱯰 Red: Press this button to access the
red item or page.
󱯱 Blue: Press this button to access the
blue item or page.
󱯲 Green: Press this button to access
the green item or page.
󱯳 Yellow: Press this button to access
the yellow item or page.

󱯎

󱯐

󱯒

󱯔

󱯖

󱯘

󱯚

󱯜

󱯞

󱯠

󱯡

󱯢

󱯣

󱯤

󱯥

󱯦 󱯧
󱯨

󱯩

󱯪

󱯫

󱯬

󱯭

󱯮

󱯯

󱯰
󱯲

󱯱
󱯳

Technical Specifications

PDP4210EA

CONTINUATION PAGE

NUMBER

9

OF 10 PAGES

Technical Specifications

PDP4210EA

CONTINUATION PAGE

NUMBER

10 OF 10 PAGES

PHYSICAL CHARACTERISTICS

14. Power Cord

Length : 1.8m nominal

Type : optional

15. Cabinet

15.1 Color : “Black” colour as defined by colour plaque reference number

15.2 Weight

Net weight : 36.2 kg(with stand) /34.0kg(without stand)
Gross weight : 41.0 kg

15.3 Dimensions(with stand)

Width : 1040 mm
Height : 690 mm
Depth : 290 mm

Block Diagram

Product Specification of PDP Module

LVDS Input

Control Signal

(Serial Interface)

APL Data

Memory

Input

Controller

Interface
Controller

Driver
Timing
Controller

Display data, Driver timing

Color Plasma Display Panel

852 X 480 pixels

Scan Driver

Vs(180V~190V)

Va(55V~65V)

Vcc(+5V)

Common sustain driver

Address Driver

☞ Applied Voltage level is specified at the time when Full-W hite pattern is displayed on the panel.

74HC74

(U12)

UPC3218

AGC Amplifier

(U10)

X6965D

SAW F ilter

(U9)

MT5111

DTV Front-end

(U11)

MT5351

DTV Back-end

(U14)

TD1336

Tuner(U8)

256Mb DDR

(U15)

256Mb DDR

(U18)

TS[0...7]

Coaxial

I2C

2nd_IF+ & 2nd_IF-

Differential Data Stream

EEPROM

24C16(U13)

I2C

32Mb

Flash(U17)

Video Data[0...23]

Audio Data

Control

Signals

SPD

Connect with

MT8205

Block Diagram

EEPOROM

24C02(U14)

LP2996

(U12)

IDTQS3VH257

(U25)

IDTQS3

VH257

(U16)

YPbPr

BA7612F

(U23)

EEPROM

24C02(U19)

MT8205

(U7)

CS4334

(U22)

MT8776

(U20)

DDR

128Mb(U11)

Power Connector

(Supplied by PDP)

EEPROM

24C16(U2)

Flash

16M-BIT (U9)

DDR

128Mb(U10)

PDP Connector

SiI161B
(SiI169)

DVI Reciver

(U18)

YpbPr×2

DVI

Video[0...23]

Vedio[0...23]

74LVC244A

U30-U33

Audio

From MT 5351

Control Signals

DVI Audio in

Din

Dout

Bypass Out

Audio L

& Audio R

Audio Bypass

LVDS Data

RGB Output

TV

PDP Control Signals

VGA

I2C (MT8205 I2C)

3.3V

2.5V

1.25V

2.5V

1.25V

5V

5V

5V

3.3V

1.8V

2.5V

3.3V

1.8V

2.5V

1.25V

5V

3.3V

Data[0...31]

Address[0...11]

I2C

MT8205 I2C

I2C

CVBS×2 (CVBS0 is from tuner.)

To PDP

To PDP

MX232A

(U1)

RS232
Signals

TTL Signals

(Used by MT8205)

VGAI2C

DVII2C

AV

V_BYPASS

5V

5V

3.3V

UART0 (Communication with MT5351)

UART2 (MT5351 DownLoad)

From MT3551

YPbPr Audio in

AV Audio in

CD4052

(U17)

AV1 Audio

AV2 Audio

S-Video

Block Diagram

Circuit Diagram

- Power supply board of PDP Module, DGP-420WXGA

- Power supply board of PDP Module, USP490M-42LP

- Main (Video) board

- Audio/Tuner board

- ATSC board

- Keypad board

- Remote control receiver board

- External L/R Speakers board

- Remote control board

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

18 1516

4

151323717

9

11 1221 819

20

D

HIC_MICOM

6

REVISION HISTORY

NO

1

변경
전

변경
후

일자

/

사유

2004/07/28 FEP30JPPH967C6

<D<m

1

R612
12KF

R411 330F

R412 1KF

C403 50V 0.68uF

R504

1.8KF

C225

0.1uF

R132

33KF

PC101

PC-17K1C

R214
360RF

R500
1W 10

D501

SUF30J

C111

0.1uF

R410 330F

R114 3K

TNR101

14D 621K

R416 1K F

0.001uFC204

C101

275VAC 1uF

R700

1W 10

R199
56KF

R414 2KF

D226
LL4148

R210
1W 10F

PC202

CN808

171825-8

1

2

3

4

5

6

7

8

R415 100F

PC-17K1C

PC206

250V 0.47uF

C126

R249
10KF

R176
10KF

R137

10KF

L101

23mH

R408 1K F

1KF

R261

D302
US1M

Q108
KTC3198Y

D503

D10L20U

CN03
3-176976-1

1

2

R143

3W 470K

C116 0.0022uF

45.3KF

R718

R126

75KF

R402 4.7KF

D103

LL4148

C105,106
450V 330uF

L104
CH108200S

D104
US1M

PC102

D5001
SF30SC6

IC300
KA431AZ

R217
10KF

IC501

KIA278R12PI

1 2

3

4

Vin Vo

GND

ON/OFF

R247

1.2K

R229
1W 4.7F

Q202
KRC103M

R301
220F

C410 50V0.01uF

45.3KF

R720

C701,702,704
100V 330uF

J2
0

0R

R508

C516
35V 1000uF

C400
50V 0.1uF

R531

35V 470uF

C117

R518

3.9KF

R115

1.5KF

0.0047uF

C212

Q107
KTC3198Y

R149
100KF

4.7KF

R522

R403 1K F

R609
300KF

R196
56KF

Q702
KTC3207

CN804

171825-9

1

2

3

4

5

6

7

8

9

PC205

R515

1.8KF

R189
200KF

R507

5W 2.7K

C114

0.68uF

R400
1KF

IC502

KIA378R09PI

1 2

3

4

Vin Vo

GND

ON/OFF

KA7552A

IC202

8

1

2

4

3

5

6

7

CS

RT

FB

GND

IS +

OUT

VCC

CT

R155
100KF

R145

2W 240K

KA431AZ

IC500A

2K

VR500

0.047uFC218

C261

4.7uF

C118

0.01uF

R237
5W 0.1

C510

35V 470uF

5K

VR601

CRST400
4MHZ

321

Xout

GND

Xin

C520

4.7KFR250

R307
5W6.8

R216
100KF

1W 100R

R252

CN806

1-1123723-0

1

2

3

4

5

6

7

8

9

10

L500

6*20 2.5uH

Q208
KTA1281

R120
160KF

C119

0.1uF

R512
15KF

PC204

C406 50V 0.1uF

D105
US1M

SW400
JSS 2209

R117
180KF

C404 50V 0.1uF

R104
10W 0.02

C109
68PF

R222

2.2M

R227
1W 4.7

R423 1K F

R248
100KF

R233
100KF

Q106

KSP2907

C600

1KV 220pF

0.22uFC205 D502

31GF6

CN809

171825-2

1

2

0.001uFC210

R502
0

D200

LL4148

120KF

R627

C514
35V 47uF

SDT-SH-118DM

2W 100K

R602

R501

3.3KF

18KF

R701

R404

1KF

C302

0.68uF

4.7uF

C262

L102
23mH

Q701
KTC3207

R123
330KF

10K

R219

45.3KF

R717

R134
24KF

C113

2.2uF

VA EER4042

T206

R221

2.2M

D300

SB560

D500
SF30SC6

R505
1W 4R7

36KF

R709

R124
220KF

R127
75KF

R706
20KF

D211

1N5234B

R128
75KF

120KF

R604

1KF

R262

CN802

171825-4

1

2

3

4

45.3KF

R721

R133
33KF

270KF

R606

R193
56KF

R516
1KF

R113
24KF

C504,C555~C557
10V 2200uF*4

T208

PFC COIL 200uH

R610
300KF

C407 50V 0.1uF

10KFR251

R102
1W 390KJ

R154
100KF

LED400
GREEN

R305
5W15

120KF

R608

4.7KFR235

R532
1W 2.7K

18KF

R714

R705
20KF

FSF10A60

D600

R224

2.2M

CN02
3-176976-1

1

2

R409 2K F

470pF

C208

R417 1KF

PC206

D106
US1M

C200
630V 0.01uF

R405

1KF

C102,103
250V 0.001uF

C601

1KV 220pF

10uF

C263

D111
1N4148

R407 1KF

Q210

KRC103M

35V 47uFC220

KA7552A

IC201

8

1

2

4

3

5

6

7

CS

RT

FB

GND

IS +

OUT

VCC

CT

BYV26EGP

D205

R112 3KF

C112
330pF

C511

35V 47uF

D303
1N5245B

PC100
PC-17K1C

C227

0.001uF

C409 50V 0.1uF

C405 50V 0.1uF

35V 47uF

C507

10V 2200uF*2

C301,301A

RELAY1

R707

2.7KF

R420 4.7KF

LED401

RED

LL4148

D213

18KF

R708

36KF

R703

R704
22KF

R110
10KF

R175
0

45.3KF

R716

D208

BYV26EGP

3.3KF

R509

F101

250VAC 8A

R148
100KF

Q200

KTA1281

R136
10KF

18KF

R615

R144
10F

35V 47uF

C120

R153
100KF

R306
5W6.8

C202 35V 47uF

35V 47uFC215

1uFC203

CN801

171825-7

1

2

3

4

5

6

7

R125
75KF

R406

1KF

C408 50V 0.1uF

SPW20N60C3*3

Q102,Q103,Q109

R603

1W4R7

10KFR236

LL4148

D204

C110
470pF

PC201 PC-17K1C

Q209

SPW11N80C3

120KF

R613

C222
630V 0.1uF

C104
630V 1uF

630V 0.047uF

C206

R519

1.5KF

Q206
KTA1281

1W 47R

R243

D102
FEP30JP

R150
100KF

C550~C554
10V 2200uF*5

R526

2W 100K

R620

IC400

KIA7045AP

321

OUT
GND

VCC

TNR102
14D 621K

PC-17K1C

PC202

R401 1KF

R212
10KF

120KF

R628

C214

0.01uF

R109

1W 4.7

PC100

R513

2.7KF

IC200
KA7552A

8

1

2

4

3

5

6

7

CS

RT

FB

GND

IS +

OUT

VCC

CT

L103

CH108200S

Q105
KTA1281

250V 820uF

C602

C226

0.001uF

D109
1N5236B

R228
1W 4.7

Q203,204
SPW11N80C3*2

1uFC216

R198
56KF

PC-17K1C

PC204

R600

1W4R7

R146

2W 100

C505

1KV 0.001uF

PC101

R514
2KF

U101 UC3854N

1

234

5

6

7

8

91011

121314

15

16

GND

PK

CA

IS

MO

IA

VO

VR

RE

EN

VS

RSSSCT

VC

GT

R142

6.8KF

C221
630V 0.1uF

IC401

HMS87C1304A

6534217891011

12 13

1415161718192021222324

RD0

VDD

AN6/RA6

AN6/RA6

AN5/RA5

AN4/RA4

RD1

AN0/AVref/RB0

BUZ/RB1

INT0/RB2

INT1/RB3

PWM0/COMP0/RB4 RD2

RD3

Xin

Xout

|RESET

Vss

RC0

RC1

RA0/EC0

RA1/AN1

RA2/AN2

RA3/AN3

C411

50V0.01uF

Q300
FQP17N40

STBY EE1927

T100

D212

1N5234B

C201

0.01uF

18KF

R710

R118
180KF

FSF10A60

D700

R135

10KF

FSF10A60

D601

Q104
KTC3209

R418 1KF

R106
1W 4.7

L301

27uH

PC201

D202
BYV26EGP

35V 47uF

C123

11KF

R711

50V 10uFC115

CN01

3-176976-2

1

2

R111
100F

130KF

R607

18KF

R719

R103
5W 20

C700

1KV 100pF

R195
56KF

45.3KF

R715

R230

4.7KF

T204,205
VS EER4042

U100
5M0280R-YDTU

1 2

34

GND DRAIN

VCCFB

R302

1.02KF

2W 240K

R226

0.001uFC211

R190
200KF

5K

VR700

R140

7.5KF

R141

4.7KF

R510
5W 1K

SEL
CABLE

35V 470uF

C128

470F

R520

C401

50V 0.1uF

R121
160KF

R131
33KF

Q207
KRC103M

D107
US1M

R422 10KF

R108
5W 15

R130
240KF

Q201

SPW11N80C3

1uF

C530

56KF

R525

C108
680pF

33KF

R702

1uFC209

PC205

PC-17K1C

R152
100KF

R511
15KF

D206
LL4148

C304
50V 4.7uF

MULTI EER4042

T207

0.01uF

C219

BD101
D25XB60

R119
180KF

R611
300KF

2.4KF

R260

D301
US1M

R156
1KF

C500

1KV0.001uF

50V 220uF

C506

4.7KFR218

R231
5W 0.05

R303
1KF

R122
18KF

R421 10KF

R246
5W 0.2

R223

2.2M

CN803

1-171825-2

1

2

3

4

5

6

7

8

9

10

11

12

C519

C213

630V 0.01uF

R116
10KF

R225
1M

R107
1W 4.7

LL4148

D203

LL4148

D209

C121

630V 0.01uF

R151
100KF

R503

1KF

R232
1K

CN805

1-1123723-4

1

3

4

2

0.001uFC217

CN807

1-1123723-8

1

2

3

4

5

6

7

8

18KF

R712

R129
150KF

PC-17K1C

PC102

R245
10KF

R253

2W 240K

D108 1N5236B

1/4W 100R

R220

IC500
KA317

1 2

3

Adj Output

Input

R192
56KF

R209
2W 240K

VS_ON

+5V DET

9VSC

+12V DET

5VCTRL

60VA

RYC

ACD

5VSC

PFC +

RLY_ON

RLY ON

SB5V

ACD OUT

VI

5VCTRL

190VS 5VCTRL

AC DET

VI

60VA

9VSC

190VS

+5VSTBY

VS DET

24V/30V

+30V DET

+9V DET

VS ON

RY ON/OFF

RYC

12VSC

VA DET

VA VCC

PFC ON/OFF

5VSC

5VD

PFC+

MULTI ON/OFF

60VA

PFC+

VA DET

5VD OUT

GND

MULTI VCC

PFC +

+12V /1.0A

GND

+9V DET

+12V DET

9VSC

PFC +

VA VCC

VS DET

190VS

190VS

GND

VA,VS ON/OFF

PFC VCC

VA ON/OFF

60VA

GND

GND

GND

GND

방전CTL

VA

AC-1

PFC+

PFC VCC

AC DET

PFC GND

+5VSTBY

PFC ON/OFF

방전 CTL

GND

VS

+5V DET

5VCTRL

+30V/1.0A (+24V/1.25A)

5VSC

GND

MULTI ON/OFF

+5VCTRL

+30V DET

DGP-420WXGA

USP490M-42LP

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

SCL
SDA

TxD

INVERTER_PWR

8205UP3_1
PWR_GND

+12V

SCL
SDA

TUNER_12V

TUNER_12V

TXD
RXD

RxD

RSRXD

PCRXD

PCTXD

SYS_PWR

8205UP3_1

PCRXD
PCTXD

RSRXD
RSTXD

RSTXD

INVERTER_PWR

PWR_GND

PWR_GND

GPIO_DVD1

GPIO_DVD1

DV33A URST#

URST#

DV18A

5VSB

5VSB

INVERTER_PWR

VCC

DV33A

+12V

+12V

5VSB

5VSB

5VSB

5VSB

DV33A

5VSB

VCC

+12V

DV18A

SDA 7,10

SCL 7,10

INVERTER_PWR 11

8205UP3_1 3

+12V 7,10,13,14
TUNER_12V 7

TXD 3, 13
RXD 3,13

PWR_GND 11

PCTXD 13

RSTXD 6

RSRXD 6

GPIO_DVD1 3

URST# 3

DV18A 2,3

PCRXD 13

Title

Size Doc Number Re v

Date: Sheet of

INDEX

V1.2

C

115Wednesday, October 12, 2005

12.WM8776 & A/V BYPASS

2. LDO

14.PDP INTERFACE

For Tuner

5. DDR MEMORY & FLASH

6. VGA IN & PC AUDIO IN

RS-232

7. VIDEO IN & TUNER IO

3. MT8205E PBGA388

1. INDEX

4. MT8205 ANALOG DECOUPLING

DIGITAL GND

8. AUDIO/VIDEO IN CIRCUIT

9. DVI INPUT

10.LVDS/CRT/TTL OUT

11.BACK LIGHT / KEYPAD

SYSTEM EEPROM

AUIO IN/OUT GND

MT8205E (PBGA388) LCDTV BOARD 4 LAYERS

13.ATSC INTERFACE

From Power board.

8205UP3_1 HIGH :POWER OFF
8205UP3_1 LOW :POWER ON

ANALOG INPUT GND

ADD BY MTK

Add by MTK

Add by MTK

Power down Reset circuit

ADD BY MTK

Q14

2N3904

1

3 2

R337
10k

R6
10k

U2

EEPROM 24C16

SOP8/SMD

NC

1

NC

2

NC

3

GND4SDA

5

SCL

6

WP

7

VCC

8

R1
10k

R342

0

+

CE3
47uF/16v

C4

0.1uF

C133

20pF

M2

1

R335
0/NC

R3
10K

R2

4.7k

R341 10

R73 10 /NC

C3 0. 1uF

C132
20pF

M3

1

H4

HOLE/GND

2

2

3

3

4

4

5

5

9

9

8

8

7

7

6

6

1

1

J1

5x1 W/HOUSING

PH5/2.0

1

2

3

4

5

J21

CON10

1
2
3
4
5
6
7
8
9

10

J2

DIP11/P2.54

1
2
3
4
5
6
7
8
9
10
11

C5 0. 1uF

J3

8x1 W/HOUSING

DIP8/W/H/P2.54

1
2
3
4
5
6
7
8

C1 0.1uF

+

CE88

47uF/16v

R4
10K

H1

HOLE/GND

2

2

3

3

4

4

5

5

9

9

8

8

7

7

6

6

1

1

V1

1

L50

FB

BEAD/SMD/1206

L1

FB

BEAD/SMD/0805

D28

1N4148

H3

HOLE/GND

2

2

3

3

4

4

5

5

9

9

8

8

7

7

6

6

1

1

H2

HOLE/GND

2

2

3

3

4

4

5

5

9

9

8

8

7

7

6

6

1

1

V2

1

CB1

0.1uF

CB136

0.1uF

C2 0. 1uF

V3

1

R112
R

R0603/SMD

R5
10k

+

CE2
220uF/16v

C220UF16V/D6H11

M1

1

L44

FB

BEAD/SMD/1206

Q1

2N3904

SOT23/SMD

1

3 2

V4

1

U1

MAX232A

R1IN

13

R2IN

8

T1IN

11

T2IN

10

C+

1

C1-

3

C2+

4

C2-

5

V+

2

V-

6

R1OUT

12

R2OUT

9

T1OUT

14

T2OUT

7

VCC

16

GND

15

R336

0

J4

4x1 W/HOUSING

DIP4/W/H/P2.0

1
2
3
4

+

CE1
220uF/16v

C220UF16V/D6H11

CB2

0.1uF

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

AV33

DV33

DV33A

DV18A

DV18A

AV33

DV33VCC 5VSB

DV33A

DV18A

DV18A 1,3

Title

Size Doc Number Re v

Date: Sheet of

LDO

V1.2

C

215Wednesday, October 12, 2005

Vout

Power ON alive source

CB5

0.1uF

+

CE8
220uF/16v

U3

CM1117-3.3V

SOT223/SMD

ADJ/GND

1

OUT2IN

3

U5

CM1117-3.3V

SOT223/SMD

ADJ/GND

1

OUT2IN

3

+

CE10
220uF/16v

CB7

0.1uF

CB9

0.1uF

+

CE4

220uF/16v

CB3

0.1uF

TP2

R96

0/NC

R0805/SMD

C6
10uF/10v

L5

FB

BEAD/SMD/0805

+

CE6
220uF/16v

+

CE7
220uF/16v

L4

FB

BEAD/SMD/0805

R99

0/NC

R0805/SMD

+

CE5
220uF/16v

U6

CM1117-1.8V

SOT223/SMD

ADJ/GND

1

OUT2IN

3

CB8

0.1uF

TP1
TEST POINT DIP1.0

CB4

0.1uF

+

CE9
100uF/16v

L2

FB

BEAD/SMD/0805

L3

FB

BEAD/SMD/0805

CB6

0.1uF

U4

CM1117-3.3V

SOT223/SMD

ADJ/GND

1

OUT2IN

3

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

A_CLK

A_DQM[0..1]

A_BA[0..1]

A_WE#

A_CKE

A_CLK#

A_DQ[0..31]

A_RA[0..11]

A_CAS#

A_DQS[0..3]

SDV25

A_CS#
A_RAS#

F_A[0..20]

F_OE#

F_D[0..7]

8205UP3_0

VSYNC
HSYNC

GREEN­BLUE+
BLUE-

RED+

VGASOG

RED-

VGAVSYNC#

Y-

SY+

CB-

SC-

CVBS0-

Y+

CB+

SC+

CR-

SY-

CR+

CVBS0+

AP[0..7]
AN[0..6]

CLK1-

CLK1+

SCL_8205
SDA_8205

CVBS1-

CVBS1+

MPX1
MPX2

PWM0

DACVREF

DACFS

LVDDA

DACVDD

VREFN4

VREFP4

AVCM
VOCM
VICM

ADCVDD0

REXTA
APLL_CAP

XTALI
XTALO

ADCPLLVDD1
ADCPLLVDD

VPLLVDD

APLLVDD

PWM2VREF

AUXTOP
AUXBOTTOM

ADCVDD

GND

OBO7

GND

OBO4

OBO5

OBO6

MPX2

ADCVDD4
MPX1

DACVREF

VREFN4

GND
VREFP4

GND

AUXTOP

GND

PWM2VREF

ADCVDD

VPLLVDD

AUXBOTTOM

VPLLVDD
GND

REXTA

LVDDA

VPLLVDD

GND

AP7

AP6

GND

AN6
AP5

AP4
AN4

AN5
LVDDA

AP2

GND
CLK1+

AN3

AP3

CLK1-

HSYNC

LVDDA

AN2

DACVDD

AP0

R

AN0

DV33A

AP1

VSYNC

DACVDD

GND

G

B

GND

GND

DACVDD

AN1

GND

DACFS

DV33A

F_A16

F_A17

F_A6

GND

F_A19

F_A20

F_A18

GND

ORO6

F_A15

F_A14

OGO1

GND

OBO2

OGO2

F_D5

OBO0

F_A8

OGO6

OGO5

ORO7

DV18A

F_A10

F_D3

OBO3

OBO1

F_D1

F_A12

F_D6

F_A13

GND

F_A9

OGO0

F_D7

F_D4

F_A3

F_A5

F_D0

F_D2

DV33A

OGO3

F_A4

F_A1

F_A2

F_A0

F_A11

8205UP1_3

8205UP1_2

PCE#

F_OE#

WE#

F_A21

RxDIRPWM0

GND

HWSCL

TxD

HWSDA

GPIO

A_DQ0

8205UP3_0

URST#

GND

8205UP3_1

UP3_4

UP3_5

DV33A

A_CS#

A_DQ8

A_RA0

A_CKE

A_BA0

A_DQ11

DV18A

SDV25

GND

GND

A_DQ10

GND

A_RA10

A_RA3

A_DQ17

A_RA5

A_DQM1

SDV25

A_DQ13

A_DQ25

A_DQ5

GND

A_RA6

SDV25

GND

A_DQ29

SDV25

A_DQ12

A_RA2

A_DQ15

A_DQ9

GND

DV18A

A_RA1

GND

A_DQ18

A_DQS3

A_DQ7

A_RAS#

A_RA7

A_DQS1

GND

A_DQ19

GND

A_DQ1

SDV25

A_DQ28

A_DQ22

GND

A_DQ24

A_CLK

GND

A_DQ3

A_DQ2

SDV25

A_RA8

A_DQM0

A_DQ21

A_DQ6

GND

A_DQ20

A_WE#

A_BA1

A_DQ23

A_DQ27

VREF

A_DQ30

A_DQ4

A_DQ14

A_RA11

A_DQ26

A_CLK#

SDV25

A_DQ31

A_DQS2

DV18A

A_RA9

SDV25

GND

A_CAS#

A_DQ16
A_RA4

DACMCLK

DACLRC

DACBCLK

DOUT

DV18A

DV33A

DVIODCK

GND

GND

HSYNC_VGA

BLUE+

GND

BLUE-

DV18A

ADCPLLVDD

GND

VGAVSYNC#

VI13

VI12

VI23

VI14

VI15

DV18A

VI1

VI8

GND

VI6

VI4

VI11

VI5

VI3

VI7

VI0

VI9

VI2

VI10

VGASOG

ADCVDD0

GREEN-

RED+

GREEN+

RED-

XTALI

APLL_CAP

GND

XTALO

ANALOGVDD

APLLVDD

ANALOGVDD

ANALOGVDD

GND

VI17

VI20

VI22

VI18

VI19

VI16

VI21

GND

ADCPLLVDD1

GND

ADCVDD4

GND

GND

ADCVDD0

AVCM

CVBS2+

CVBS1+

CVBS1-

CVBS2-

CVBS0+

GND

CVBS0-

ADCVDD0

SC-

SC+

SY-

GND

SY+

VOCM

CB+

GND

CB-

Y+

VICMY-ADCVDD0

SOY

CR-

CR+

ANALOGVDD

GND

DACBCLK

ADCVDD0

DV18A

DV18A

OBO[0..7]

GREEN+

HSYNC_VGA

DVIHSYNC
DVIVSYNC

DVIDE

DVIODCK

DVIDE
DVIVSYNC
DVIHSYNC

OGO7

F_A7

A_DQS0

VREF

8205UP1_4

PWM1

CVBS2-

CVBS2+

VI[0..23]

SOY

MUTE

MUTE

ORO5

ORO4

ORO2

ORO2

ORO4

OGO[0..6]

ADCVDD4

ORO7

DV18A

ORO3

AOSDATA3

SW

ORO1

WE#
PCE#

TXD
RXD

DOUT

DACMCLK
DACLRC

DACBCLK

READY#

REQUEST#

SCL_8205

UP3_5

SDA_8205

HWSCL

UP3_4

HWSDA

AOSDATA1

AOSDATA1
AOSDATA3

ORO1
ORO3
ORO5
8205UP1_4

SW

8205UP1_3

IR

8205UP3_1

GPIO
ORO6

GPIO_DVD0

GPIO_DVD1

OGO4

ICE

DVISCL

DVISDA

REQUEST#

READY#

DV33A

DV33A

R
G
B

8205UP1_2

OGO7
PWM1
OGO4

DVISDA

DVISCL

GPIO_DVD1

DV18A

GPIO_DVD2

GPIO_DVD0

GPIO_DVD2

F_A21

ADIN4

ADIN4
URST#

ADIN3

ADIN0

ADIN3
ADIN2
ADIN1
ADIN0

ADIN2
ADIN1

DV18A

URST#

GND

RSTVCC URST#

DV33A DV18A

DV33A

DV33A

DV33A

5VSB

A_CKE 5

A_CAS# 5

A_DQS[0..3] 5

A_CLK 5

A_WE# 5

A_BA[0..1] 5

A_RA[0..11] 5

A_CS# 5

A_DQ[0..31] 5

SDV25 5

A_RAS# 5

A_DQM[0..1] 5

A_CLK# 5

F_D[0..7] 5
F_OE# 5

F_A[0..20] 5

OBO[0..7] 11

VSYNC 10
HSYNC 10

RED- 8

BLUE+ 8
BLUE- 8

RED+ 8

VGASOG 8

GREEN- 8

VGAVSYNC# 6

SC+ 8

CR+ 8

SC- 8

SY+ 8

CR- 8

Y- 8

SY- 8

CVBS0+ 8

CB+ 8

CVBS0- 8

CB- 8

Y+ 8

AP[0..7] 10
AN[0..6] 10

CLK1+ 10
CLK1- 10

SDA_8205 10

SCL_8205 10

CVBS1+ 8
CVBS1- 8

PWM0 11

DACVREF 4

DACFS 4

LVDDA 4

DACVDD 4

VREFP4 4
VREFN4 4

VOCM 4

AVCM 4

VICM 4

ADCVDD0 4

REXTA 4
APLL_CAP 4

XTALO 4

XTALI 4

ADCPLLVDD 4

ADCPLLVDD1 4

APLLVDD 4
VPLLVDD 4

PWM2VREF 4

AUXTOP 4
AUXBOTTOM 4

ADCVDD 4

MPX2 8

MPX1 8

ANALOGVDD 4

GREEN+ 8

HSYNC_VGA 6

DVIHSYNC 9,13
DVIVSYNC 9,13

DVIODCK 9,13
DVIDE 9,13

VREF 5

VI[0..23] 9,13

SOY 7

MUTE 12

ORO2 7

ORO4 12

OGO[0..6] 7,9,13

ADCVDD4 4

ORO7 12

SW 13

WE# 13
PCE# 5

RXD 1,13

TXD 1 ,13

DOUT 12

DACMCLK 12

AOSDATA3 12

DACBCLK 12

DACLRC 12

AOSDATA1 12

READY# 13

REQUEST# 13

ORO1 10,14
ORO3 10,14
ORO5 10
8205UP1_4 10

8205UP1_3 13

IR 7,11

CVBS2- 8

CVBS2+ 8

8205UP3_1 1

GPIO 7,10
ORO6 10

GPIO_DVD1 1

8205UP3_0 11

R10
G10
B10

8205UP1_2 9,11

OGO4 9 ,13

PWM1 12

DVISDA 9

DVISCL 9

OGO7 12

GPIO_DVD2 7

GPIO_DVD0 7

F_A21 9
ADIN4 14
URST# 1
DV18A 1,2

Title

Size Doc Nu mber Rev

Date: Sheet of

MT5205BGA388

V1.2

C

315Wednesday, October 12, 2005

UP3_5 FOR S/W SDA

UP3_4 FOR S/W SCL

PDP power cotrol GPIO.

PDP signal cotrol GPIO.

DVD GPIO PORTS

Internal Reset Circuit

External Reset Circuit

Change by MTK

R9
1k

CB135

0.1uF

R368 10K

R16 R/NC

R270
100K

R104

0

R17 0

R7
10K/NC

R106

0

R367 10K

+

CE81

22uF/25v

R18 0

+

CE11

10uF/25v/NC

R366 10K

U27

LM809

SOT23/SMD

GND

1

OUT2IN

3

R365 10K

R8
47k

MT8205

U7

MT8205

BGA388/SOCKET

A2P

P2

DVSS3

R11

ERO1

AD1

HIGHA6

AE9

HIGHA5

AF9

HIGHA4

AE10

HIGHA3

AF10

SCL0

AF26

DVDD18

AD18

EBO7

V2

EBO6

V3

EBO5

W1

EBO4

W2

DVDD3I

AC9

EBO3

W3

EBO2

W4

CLK1P

N2

A4N

L1

CLK2P

H2

VREF

M4

LVDDC

M3

R

V4

HSYNCO

U2

G

U4

RWE#

U24

DQ10

V26

DQ9

V25

DQ8

W26

RAS#

T24

CAS#

T23

DVSS2

R15

DVDD2I

U23

DQ11

U25

DQ13

T25

ORO3

AE7

SDA0

AE26

ORO6

AF6

ORO2

AF7

ORO1

AC8

ORO0

AD8

HIGHA7

AF8

HIGHA1

AD11

HIGHA0

AF12

AD0

AE15

AD1

AD15

DVDD18

AC19

AD2

AC15

AD3

AF16

AD4

AE16

DVSS3

R12

AD7

AF17

AD5

AD16

IOA0

AD17

IOA3

AF14

IOA4

AF13

IOA5

AE13

IOA6

AD13

IOA7

AC13

DVDD3I

AC10

A16

AE8

A17

AC17

IOA20

AE11

DVSS18

T12

IOA21

AF11

IOALE

AE17

EBO1

Y1

OBO1

AE3

DVSS18

T11

OBO0

AF3

ERO5

AC1

OGO1

AC6

DVDD3

AD9

ORO7

AE6

OGO0

AD6

OBO6

AD4

ERO6

AB4

OBO5

AE1

OGO4

AD5

ERO7

AB3

EGO1

AB1

EGO5

AA1

ERO4

AC2

OBO4

AE2

OGO3

AE5

OGO2

AF5

EGO0

AB2

EGO2

AA4

DVDD18

AC18

EGO4

AA2

DVSS18

P11

EGO7

Y3

VCLK

V1

OGO5

AC5

EGO3

AA3

IOCS#

AC14

AUXVTOP

F3

VPLLVDD

G4

ADIN2

E2

ADCVSS

F2

RA2

N23

AUXVBOTTOM

G3

TESTP

B14

ADIN1

E3

ADIN0

E4

AF

C2

A3P

M2

DVSS2

R16

RA5

J24

RA6

K23

DVDD18

AA23

DVDD2

H23

DVSS18

R14

RA8

L23

RA9

L24

RA11

M23

RCLK

P26

ORO4

AD7

DACVSSB

R3

SVM

T4

DACVSSC

N11

BGVDD

H4

BGVSS

K4

DLLVSS

K3

REXTA

J4

A4P

L2

A5N

K1

LVSSA

M12

A2N

P1

DACVDDB

P3

LVDDB

L4

REFP4

D1

REFN4

D2

ADCVDD

F1

DLLVDD

H3

RCLKB

P25

DVSS2

P15

RA3

M24

RA0

R26

RA1

N24

B

U3

DACVSSA

R4

DACVDDA

P4

ADCVDD4

D3

DQ18

M25

DQ17

M26

RA4

J23

RA10

P24

DQ16

N25

BA0

R24

DVDD18

AD19

UP30

AE21

PRST#

AC21

UP34

AD22

UP35

AC22

WR#

AF18

DQ3

AC26

DVDD2

W24

DQ2

AC25

RXD

AE24

IR

AF24

PWM1

AC23

PWM0

AD23

TESTN

A14

FCICMD

AE22

FCICLK

AF22

DQ7

AA26

DVSS18

T16

DQ6

AA25

DVSS2

T14

DQ4

AB25

SDA1

AB24

SCL1

AB23

SCL

AF25

UP12

AE19

INT0#

AF19

DVDD3

AD10

AVDD18

Y23

RVREF

G23

RD#

AE18

DQ14

T26

AVSS18

W23

DQS1

W25

DQ15

R25

UP17

AF21

DVDD2

V24

DVDD2

H24

SIF

C1

ADCVSS4

L11

ADIN4

D4

ADIN3

E1

PWM2VREF

F4

VPLLVSS

J3

A0N

T1

A0P

T2

LVDDA

L3

A1N

R1

CLK1N

N1

A3N

M1

A1P

R2

A5P

K2

A6N

J1

A6P

J2

UP15

AD20

OGO7

AE4

EGO6

Y4

LVSSB

M11

FS

N4

DACVDDC

N3

A7P

G2

CLK2N

H1

ERO0

AD2

OBO2

AF2

EBO0

Y2

OGO6

AF4

RCS#

R23

BA1

P23

RA7

K24

CKE

N26

DVSS18

T13

DVSS2

T15

DQ12

U26

SDA

AE25

FCIDAT

AF23

UP31

AD21

UP13

AF20

IOA18

AE12

IOOE#

AF15

AD6

AC16

IOA1

AD14

ORO5

AC7

DE

T3

ERO3

AC3

DVDD2

V23

UP14

AE20

A7N

G1

LVSSC

N12

TXD

AD24

ICE

AC24

DQ0

AD25

DQS0

Y25

DQ5

AB26

DVSS18

P12

VSYNCO

U1

ERO2

AC4

OBO7

AD3

OBO3

AF1

HIGHA2

AC11

DVSS18

P13

UP16

AC20

GPIO0

AE23

IOWR#

AC12

IOA2

AE14

DVSS3

R13

DQM0

Y26

IOA19

AD12

DQ1

AD26

DQ19

L26

DVDD18

AA24

DQ20

L25

DQ21

K26

DVSS2

P16

DQ22

K25

DQ23

J26

DQS2

J25

DQM1

H26

DVDD2

G24

DQS3

H25

DQ31

D25

DQ30

D26

DVSS2

N16

DQ29

E25

DVSS18

P14

DQ28

E26

DQ27

F25

DVDD2

F24

DQ26

F26

DQ25

G25

DQ24

G26

DVSS3

N15

AOMCLK

E24

AOLRCK

C25

AOBCK

C26

LIN

B24

AOSDATA3

B25

DVDD3I

F23

AOSDATA2

B26

AOSDATA1

A26

AOSDATA0

A25

DVDD18

Y24

HSYNC_DVI

A24

VSYNC_DVI

D24

DE_DVI

C24

VCLK_DVI

B23

VI23

A23

VI22

D23

VI21

C23

VI20

B22

VI19

A22

VI18

D22

VI17

C22

VI16

B21

DVSS18

M16

VI15

A21

VI14

D21

VI13

C21

VI12

B20

DVSS3

L16

VI11

A20

VI10

D20

VI9

C20

VI8

B19

VI7

A19

DVDD18

E23

VI6

D19

VI5

C19

VI4

B18

VI3

A18

VI2

B17

VI1

A17

VI0

B16

DMPLLVSS

C18

DMPLLVDD

C17

APLLVDD

D17

APLLVSS

D18

APLL_CAP

A16

XTALVSS

M15

XTALI

A15

XTALO

B15

XTALVDD

C16

SYSPLLVDD

D16

SYSPLLVSS

L15

ADCPLLVSS

M14

ADCPLLVDD

C15

ADCPLLVDD1

D15

ADCPLLVSS1

L14

DVDD

D14

DVSS

N14

HSYNC

C14

VSYNC

C13

REFN3

C12

REFP3

D12

ADCVSS3

C10

BP

A13

BN

B13

SOG

D13

GP

A12

GN

B12

RP

A11

RN

B11

ADCVDD3

D8

MON1

C11

MON0

D11

REFN2

C9

REFP2

D9

ADCVSS2

D10

CRP

A8

CRN

B8

CBP

A9

CBN

B9

SOY

C8

YP

A10

YN

B10

ADCVDD2

C7

VICM

A7

VFEVSS0

N13

VOCM

B7

VFEVDD0

D7

REFN1

C6

REFP1

D6

ADCVSS1

M13

SYP

A6

SYNB6SCP

A5

SCN

B5

ADCVDD1

C5

REFN0

A4

REFP0

B4

ADCVSS0

L13

CVBS0P

A3

CVBS0N

B3

CVBS1P

A2

CVBS1N

B2

CVBS2P

A1

CVBS2N

B1

ADCVDD0

C4

AVCM

D5

VFEVSS1

L12

VFEVDD1

C3

D1

1N4148/SMD

R15 R/NC

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

ADC_VDD

DACVDD

DACVDD

DACVDD

GND

VICM

VOCM

ADCVDD

DACVREF

VPLLVDD

VPLLVDD

AUXTOP

AUXBOTTOM

ANALOGVDD

ADCPLLVDD

ANALOGVDD

XTALO

ADCPLLVDD1DV18A

ADCPLLVDD1
ADCPLLVDD
APLLVDD

APLL_CAP
XTALI
XTALO

APLLVDD

VPLLVDD

REXTA

AUXTOP
AUXBOTTOM

LVDDA

PWM2VREF

ADCVDD

ADCVDD0

DACVDD
AVCM
VOCM
VICM

VREFN4

VREFP4

DACVREF
DACFS

VPLLVDD

ANALOGVDD

AVCM

GND

GND

VREFN4

GND

VREFP4

LVDDA

APLL_CAP

ANALOGVDD

GND

ADCVDD4

ADCVDD0

ADCVDD0

ADCVDD0

GND

GND

ADCVDD4

XTALI

ADCVDD0

PWM2VREF

GND

GND

GND

AV33

GND

LVDDA

GND

LVDDA

GND

GND

LVDDA

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

REXTA

DACFS GND

DV18A

AV33

VCC

ADC_VDD

DV33A

DV18A

AV33

DV33A

DV18A

ADC_VDD

AV33

ADCPLLVDD1 3
ADCPLLVDD 3
APLLVDD 3

APLL_CAP 3
XTALI 3
XTALO 3

VPLLVDD 3

REXTA 3

AUXTOP 3
AUXBOTTOM 3

LVDDA 3

PWM2VREF 3

ADCVDD 3

ADCVDD0 3

DACVDD 3
AVCM 3
VOCM 3
VICM 3

VREFN4 3

VREFP4 3

DACVREF 3
DACFS 3

ANALOGVDD 3

ADCVDD4 3

DV18A 1,2,3

Title

Size Doc Nu mber Rev

Date: Sheet of

MT8205 DECOUPOMG--ANALOG

V1.2

C

415Wednesday, October 12, 2005

FOR DACVDD

Vout

FOR ADCVDD

MT8205 ANALOG DECOUPLING&DIGITAL DECOUPLING

0603 PUT ON NEARLY BGA

0603 PUT ON NEARLY BGA

DIGITAL DECOUPLING

C26

4.7uF

C0603/SMD

C23
3300pF

L15 FB

CB21 0.1uF

C0603/SMD

CB40

0.1uF

C0603/SMD

L14

FB

R26 50/47R

L8

FB

BEAD/SMD/0805

R101 0/NC

R0805/SMD

L12

FB

BEAD/SMD/0603

CB33

0.1uF

+

CE21
47uF/16v

CB29

0.1uF

C0603/SMD

R19

100k

C32 1500pF

L7

FB

BEAD/SMD/0603

CB31

0.1uF

C18

4.7uF

C0603/SMD

C28
3300pF

C0603/SMD

L9

FB

BEAD/SMD/0603

C25

4.7uF

C0603/SMD

R23
0

C12
33pF

+

CE15
47uF/16v

C33 0.1uF/NC

Y1 27MHz

CB41

0.1uF

C10

0.1uF

CB23 0.1uF

C0603/SMD

U8

CM1117-3.3V

SOT223/SMD

ADJ/GND

1

OUT2IN

3

C22

0.01uF

CB16

0.1uF

+

CE18
10uF/25v

CB46

0.1uF

TP6

C29
3300pF

C0603/SMD

CB20

0.1uF

C0603/SMD

+

CE14
22uF/25v

CB45

4.7uF

C17

4.7uF

C0603/SMD

+

CE19

47uF/16v

CB47

0.1uF

L11

FB

BEAD/SMD/0603

CB27

0.1uF

C0603/SMD

CB48

4.7uF

C0603/SMD

CB17

0.1uF

+

CE22
47uF/16v

CB12

0.1uF

C0603/SMD

CB14

0.1uF

C0603/SMD

CB10

0.1uF

C0603/SMD

+

CE16
100uF/16v

C30
3300pF

C0603/SMD

+

CE12

10uF/25v

C16

0.1uF

CB15

0.1uF

C0603/SMD

C27

4.7uF

C0603/SMD

CB13

0.1uF

C0603/SMD

CB36

0.1uF

C0603/SMD

C15

4.7uF

C0603/SMD

L10

FB

BEAD/SMD/0805

C13

4.7uF

C0603/SMD

CB32

0.1uF

C0603/SMD

TP5

C8

4.7uF

C0603/SMD

C7

4.7uF

C0603/SMD

C24

4.7uF

C0603/SMD

C9

4.7uF

C0603/SMD

CB44 4.7uF

C0603/SMD

C21

4.7uF

C0603/SMD

C14

4.7uF

C0603/SMD

CB37

0.1uF

C0603/SMD

CB42

0.1uF

C0603/SMD

CB22

0.1uF

C0603/SMD

CB25

0.1uF

C31
3300pF

C0603/SMD

CB11

0.1uF

R24 3.3k
C11
33pF

R21
0

R25 50/47R

CB34

0.1uF

C0603/SMD

CB49 4.7uF

C0603/SMD

L6

FB

BEAD/SMD/0603

CB38

0.1uF

C0603/SMD

CB19 0.1uF

C0603/SMD

CB26

0.1uF

CB24

0.1uF

C0603/SMD

CB28

0.1uF

+

CE17
220uF/16v

+

CE20
22uF/25v

L13

FB

BEAD/SMD/0603

R20

0

R22

0

CB35

0.1uF

C20

0.1uF

CB43

0.1uF

CB39

0.1uF

C0603/SMD

CB18

0.1uF

C19

4.7uF

C0603/SMD

R27 560

CB30

0.1uF

+

CE13

10uF/25v

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

A_RA[0..11]
A_BA[0..1]

A_CLK

A_CKE

A_RAS#

A_CS#

A_WE#

A_CAS#

A_DQM[0..1]
A_DQ[0..31]

F_D[0..7]

F_OE#

A_DQS[0..3]

A_CLK#

SDV25
VREF

F_D3

F_A14

F_A20

F_A17

F_A2
F_A3

F_A9

F_A11

F_A7

F_A12

PWR#

F_D4

F_A8

F_A0

F_A5

F_D6

F_D1

F_A13

F_A4

F_A10

F_A18

F_A1

F_D2

F_D5

F_A16

F_A15

F_A19

PCE#
F_OE#

F_D0

F_D7

F_A[0..20]

FLASHVCC

SDV25

D1V25

D1V25

D1V25

D1V25

SDV25

SDV25

SDV25

SDV25

VREF

A_DQ19

A_CLK

A_DQ17

D_CLK

D_DQ14

D_CAS#

D_RA6

D_DQ23

A_DQ8

D_DQ20

D_RA4

D_DQS1

D_DQM1

A_DQ25

A_RA5

D_DQ17

A_DQ1

D_RA8

D_DQ29

D_DQ24

D_DQS2

D_RA3

D_DQ3

D_DQM1

D_DQ8

D_RA7

D_CKE

D_DQ13

D_DQ1

A_RA2

D_RA9

A_DQM0

A_DQ4

D_DQ8

A_DQ16

D_DQ6

D_RA5

A_DQ14

D_WE#

A_DQS1

D_DQ15

A_DQ26

A_RA4

D_CKE

D_CLK

A_DQS2

D_DQS3

D_DQ30

D_BA1

A_DQ13

A_CKE

D_RA6

A_DQ3

D_DQ6

A_RA3

D_RA2

D_RA3

D_DQS1

D_DQ15

D_DQ4

D_RA7

A_BA1

D_DQ5

A_DQ21

D_CLK#

D_CS#

D_DQ14

D_DQM1

D_DQ0

D_BA0

D_DQ22

A_DQS0

A_RA8

D_DQ22

A_DQ24

A_RA6

D_RA5

A_DQ0

D_DQ5

A_DQ29

A_DQ15

A_RAS#

D_DQ11

A_DQ10

D_CS#

D_CLK#

D_DQS2

D_DQ24

D_DQ7

D_DQ13

D_RA1

D_DQ20

A_RA0

A_WE#

D_BA1

D_DQ23

A_RA9

A_BA0

A_DQ22

D_RA4

D_CAS#

A_DQM1

D_RA3

D_DQ4

A_CLK#

A_DQ27

D_CAS#

D_DQ19

D_DQS3

D_RAS#

A_DQ6

D_RA11

D_DQ25

VREF

D_DQ28

D_RA2

D_RA8

A_DQ12

D_BA0

D_DQ25

D_CS#

A_DQ9

D_DQ18

D_DQ12

D_DQ26

D_RA0

A_CAS#

D_DQ26

VREF

A_RA11

D_RA4

D_WE#

D_DQ17

D_DQ12

D_RA11
D_RA9

A_DQ20

D_RA2

D_WE#

D_CLK

D_DQ31

D_DQ18

D_DQ11

A_RA1

D_RA10

A_DQ30

D_DQ2

D_DQ31

A_RA10

D_DQ16

D_RA10

D_DQ27

A_DQ5

D_RA1

D_BA0

D_DQ28

D_DQ27

A_DQ18

D_CKE

D_RAS#

D_RA7

D_BA1

D_DQ2

A_DQ11

D_RA10

D_DQ10

D_DQM0

D_DQ29

D_DQ19

D_RAS#

D_RA6

A_RA7

A_CS#

D_RA9

A_DQ31

A_DQ2

D_DQ21

A_DQS3

D_RA8

D_DQ16

D_RA1

D_CLK#

D_DQ10

D1V25

A_DQ23

D_DQM0

D_DQS0

D_RA0

D_DQ1

D_DQ9

D_RA5

D_DQS0

D_DQ30

D_DQ21

A_DQ28

A_DQ7

D_DQ9

D_DQ3

D_RA11

D_RA0

D_DQ7

VREF

D_RA2

D_DQ6

D_DQ12

D_DQS3

D_DQM1

D_DQ11

D_BA1

D_DQS1

D_CAS#

D_RA1

D_DQ3

D_DQ24

D_DQ23

D_DQ28

D_DQS2

D_DQM0

D_DQ20

D_RA7

D_DQ30

D_DQ5

D_DQ16

D_RA0

D_RA5

D_RA4

D_WE#

D_RAS#

D_RA6

D_DQ19

D_DQ22

D_RA11

D_DQ1

D_DQ13

D_DQS0

D_DQ18

D_DQ26

D_DQ14

D_DQ21

D_RA8

D_DQ15

D_DQ17

D_DQ31

D_RA3

D_CS#

D_DQ7

D_DQ4

D_RA10

D_DQ2

D_DQ8

D_DQ27

D_DQ29

D_DQ25

D_DQ10

D_BA0

D_DQ9

D_DQ0

D_RA9

PCE#

RWR#

F_A6

D_DQ0

D_DQM0

VREF

DV33A

DV33A

DV33A

SDV25

DV33A

D1V25

VCC

SDV25

VREF

SDV25

VREF

SDV25

SDV25 SDV25

D1V25

SDV25 SDV25

D1V25

A_RA[0..11] 3
A_BA[0..1] 3

A_CLK 3

A_CKE 3

A_RAS# 3

A_CS# 3

A_WE# 3

A_CAS# 3

A_DQM[0..1] 3
A_DQ[0..31] 3

F_D[0..7] 3

F_OE# 3

A_DQS[0..3] 3

A_CLK# 3

SDV25 3
VREF 3

F_A[0..20] 3

PCE# 3

PWR# 13

Title

Size Doc Nu mber Rev

Date: Sheet of

DDR MEMORY&FLASH

V1.2

C

515Wednesday, October 12, 2005

TSOP 48 pin

VREF DECOUPLING

Del By Ada

R32 75

CB56

0.1uF

CB68

0.1uF

C45
3300pF

CB65

0.1uF

RN20

47x4

1 2

3 4

5 6

7 8

RN9

47x4

1 2

3 4

5 6

7 8

CB114

0.1uF

R46 75

C40
3300pF

CB85

0.1uF

CB74

0.1uF

RN24

22x4

1 2

3 4

5 6

7 8

CB76

0.1uF

R48 75

R51 22

R29
0

CB63

0.1uF

CB58

0.1uF

RN18

47x4

1 2

3 4

5 6

7 8

C38
3300pF

R52 75

CB84

0.1uF

R41 4.7k

+

CE28

220uF/16v

CB97

0.1uF

R31 22

CB50

0.1uF

CB101

0.1uF

CB64

0.1uF

U9

MX29LV160BT

A0

25

A1

24

A2

23

A3

22

A4

21

A5

20

A6

19

A7

18

A8

8

A19

9

OE

28

BYTE

47

A18

16

D0

29

D1

31

D2

33

D3

35

A9

7

CE

26

D4

38

D5

40

D6

42

D7

44

D8

30

D9

32

A20

10

D11

36

D12

39

D13

41

D14

43

D15

45

VCC

37

GND1

27

WE

11

RY/BY

15

D10

34

GND2

46

A10

6

A12

4

A11

5

A13

3

A14

2

A15

1

A16

48

A1717NC

13

RESET

12

WP/ACC

14

+

CE24

220uF/16v

CB111

0.1uF

RN7

47x4

1 2

3 4

5 6

7 8

CB77

0.1uF

R40 22

C43

3300pF

R45 22

C35

3300pF

CB53

0.1uF

CB94

0.1uF

CB110

0.1uF

RN12

47x4

1 2

3 4

5 6

7 8

C39
3300pF

CB60

0.1uF

CB71

0.1uF

R34 47

CB52

0.1uF

RN14

75x4

1 2

3 4

5 6

7 8

TP7

8M x 16

DDR

U11

M13L128168 8Mx16-6/NC FOR ENTRY

VDD

1

DQ0

2

VDDQ

3

DQ1

4

DQ2

5

VSSQ

6

DQ3

7

DQ4

8

VDDQ

9

DQ5

10

DQ6

11

VSSQ

12

DQ7

13

NC

14

VDDQ

15

LDQS

16

NC

17

VDD

18

DNU

19

LDM

20

WE

21

CAS

22

RAS

23

CS

24

NC

25

BA0

26

BA1

27

A10/AP

28

A0

29

A1

30

A2

31

A3

32

VDD

33

VSS

66

DQ15

65

VSSQ

64

DQ14

63

DQ13

62

VDDQ

61

DQ12

60

DQ11

59

VSSQ

58

DQ10

57

DQ9

56

VDDQ

55

DQ8

54

NC

53

VSSQ

52

UDQS

51

NC

50

VREF

49

VSS

48

UDM

47

CK

46

CK

45

CKE

44

NC

43

A12

42

A11

41

A9

40

A8

39

A7

38

A6

37

A5

36

A4

35

VSS

34

CB83

0.1uF

+

CE31

220uF/16v

+

CE29

220uF/16v

CB96

0.1uF

CB102

0.1uF

RN13

75x4

1 2

3 4

5 6

7 8

RN19

75x4

12
34
56
78

RN5

22x4

1 2

3 4

5 6

7 8

R30

10k

CB79

0.1uF

CB72

0.1uF

R42 75

+

CE27

220uF/16v

CB61

0.1uF

RN16

47x4

1 2

3 4

5 6

7 8

CB57

0.1uF

R50 75

CB105

0.1uF

C47
3300pF

R33 47

CB82

0.1uF

CB107

0.1uF

CB51

0.1uF

C44
3300pF

CB73

0.1uF

R38 22

C49
3300pF

C48
3300pF

CB89

0.1uF

R43 22

C34
3300pF

CB98

0.1uF

R36 47

CB81

0.1uF

R28

10k

RN10

47x4

1 2

3 4

5 6

7 8

RN15

47x4

1 2

3 4

5 6

7 8

L16

FB

BEAD/SMD/0805

+

CE30

220uF/16v

R39 75

CB103

0.1uF

CB106

0.1uF

C46
3300pF

CB54

0.1uF

CB80

0.1uF

CB55

0.1uF

U12

IC LP2996 DDR Termination SOP8

SD

2

GND

1

VSENSE

3

VREF4VDDQ

5

AVIN

6

PVIN

7

VTT

8

CB112

0.1uF

CB91

0.1uF

CB90

0.1uF

C36
3300pF

RN2

75x4

1 2

3 4

5 6

7 8

CB88

0.1uF

RN22

75x4

1 2
3 4
5 6
7 8

RN1

22x4

1 2

3 4

5 6

7 8

+

CE25
47uF/16v

CB108

0.1uF

C37
3300pF

RN4

75x4

12

34

56

78

RN23

75x4

1 2

3 4

5 6

7 8

CB78

0.1uF

RN8

75x4

1 2

3 4

5 6

7 8

CB69

0.1uF

CB99

0.1uF

CB66

0.1uF

CB92

0.1uF

CB86

0.1uF

RN3

22x4

1 2

3 4

5 6

7 8

R49 22

CB62

0.1uF

RN21

75x4

1 2
3 4
5 6
7 8

CB109

0.1uF

R44 75

CB87

0.1uF

R35 47

CB75

0.1uF

CB113

0.1uF

CB59

0.1uF

U13 CM1117-2.5V

SOT223/SMD

IN

3

ADJ/GND

1

OUT

2

RN11

75x4

1 2

3 4

5 6

7 8

R37 75

8M x 16

DDR

U10

M13L128168 8Mx16-6

VDD

1

DQ0

2

VDDQ

3

DQ1

4

DQ2

5

VSSQ

6

DQ3

7

DQ4

8

VDDQ

9

DQ5

10

DQ6

11

VSSQ

12

DQ7

13

NC

14

VDDQ

15

LDQS

16

NC

17

VDD

18

DNU

19

LDM

20

WE

21

CAS

22

RAS

23

CS

24

NC

25

BA0

26

BA1

27

A10/AP

28

A0

29

A1

30

A2

31

A3

32

VDD

33

VSS

66

DQ15

65

VSSQ

64

DQ14

63

DQ13

62

VDDQ

61

DQ12

60

DQ11

59

VSSQ

58

DQ10

57

DQ9

56

VDDQ

55

DQ8

54

NC

53

VSSQ

52

UDQS

51

NC

50

VREF

49

VSS

48

UDM

47

CK

46

CK

45

CKE

44

NC

43

A12

42

A11

41

A9

40

A8

39

A7

38

A6

37

A5

36

A4

35

VSS

34

C42
3300pF

CB95

0.1uF

CB93

0.1uF

CB70

0.1uF

+

CE26
220uF/16v

CB104

0.1uF

C41
3300pF

RN17

75x4

12
34
56
78

CB100

0.1uF

CB67

0.1uF

RN6

75x4

12
34
56
78

R47 22

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

VGASDA

BLU_GND

HSYNC_VGA

GRN_GND

VGAVSYNC#
RED_GND

VGASCL

VGA_PLUGPWR

VGA_PLUGPWRVGA_PWR

VGA_IN_L
VGA_IN_R

VGASDA

VGASCL

VGA_SDA

GND

RED_GND

GRN_GND

BLU_GND

VGA_SCL

RED

GREEN

BLUEHSYNC#

VSYNC#

HSYNC#

VSYNC# VGAVSYNC#

HSYNC_VGA

VGA_R

BLUE

RED
GREENVGA_L VGA_IN_L

RSRXD
RSTXD

RSRXD

RSTXD

VGA_IN_R

RED

RED_GND

GREEN

GRN_GND

BLU_GND

BLUE

GND

GND

VSYNC#

HSYNC#

VCC

VGA_PLUGPWR

VGA_PLUGPWR

VCC

VCC

VCC

VCC

VCC

BLU_GND 8

RED_GND 8

VGAVSYNC# 3

HSYNC_VGA 3

GRN_GND 8

VGA_IN_R 12

VGA_IN_L 12

RED 8
GREEN 8
BLUE 8

RSTXD 1

RSRXD 1

Title

Size Doc Number Rev

Date: Sheet of

VGA IN&PC AUDIO IN

V1.2

B

615Wednesday, October 12, 2005

Modified by Bin_wang.22/7/05

Change by MICO

Change by MICO

R56 15K

C50

0.1uF

R58 15K

D15

SOT23/SMD

1

3

2

D2

DIODE SMD

1N4148/SMD

C51
5pF

D16

SOT23/SMD

1

3

2

R60

75K

L17

FB

BEAD/SMD/0603

R54
10k

D17

SOT23/SMD

1

3

2

R

L

P2

PHONEJACK STEREO

PHONEJACK/DIP

1
2
3
4
G

K1K2K3K4K5

D3

DIODE SMD

1N4148/SMD

L18

FB

BEAD/SMD/0603

CB115

0.1uF

R59

75K

R61

2.2k

D13

SOT23/SMD

1

3

2

R57 100

R53

10k

P3

D-SUB15 FEMALE

DSUB15/DIP/F

1617

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

R62

2.2k

R55 100

D14

SOT23/SMD

1

3

2

U14

EEPROM 24C02

NC

1

NC

2

NC

3

GND4SDA

5

SCL

6

WP

7

VCC

8

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

CB2SWB

CR2SWB

Y2_GNDB

CB2_GNDB

CR2_GNDB

TU_VCC

CB1SWB

CBQ

GNDS

YQ

Y2SWB

Y1SWB

CB2SWB

GNDS

CR1SWB

CRQ

CR2SWB

YPBPR2_L
YPBPR2_R

AF1_OUT

SIF1_OUT

CB_GND

Y_GND

SOY

Y

CR_GND

CR

CB

SDA

SCL

Y_GND

CB_GND

CR_GND

CB1_INB

AF1_OUT

TV_GND

TV

TUNER_12V

Y1_GNDB

CB1_GNDB

CR1_GNDB

AV_L
AV_R

CR1_INB

Y1SWB

CB1SWB

CR1SWB

ORO2

YPBPR1_L
YPBPR1_R

SIF1_OUT

YPBPR1_R

CR2B

Y1_GNDB

Y1_GNDB

CR1_GNDB

Y2_INB

CR2_INB

CB1_GNDB

CR1_GNDB

CR2_GNDB

YPBPR1/R YPBPR1/L

YPBPR2/R YPBPR2/L

SC_IN
SC_GND1 SY_GND1

SY_IN

ORO2

CB2_GNDB

CB1_GNDB

Y2_GNDB

OGO6

DVI_L
DVI_R

AV2_IN
AV2_GND

AV2_R

AV2_L

CB3B

Y3_GNDB

CB3_GNDB

CR3_GNDB

Y3B Y3SWB

CR3SWB

CB3SWB

CBQ

CB

GNDS

Y

Y3SWB

YQ

CB3SWB

GNDS

CRQ

CR

CR3SWB

GPIO_DVD0
GPIO

CB1B

OGO[0..6]

SDA

SCL

AV/L

AV/R

TU_12V

+12V

SY_IN
SY_GND1
SC_IN

SC_GND1

DVI/R

AV/L

YPBPR1_LYPBPR1/L

YPBPR1/R

AV/R AV_R

DVI/L

YPBPR2/R

Y1_INB Y1B

AV1_GND

AV1_R

AV1_IN

CR2_INB

CB2B

Y2_INB Y2B Y2SWB

CB1_GNDB

CR3B

Y1_GNDB

Y3SOY

Y2SOY

Y1SOY

Y1SOY
Y2SOY
SOYQ SOY

Y3SOY

SOYQ

AV2_R

AV1_L

DVD/R

DVD/L

AV2_L

AV1_R

DVD+5V

DVD/CR_IN

GPIO_DVD0

DVD/CB_IN

DVD+5V

GND
GND

DVI/R

DVI/L

DVD/CB_IN

DVD/Y_GND

DVD/Y_IN

DVD/CB_GND

DVD/CR_GND

Y1_GNDB

DVD/Y_IN
DVD/CR_GND

CR1_GNDB

DVD/R

DVD/CR_IN

DVD/Y_GND

DVD/L

YPBPR2/L YPBPR2_L

TV
TV_GND
AV1_IN
AV1_GND

AV2_GND

AV2_IN

CR1B

DVD/CB_GND

AV1_L

AV_L

DVI_L

DVI_R

YPBPR2_R

CB2_INB

CR1_GNDB

CB1_GNDB

DVD+5V

GPIO_DVD2

DVD_IR

CB2_INB

Y1_INB

CB1_INB

CR1_INB

IR

IR

GPIO_DVD2

GPIO_DVD0

OGO6

SOYQ SOY

YQ Y

CBQ CB

CRQ CR

GPIO

AV1_L

AV1_R

AV/L

AV/R

DVI/R
GND
DVI/L
GND

TUNER_12V

VCC

VCC

VCC

TU_VCC

TU_12V

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC VCC

+12V

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

CB 8

SOY 3

CR_GND 8

Y8

CR 8

CB_GND 8

Y_GND 8

SDA 1,10

SCL 1,10

TUNER_12V 1

YPBPR2_R 12

YPBPR2_L 12

SIF1_OUT 8
AF1_OUT 8

AV_L 12
AV_R 12

ORO2 3

YPBPR1_L 12
YPBPR1_R 12

OGO6 3

DVI_L 12
DVI_R 12

GPIO_DVD0 3
GPIO 3,10

OGO[0..6] 3,9,13

+12V 1,10,13,14

SY_IN 8
SY_GND1 8

SC_GND1 8

SC_IN 8

TV 8,12
TV_GND 8
AV1_IN 8,12
AV1_GND 8

AV2_GND 8

AV2_IN 8,12

GPIO_DVD2 3
IR 3,11

Title

Size Doc Nu mber Rev

Date: Sheet of

VIDEO IN & TUNER IO

V1.2

C

715Wednesday, October 12, 2005

NEARLY YPBPR2-CON.

TUNER IN

NEARLY YPBPR1-CON.

COMPONENTS SWITCH.

AV1 & S-VIDEO AUDIO IN

EMC Ready

8/18 modify by steven

9/05

Change by MTK

Change by MICO

ADD BY MICO

+

CE85

22uF/25v

P4

RCA1X3

RCA5/9P/Y

3
1

4

6

7

9

2

5

8

R123
75K

R312 0

U26

IR7314

S1

1

G1

2

S2

3

G24D2

5

D2

6

D1

7

D1

8

D9
BAV99

1

3

2

J6

4x1 W/HOUSING

DIP4/W/H/P2.0

1
2
3
4

R78 0

R285
47k

D8
BAV99

1

3

2

R276
47k

+

CE42
1000uF/16v

C52
100pF

FB7 0

R95

4.7k

J8

4x1 W/HOUSING

DIP4/W/H/P2.0

1
2
3
4

FB4 0

R269

10K

R79
75

R12
10k

FB11 0

R279
47k

R121
75K

R313 0

+

CE87

22uF/25v

D7
BAV99

1

3

2

R107

4.7K

R8615K

+

CE83

22uF/25v

R9415K

L19
FB

C117
100pF

JP1
CON\SVHS

213

4

567

L22

FB

FB10 0

R69 0

P7

RCA2

RCA2/4P/DIP

3

2

1

4

5

R351 0/NC

FB3 0

L21
FB

R100
75

D5
BAV99

1

3

2

FB12 0

R282
47k

J9

5x1 W/HOUSING R.A.

PH5/2.5

1

2

3

4

5

R118
75K

R9715K

U17

CD 4052BC

SOP16/SMD

3X

11

0X

12

2Y

2

0Y

1

1Y

5

Y31X

14

A

10

B

9

X

13

3Y

4

VEE

7

INH

6

VCC

16

VSS

8

2X

15

R283
47k

R8415K

R275
47k

J7

10x1 W/HOUSING

PH10/2.0

1
2
3
4
5
6
7
8
9

10

C127
100pF

P5

RCA2

RCA2X2/6P/DIP

321

4

5

6

+

CE39 22uF/10V

+

CE34 22uF/10V

R67
10K

R65 0

R71 0

C122 4.7nF

FB13 0

C124 4.7nF

U16

IDTQS3VH257/TIV330

TSSOP16/SMD

I1B

6

I0A

2

I1A

3

S

1

YA

4

I0B

5

YB

7

GND

8

I0D

14

E#

15

I1D

13

I0C

11

YD

12

VCC

16

I1C

10

YC

9

+

CE86

22uF/25v

R64
75

R89
75

R119
75K

R274
47k

D6
BAV99

1

3

2

R10315K

L23

FB

C128
100pF

+

CE36 22uF/10V

R63 0

R74 0

R10215K

+

CE40 22uF/10V

R350 0/NC

L48

FB

BEAD/SMD/1206

C53

0.1uF

R281
47k

+

CE32 22uF/10V

+

CE82

22uF/25v

R278
47k

FB5 0

R68
10K

R72

75

R120
75K

R70
75

+

CE38 22uF/10V

R267
22K

R9215K

C129
100pF

R300
10K

R299

10K

C54

0.1uF

R11
10k/NC

R98 0

+

CE33 22uF/10V

+

CE84

22uF/25v

R272
47k

C123 4.7nF

R8715K

+

CE41

1000uF/16v

Q2

2N3904

SOT-23

1

2 3

D12
BAV99

1

3

2

R66
75

R268
22K

R124
75K

C130
100pF

R76 0

D10
BAV99

1

3

2

D11
BAV99

1

3

2

J5

CON12

PH12/2.0

1
2
3
4
5
6
7
8
9
10
11
12

R280
47k

R311 0

FB6 0

R122
75K

R314 0

D4
BAV99

1

3

2

U15

IDTQS3VH257/TIV330

TSSOP16/SMD

I1B

6

I0A

2

I1A

3

S

1

YA

4

I0B

5

YB

7

GND

8

I0D

14

E#

15

I1D

13

I0C

11

YD

12

VCC

16

I1C

10

YC

9

+

CE35 22uF/10V

R85 0

CB116

0.1uF

R277
47k

+

CE37 2 2uF/10V

P6

RCA1X3

RCA2X2/6P/DIP

1
2

3
4

5
6

R75
75

Q3

2N3904

SOT-23

1

2 3

L20
FB

R77
75

C131
100pF

R125
75K

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

CVBS1+CVBS1

CVBS1-

BLUE

RED

GREEN

CB-

CB+

CR+

Y-

Y+

CR-

RED+

BLUE+

GREEN-

RED-

GREEN+

BLUE-

SY-

SY+

SC-

SC+

CVBS0+

CVBS0-

CVBS1+

CVBS1-

TV

AF1_OUT

SIF1_OUT

SIF1_OUT

MPX1

MPX2

VGASOG

GRN_GND

BLU_GND

RED_GND

Y

CR

CB

SOY

SC+

SC-

SY-

Y

CR

SY

CB

SY+

BLUE+

GREEN+

GREEN-

BLUE-

RED+

RED-

CVBS1_GND

TV_GND

AV1_IN

AV1_GND

CB_GND

Y_GND

CB_GND

CR_GND

AF1_OUT

CB+

CB-

CR+

Y+

CR-

Y-

MPX2

MPX1

VGASOG

SC_GND

SY_GND

CVBS0+CVBS0

CVBS0-

RED RED_IN

BLUE

RED_GND

GREEN

GRN_GND

BLU_GND

BLUE_IN

GREEN_IN

CVBS2+CVBS2

CVBS2-

CVBS2+

CVBS2-

AV2_GND

AV2_IN

Y_GND

CR_GND

SY_GND1

SC_GND1

SC_IN

SY_IN

SC

SY_IN

SY_GND1

SC_IN

SC_GND1

AV1_IN

AV1_GND

TV

TV_GND CVBS0_GND

AV2_IN

AV2_GND CVBS2_GND

RED 6

GREEN 6

BLUE 6

CB+ 3

CB- 3

CR+ 3

CR- 3

Y- 3

Y+ 3

BLUE+ 3

GREEN- 3

RED+ 3

RED- 3

GREEN+ 3

BLUE- 3

SY- 3

SY+ 3

SC- 3

SC+ 3

CVBS0+ 3

CVBS0- 3

CVBS1+ 3

CVBS1- 3

TV 7,12

AF1_OUT 7

SIF1_OUT 7

MPX2 3

MPX1 3

VGASOG 3

BLU_GND 6

GRN_GND 6

RED_GND 6

CR 7

CB 7

Y7

SOY 3,7

TV_GND 7

AV1_IN 7,12

AV1_GND 7

Y_GND 7

CB_GND 7

CR_GND 7

CVBS2+ 3

CVBS2- 3

AV2_GND 7

AV2_IN 7,12

SY_IN 7

SY_GND1 7

SC_GND1 7

SC_IN 7

Title

Size Doc Nu mber Rev

Date: Sheet of

AUDIO/VIDEO IN CIRCUIT

V1.2

C

815Wednesday, October 12, 2005

FROM Tuner

OUTPUT

INPUT

Close VGA input interface Close to MT8205

Close to 8205.

Close to 8205.

R131

100

FB8

0

L24

FB

BEAD/SMD/0603

FB1

0

C70

47nF

C72

47nF

FB9

0

L25

FB

R146 0

C56

15pF

R152

75

R90 18

R154 0

C68

15pF

R128

100

R108

0

R158 68

R156

75

R147 8.2K

C86
5pF

C71
330pF

R111
56

C85
15pF

C66

47nF

C62

15pF

R143

22

R82
56

C90
5pF

C60

47nF

C84
15pF

C69

47nF

C80
15pF/NC

R155 68

R151 68

R110
75

R105

18

C93
5pF

C55

47nF

R132

0

C81
15pF/NC

+

CE44

47uF/16v

C88

4.7nF

C64

47nF

C57

47nF

L28

FB

BEAD/SMD/0603

R80 18

R136

100

C91

47nF

R116
75

C82

47nF/NC

L29

FB

R148

0

R141

100

C61

47nF

R144

0

C89

47nF

C87

47nF

C83

47nF

C75

47nF

C63

47nF

R140

22

C65
330pF

R138

0

R149 39k

C92

47nF

C79

47nF

R153 100

R157 100

+

CE43

47uF/16v /NC

L26

FB

BEAD/SMD/0603

C67

47nF

L27

FB

FB2

0

R114

0

C59
330pF

C76

47nF

C58

47nF

FB14

0

C74
330pF

C73

47nF

R135

22

R159

75

C77
330pF

C94

47nF

R142

0

C78

47nF

R93
56

R133

100

R145

22

R160 100

R150 39k

R130

22

R137

100

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

DDCDVISDA

DVIPWR

DVIHSYNC0

DVISCL

VI[0..23]

DVIVSYNC0

DVI16
DVI17
DVI18
DVI19

DVI12
DVI13

DVI8
DVI9
DVI10

DVI15

DVI14

DVI11

DVI4

DVI6

DVI5

DVI0

DVI2
DVI3

DVI1

VI3

VI2

VI1

DVI7

VI0

VI7

VI6

VI5

VI4

VI11

VI10

VI9

VI8

VI15

VI14

VI13

VI12

VI19

VI18

VI17

VI16

VI23

VI22

VI21

VI20DVI20
DVI21
DVI22
DVI23

DATA1+

DVISCDT

DVISCDT

DVIPDO#

DVIPVCC

DVIPDO#

DVIPVCC

DVIAVCC

DVI18
DVI17
DVI16

DVI19

DVI20

DATA0-

DVI21

DVI0

DVI2

DVI23

DVI1

DVI22

DATA1-

CLOCK+
CLOCK-

DVI3

DVI4

DDC_SDA

8205UP1_2

DVIRST#

DVIHSYNC

DVI5

DVIVSYNC

DVI6

DVIPWR

DVIODCK

DATA0+

DVIDE

DVI7

DDCDVISCL

DVIRST#

DVISCL

DVIPWR

EXT_RST

HS_DJTR

DVIAVCC

OCK_INV

CTL3

DVIPD#

DVISDA

DVISDA

DVICAB 8205UP1_2

DVIODCK0

DVIDE0DATA2+

DVIVSYNC0

DVIHSYNC0

DATA2-

DATA1+

DATA0-

DATA0+

DATA1-

DVIDE0

CLOCK+
CLOCK-

DVI13

DVI10

DVI9

DVI11

DVI8

DVI12

DVISCL
DVISDA

DVI14

DDC_SCL

DVI15

DVISTAG

DVIODCK0

OGO4

DVIPIXS

DVIHSYNC

DVISCL

DVIVSYNC

DVIDE

DVISTAGHS_DJTR

DVIPWR

DVIODCK

F_A21

OGO4

DVISDA

DDCDVISCL

DVIPWR

OCK_INV

F_A21

DDCDVISDA

DDCDVISCL
DDCDVISDA

DATA2­DATA2+

DVIPIXS

DVIPDO#DVIPD#

DVIPWR

DVIPWR

DVIPWR

DVIPWR

M_S#

M_S#

DATA2-

DATA2+

GND

DATA1+

GND

DATA1-

GND

DATA0+

GND

DATA0-

GND

CLOCK+

GND

CLOCK- DDC_SCL DDC_SDA

DVI_PLUGPWR

GND GND

GND

GND

DVI_PLUGPWR

DVICAB

DVIPWR DVIPWRDVIPWR DVIPWRDVIPWRDVIPWR DVIPWR

DVIPWR

DVI_PLUGPWR

DVIAVCC

DV33

DV33A

DVIPWR

DVI_PLUGPWR

DV33A

DVIPWR

DVIPWR

DVIPWR

DVIPWR

DVIPWR

DVIPWR

DVIPWR

VCC

VCC

VCC

VCCVCC

VCC

VCC VCC VCC VCC

VCC

DVI_PLUGPWR

VI[0..23]

8205UP1_2

DVIHSYNC
DVIVSYNC

DVIODCK
DVIDE

DVISCL
DVISDA

OGO4

F_A21

Title

Size Doc Nu mber Rev

Date: Sheet of

DVI INPUT

V1.2

C

915Wednesday, October 12, 2005

When use Sil169/Sil1161 ADD R333

RED

GREEN

BLUE

CHANGE

WHEN SIL161 ADD R173 R174

WHhen use Sil161 R326 NC,Add R172

When use Sil169//Sil1169 R172 NC,Add R326

WHEN Sil169/ Sil1169 R173 R174 NC

WHEN USE Sil169/sil1169 ADD

CHANGE

DVISCL REPLACE OCK_INV NET
DVISDA REPLACE ST

WHEN USE Sil169 add R327 R332

Add by MTK

WHEN USE Sil1169 ADD R345,NC R175

WHEN USE Sil169//Sil161 ADD R175 , NC R345

When Sil169/Sil161 R346 NC
Add R347

WHEN USE Sil161 NC R331 R332

WHEN USE Sil1169 add R331 R332

Add By MTK

Add By MTK

ADD BY MTK

C102
220pF

R333
0

C101
10uF/10v

R165
390

C112
220pF

C95
10uF/10v

D31

SOT23/SMD

1

3

2

L33

FB BEAD/SMD/0603

C111
10uF/10v

R88

0/NC

R0603/SMD

R347
10k/NC

CB118

0.1uF

R168
10k

R171
10k

R162 100

C105
10uF/10v

RN28

33x4

12
34
56
78

R173
10k/NC

C109
10uF/10v

R91

0/NC

R0603/SMD

TP8

R163
10k

R325

4K7

R172

0.1uF

R330 0

RN25

33x4

12
34
56
78

D30

SOT23/SMD

1

3

2

C108
220pF

R176
R/NC

TP11

R332
0

SiI 161B

U18

SiI 169

TQFP100/SMD

OCK_INV

100

RESERVED

99

PGND

98

PVCC

97

ST3PD#

2

EXT_RST

96

AVCC

95

RXC-

94

RXC+

93

RX0+

90

AVCC

88

AGND

87

RX1-

86

RX1+

85

AVCC

84

AGND

83

AVCC

82

RX2-

81

QE16

30

OVCC

29

OGND

28

QE15

27

QE14

26

QE1325QE1224QE1123QE1022QE921OE820OGND19OVCC18QE717QE616QE515QE414QE313QE212QE111QE010PDO9SCDT8STAG_OUT7VCC6GND

5

RX0-

91

AGND

92

HS_DJTR

1

QE17

31

QE18

32

QE19

33

QE20

34

QE21

35

QE22

36

QE23

37

VCC

38

GND

39

CTL1

40

CTL2

41

CTL3

42

OVCC

43

ODCK

44

OGND

45

DE

46

VSYNC

47

QO2

51

HSYNC

48

QO1

50

QO352QO453QO554QO655QO7

56

OVCC

57

OGND

58

QO859QO9

60

QO1061QO1162QO1263QO1364QO1465QO15

66

VCC

67

GND

68

QO1669QO1770QO1871QO1972QO2073QO2174QO22

75

OGND

76

QO23

77

OVCC

78

AGND

79

RX2+

80

QO0

49

PIXS

4

AGND

89

R310
10k

+

C134

1uF/25V/NC

D22

1N4148/SMD

RN31

33x4

12
34
56
78

R164
100k

R324

4K7

R177 0

R331
0

C104
220pF

TP10

RN27

33x4

12
34
56
78

R170
10k

C99

0.1uF

D36

SOT23/SMD

1

3

2

D37

SOT23/SMD

1

3

2

R81

10k/NC

R328

4.7K/NC

QF4

MOSFET N 2N7002

SOT23/SMD

1

32

C110
220pF

C106
220pF

TP12

R327

4.7K/NC

R323
4K7

D18

DIODE SMD

1N4148/SMD

R167 R

R344

R/NC

C98
220pF

RN30

33x4

12
34
56
78

R174
10k/NC

TP9

D33

SOT23/SMD

1

3

2

R169
10k

L31

FB

P8 DVI-I DIP 34P

1
2
3
4
5
6
7
8

9
10
11
12

13
14
15
16
17
18
19
20
21
22

24

23

2526

2728

29

30

31

32

33 34

+

CE45

100uF/16v

C103
10uF/10v

D29

SOT23/SMD

1

3

2

D35

SOT23/SMD

1

3

2

R83

0/NC

D34

SOT23/SMD

1

3

2

L32

FB BEAD/SMD/0603

R345
10k/NC

R322
4K7

RN26

33x4

12
34
56
78

C97
10uF/10v

R326
10K

C100
220pF

R346
10k/NC

R175
0

D38

SOT23/SMD

1

3

2

R161 100

R329
4k7/NC

C107
10uF/10v

C113
10uF/10v

D32

SOT23/SMD

1

3

2

RN29

33x4

12
34
56
78

C96
220pF

QF3

MOSFET N 2N7002

SOT23/SMD

1

32

U19

EEPROM 24C02

NC

1

NC

2

NC

3

GND4SDA

5

SCL

6

WP

7

VCC

8

R166 0

CB117

0.1uF

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

AP[0..7]
AN[0..6]

GPIO

SDA_8205

R
G
B
VSYNC
HSYNC

GND

R
G
B

HSYNC
VSYNC

LVDSVDD

GND

SDA

SCL

R

GND

GND

B

G

CLK1+
CLK1-

AN0
AP0
AN1
AP1

CLK1-

AN2
AP2

AN4

CLK1+

AP4

AN3

AN5
AP5

AP3

AP7

LVDSVDD

ORO6

SEL_AP7_IRQ

+12V

SCL_P
SDA_P

SCL_8205

SCL

SDA

DV33A

DISPEN_PDWN_READY

PDPGO

AN6

AP6

CPUGO

SCL1

SCL_P

SDA1

SDA_P

SDA1

SCL1

8205UP1_4

ORO5

GPIO

SDA_8205

SCL_8205

ORO5
8205UP1_4

ORO1
ORO3

ORO3

ORO1

ORO1
ORO3

ORO6ORO6

5VSB

+12V

+12V

DV33A

VCC

5VSB

5VSB

DV33A

DV33A

DV33A

DV33A

5VSB

DV33A

5VSB

5VSB

GPIO 3,7

AP[0..7] 3
AN[0..6] 3

SDA 1,7

SCL 1,7

ORO6 3

CLK1+ 3
CLK1- 3

G3

R3

B3
VSYNC 3
HSYNC 3

+12V 1,7,13,14

SDA1 12

SCL1 12

SDA_8205 3

SCL_8205 3

ORO5 3
8205UP1_4 3

ORO1 3, 14
ORO3 3, 14

ORO1 3 ,14
ORO3 3 ,14

Title

Size Doc Nu mber Rev

Date: Sheet of

LVDS/CRT OUT

V1.2

C

10 15Wednesday, October 12, 2005

LVDS OUT(Include PDP and 32' LCD LVDS interface)

CRT OUT

WHEN NOT USE PDP ADD L49 R178 R290 R292
REMOVE R179 R185 R186 R187 R291 R293

WHEN USE LG V7 PDP ,ADD R185 R286 R179
WHEN USE SangsungSD1 PDP ,ADD R186 R187 R185 R286
WHEN USE Fujitsu 42 PDP ,ADD R179 R186 R187 R185 R286 R291 R293.REMOVE R178 R290 R292

WHEN USE LG V6 PDP ,ADD R185 R286 ,Must del R193 R194

4.7K REPALAC 47K

Change By Ada

8205UP1_4 Repalce ADIN3

ORO5 Repalce ADIN2

CHANGE

Change by MICO

Change by MICO

Change By MTK

R286

4.7k

F1

4A/?v

FUSE/DIP/P10.0

L49 FB

BEAD/SMD/1206

R361
10K

R193 0/NC

R303
10K

QF1

MOSFET N 2N7002

SOT23/SMD

1

32

R292 0/NC

+

CE48
220uF/16v

R291 0/NC

R293 0/NC

R353

10K

R298
0

J10

FI-SE30P-HF

LVDS/30P/P1.25/S

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

J11

8x1 W/HOUSING

DIP8/W/H/P2.54

1
2
3
4
5
6
7
8

R188 0

R297
0

R362
10K

R183

4.7k

R301
10K

R185 0

R178 0/NC

R182

4.7k

R184

10k

R349

10K

L52FB BEAD/SMD/1206

R363
10K

CB120

0.1uF

R197

75 1%

R186 100/NC

R352

10K

R348

10K

R296 0

QF2

MOSFET N 2N7002

SOT23/SMD

1

32

R180

4.7k/NC

R187 100/NC

+

CE49
220uF/16v

R191

4.7k

R179 0/NC

R302
10K

R196

75 1%

+

CE47
330uF/25v

C330UF25V/D8H14

R290 0/NC

L34

FB

BEAD/SMD/1206

CB119

0.1uF

R364
10K

Q4

2N3904

SOT23/SMD

1

3 2

R295 0

R181

4.7k

R192 0

+

CE46
220uF/16v

R195

75 1%

L51FB BEAD/SMD/1206

R189

4.7k

R194 0/NC

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

OBO0

OBO1

OBO2

OBO3

OBO4

OBO5

IR

VOL+
CH­CH+

OBO1 MENU

TV/AVOBO0

VOL-

OBO3

IR

OBO6

OBO7

LED_RED

OBO7

OBO6

PWM0

PWR_GND

Inverter_PWR

BL_ON/OFF

8205UP3_0

Inverter_PWR

Inverter_PWR

SELECT

Inverter_PWR

Dimming

8205UP3_0

PWM0

POW

PWR_GND

INVERTER_PWR

OBO[0..7]

PWR_GND

PWR_GND

LED_GRN

8205UP1_2

PWR_GND

OBO5

OBO4

OBO2

TV/AV
MENU
VOL­VOL+
CH­CH+

LED_RED
LED_GRN

IR

8205UP1_2

POW

8205UP1_2

5VSB

DV33A

VCC

VCC

VCC

5VSB

5VSB

OBO0 3

OBO1 3

OBO2 3

OBO3 3

OBO4 3

OBO5 3

IR 3,7

OBO6 3

OBO7 3

8205UP3_0 3

PWM0 3,14

PWR_GND 1
INVERTER_PWR 1

OBO[0..7] 3

8205UP1_2 3,9

PWR_GND 1

Title

Size Doc Nu mber Rev

Date: Sheet of

BACK_LIGHT/KEYPAD

V1.2

C

11 15Wednesday, October 12, 2005

KEYPAD - MAX 8-KEYS

IR & POWER ON LED

Back Light circuit

PANEL INVERTER POWER

FOR AU 32" INVERTER CONNECTOR

External PWM input
for dimming control

9/05

L35
FB

BEAD/SMD/1206

R315

10K

R204
0

R209 510

R203
10k

L41 FB

Q6
2N3904

SOT23/SMD

1

3 2

R207
10K

R0603/SMD

R. ANGLE

J12

14x1 W/HOUSING

DIP14/WH/P2.0/R

1
2
3
4
5
6
7
8

9
10
11
12
13
14

R211 4. 7K

R316

10K

R205

4.7k

R199
10k

R201 4.7k

J19

CON9

1
2
3
4
5
6
7
8
9

R210 0

R317

10K

+

CE51
470uF/50v

R212 4.7K

L38 FB

CB122

0.1uF

R206 510

R200

100k

R318

10K

R109

10K

L40 FB

Q5
2N3904

SOT23/SMD

1

3 2

J20

CONN RCPT 5

1
2
3
4
5

Q7
2N3906

1

3 2

J14

13x1 W/HOUSING

DIP13/W/H/P2.0

1
2
3
4
5
6
7
8

9
10
11
12
13

R319

10K

CB123

0.1uF

R. ANGLE

J13

10x1 W/HOUSING R.A.

DIP10/WH/P2.0/R

1
2
3
4
5
6
7
8
9

10

L42 FB

R320

10K

R202
R

L36
FB

BEAD/SMD/1206

Q8
2N3906

1

3 2

L37 FB

CB121

0.1uF

+

CE50
470uF/50v

L39 FB

R208
10K

R0603/SMD

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

SDA1

SCL14

SDA14

SCL14

COD_VOUTR

COD_VOUTL

VGA_IN_R

VGA_IN_L

MUTE

CODHPOUTR

CODHPOUTL

CODHPOUTR

CODHPOUTL

YPBPR1_L

YPBPR2_L

YPBPR1_R

YPBPR2_R

DACLRC

ADCREFP

DVDD

HPVDD

VMIDADC

PWM0

DV33

DVDD

DACBCLK
DACMCLK

DACLRC

AOSDATA1

DOUT

DACBCLK
DACMCLK

DACLRC

DOUT

HPVDD

DACMCLK
DACLRC

SCL1

COD_VOUTL

COD_VOUTR

SDA14

DACBCLK

HPVDD

VMIDDAC

ADCREFP

VMIDADC

L_BYPASS

DACVA

R_BYPASS

DACBCLK

AOSDATA3

DACMCLK

DACLRC

AUSPR

AUSPL

+12V

VGA_IN_R

VGA_IN_L

AV_R

AV_L

YPBPR1_R

YPBPR1_L

YPBPR2_R

YPBPR2_L

GND

R_BYPASS

L_BYPASS

AV1_IN

V_BYPASSTV

ORO4

AOSDATA1

AOSDATA3

DVI_R

DVI_L

AV2_IN

ORO7

DVI_L
DVI_R

TV
AV_L
AV_R

DACVA

SDA1

SCL1

V_BYPASS

OGO7 LINE_MUTE

ORO4
ORO7

HPVDD_

OGO7
PWM1

PWM1

AV1_IN
AV2_IN

AUSPR

AUSPL

GND

MUTE

GND

GND

GND

GND

DVDD

VCC

DV33

HPVDD

VCC

VCC

VCC

VCC

5VSB

VGA_IN_R 6

VGA_IN_L 6

MUTE 3

YPBPR1_L 7

YPBPR2_R 7

YPBPR1_R 7
YPBPR2_L 7

AOSDATA1 3
AOSDATA3 3

PWM0 3,11

DOUT 3

DACLRC 3

DACMCLK 3

DACBCLK 3

+12V 1,7,10,13,14

ORO4 3
ORO7 3

DVI_L 7
DVI_R 7

TV 7,8
AV_L 7
AV_R 7

SDA1 10

SCL1 10

OGO7 3
PWM1 3

AV1_IN 7,8
AV2_IN 7,8

Title

Size Doc Nu mber Rev

Date: Sheet of

WM8776/WM8766/AUDIO CODEC

V1.2

C

12 15Wednesday, October 12, 2005

MUST USE SHIELD CABLE

TWO WIRE SERIAL CONTROL DEVICE ADDRESS 0x34h

TO AUDIO BD

AUDIO BYPASS.

A/V Bypass

SPK SWICTH(PDP) BY MICO

OGO7 Repalce ADIN0 -----MTK
PWM1 Repalce ADIN1 -----MTK

Change

R215 100k

L43

FB

CB126

0.1uF

R234 33

L45

FB

R216 100

+

CE60 10uF/25v

R214 100k

+

CE71

10uF/25V

CB127

0.1uF

+

CE72
47uF/16v

R238 43,1%

R307
10K

CB132
1uF

R224 100k

R217 100k

+

CE62
10uF/25v

CB131

0.1uF

+

CE61 10uF/25v

+

CE73

10uF/25v

R220 5 0k

CB125

0.1uF

J16

5x1 W/HOUSING

PH6/2.0

1
2
3
4
5
6

+

CE74
100uF/16V

R213 100k

CB130

0.1uF

R226 100k

+

CE64 10uF/25v

R14
33

C125

10uF/10v

U20

WM8776

AIN2L

1

AIN1R

2

AIN1L

3

DACBCLK

4

DACMCLK

5

DIN

6

DACLRC

7

ZFLAGR

8

ZFLAGL

9

ADCBCLK

10

ADCMCLK

11

DOUT

12

ADCLRC13DGND14DVDD15MODE16CE17DI18CL19HPOUTL20HPGND21HPVDD22HPOUTR23NC

24

NC

25

VOUTL

26

VOUTR

27

VMIDDAC

28

DACREFN

29

DACREFP

30

AUXR

31

AUXL

32

VMIDADC

33

ADCREFGND

34

ADCREFP

35

AVDD

36

AGND

37

AINVGR38AINOPR

39

AINVGL40AINOPL

41

AIN5R

42

AIN5L

43

AIN4R

44

AIN4L

45

AIN3R

46

AIN3L

47

AIN2R

48

R237 33

R334

10K

C116
100pF

U23

BA7612F

IN11OUT

8

A2VCC

7

B3IN3

6

IN24GND

5

+

CE65 10uF/25v

FB15 FB

BEAD/SMD/0805

R306
10K

R236 33

+

CE75
100uF/16V

R227 100k

R13

0

C126

10uF/10v

R240

75/NC

C118 1uF

+

C114

10uF/25v

+

CE70

10uF/25v

+

CE55 10uF/25v

R231

10k

+

CE54 10uF/25v

C115
100pF

R235 33

R219 100k

R229
1k

R10
10k

C119 1uF

R239
75

CB128

0.1uF

+

CE56 10uF/25v

R232

10k

+

CE59 10uF/25v

+

CE69
10uF/25v

+

CE67
10uF/25v

CB124

0.1uF

R225 100k

R233
0

R0805/SMD

+

CE53 10uF/25v

J15

CON8

1
2
3
4
5
6
7
8

R221 5 0k

U22

CS4334 2-CH AUDIO DAC

SOP8/SMD

SDATA

1

DEM#/SCLK

2

LRCK

3

MCLK4AOUTR

5

AGND

6

VA

7

AOUTL

8

+

CE76 220uF/16v

R241
75/NC

R218 100

R222 100k

R230
10k

+

CE57 10uF/25v

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

+12V

TXD

DVIVSYNC

DVIODCK

RXD

DVIHSYNC
DVIDE

READY#

DACLRC

DACMCLK
DACBCLK

REQUEST#

OGO5
OGO6

VI[0..23]

8205UP1_3

OGO3
OGO1
OGO2
OGO0

OGO5

SW

+12V12V

PCRXD
PCTXD

12V

5V

5V

TXD

RXD_2

TXD_2

RXD

WE#
PWR#

PCTXD

READY#

WE#

TXD_0

RXD_0

SW

SW

PCRXD

PWR#

TXD_2

RXD_2

PCTXD

PCRXD

GND

RXD

TXD

REQUEST#

VI3

VI2

VI1

VI0

VI4
VI5
VI6
VI7

VI8
VI9
VI10
VI11

VI12
VI13
VI14
VI15

VI18
VI19

VI16
VI17

VI22
VI23

VI20
VI21

OGO4

REQUEST0#

RXD_2

REQUEST0#

TXD_2

READY0#

TXD_0

READY0#

8205UP1_3

GND

RXD_0

OGO4

DVIODCK

DVIDE

DVIVSYNC

DVIHSYNC

OGO2
OGO0

OGO1

OGO3

+12V

DV33A

VCC

DV33A

5VSB

5VSB

DV33A

DV33A

DV33A

5VSB

DV33A

DV33A

DV33A

DV33A

5VSB

DV33A

DV33A

+12V 1,7,10 ,14

DACBCLK 3,12

DACMCLK 3,12

DACLRC 3,12

READY# 3

REQUEST# 3

TXD 1,3
RXD 1,3

DVIHSYNC 3,9

DVIVSYNC 3,9

DVIDE 3,9
DVIODCK 3,9

OGO5 3
OGO6 3,7

VI[0..23] 3,9

8205UP1_3 3

OGO3 3
OGO1 3
OGO2 3
OGO0 3
SW 3
PCRXD 1
PCTXD 1

WE# 3
PWR# 5

OGO4 3,9

Title

Size Doc Number Rev

Date: Sheet o f

ATSC INTERFACE

V1.2

Custom

13 15Wednesday, October 12, 2005

Trace width of 12V>30mil
Trace width of 5V >40mil

LO = > DTV BOARD POWER ON

HI = > DTV BOARD POWER OFF

"GND Need Very Strong"

TXD_0:MT5351 Transmit
RXD_0:MT5351 Receiver
TXD_2:MT5351& MT8205 Communication
RXD_2:MT5351& MT8205 Communication

Add by MTK

PC <---> MT5351 U0

Function

SW

MT5351 U2 <---> MT8205

MTK Modify

PC -----> MT5351 U0RX

PC <---> MT8205

0

1

WHEN OGO4 HIGH , DVI OUPUT
WHEN OGO4 LOW ,ATSC OUPUT

ADD 22/9

R339
0/NC

R248
10k

J17

DIP8/W/H/P2.54

1
2
3
4
5
6
7
8

Q10

2N3904

SOT23/SMD

1

3 2

C121
1uF

R256

0/NC

74LVC00A/NC

U29

1
2
3
4
5
6
7 8

9

10

11

12

13

14

U25

IDTQS3VH257

TSSOP16/SMD

I1B

6

I0A

2

I1A

3

S

1

YA

4

I0B

5

YB

7

GND

8

I0D

14

E#

15

I1D

13

I0C

11

YD

12

VCC

16

I1C

10

YC

9

R252
10k/NC

U33

74LVC244A

GND

10

VCC

20

1G

1

1A1

2

1A2

4

1A3

6

1A4

8

2G

19

2A1

11

2A2

13

2A3

15

2A4

17

1Y1

18

1Y2

16

1Y3

14

1Y4

12

2Y1

9

2Y2

7

2Y3

5

2Y4

3

J18

CON50

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

JP3

3x1

JP3/DIP/P2.54

123

Q11

2N3904

SOT23/SMD

1

3 2

U31

74LVC244A

GND

10

VCC

20

1G

1

1A1

2

1A2

4

1A3

6

1A4

8

2G

19

2A1

11

2A2

13

2A3

15

2A4

17

1Y1

18

1Y2

16

1Y3

14

1Y4

12

2Y1

9

2Y2

7

2Y3

5

2Y4

3

R247

10k

U30

74LVC244A

GND

10

VCC

20

1G

1

1A1

2

1A2

4

1A3

6

1A4

8

2G

19

2A1

11

2A2

13

2A3

15

2A4

17

1Y1

18

1Y2

16

1Y3

14

1Y4

12

2Y1

9

2Y2

7

2Y3

5

2Y4

3

R244
10k

U24

IRF7314

SOIC8/SMD

S1

1

G1

2

S2

3

G2

4

D2

5

D2

6

D1

7

D1

8

C120
1uF

R251
0

74HCT04A/NC

U28

1
2
3
4
5
6
7 8

9

10

11

12

13

14

L46
FB/NC

R255

10k

CB133

0.1uF

R338
0/NC

C135
56pF

Q9
2N3904

SOT23/SMD

1

3 2

+

CE77

220uF/16v

L47
FB

U32

74LVC244A

GND

10

VCC

20

1G

1

1A1

2

1A2

4

1A3

6

1A4

8

2G

19

2A1

11

2A2

13

2A3

15

2A4

17

1Y1

18

1Y2

16

1Y3

14

1Y4

12

2Y1

9

2Y2

7

2Y3

5

2Y4

3

R254
10k

R253
10k

R242
22k

R245

0

CB134

0.1uF

R246
10k

R250

0/NC

R243
22k

+

CE78

220uF/16v

R249
10k/NC

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

+12V

GND

RELAY_ON

VS_ON

5VSB

RELAY_ON

VS_ON

5VD

5VD PWM0

PWM0

ORO1
ORO3

ORO1

ORO3

ADIN4

ADIN4

5VSB

5VSB

VCC

+12V

DV33A

DV33A

DV33A

DV33A

+12V 1,7,10,13

PWM0 3,11

ORO1 3,10
ORO3 3,10

ADIN4 3

Title

Size Doc Number R e v

Date : Sheet o f

PDP interface

V1.2

A

14 15Wednesday, October 12, 2005

DEL ACD Net--------MTK

Change--------MTK

USE WHEN LG V6

USE WHEN LG V6

R340

4.7k

R357

10K

+

CE79
220uF/16v

C220UF16V/D6H11

Q15
2N3904

1

3 2

R354

10K

R343
10k

R260
1k

R360 0/NC

R294

4.7k/NC

R358 1k

Q13
2N3904

1

3 2

R288

10k/NC

R287

4.7k/NC

TP3

R257
1k

R356 0/NC

CN2

DIP7/P2.0

1
2
3
4
5
6
7

R262

1k

+

CE80
220uF/16v

C220UF16V/D6H11

Q12

2N3904

1

3 2

R289
10k/NC

R355 1k

Q16
2N3904

1

3 2

R259

1k

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Title

Size Doc Number R e v

Date : Sheet o f

V1.2

A

15 15Wednesday, October 12, 2005

History

From V0.1 To V1.2 change item:

1,Add R109-10K;R107-4.7K;C135-56pF;0603-R88,R91,R104,R106-0 .0805-R96,R99,R101-0

欧姆 欧姆

2,Reset IC 5V Supply;DVI AUDIO ADD CO增加NNECTOR J8.
3,ADIN4 CHANGE TO PWM0

1 2 3 4 5 6 7 8

A

B

C

D

8

7654321

D

C

B

A

Title

Number RevisionSize

D
Date: 21-Sep-2005 Sheet of
File: D:\

正在进行的项目\LCD TV\LCD TV.DdbDrawn By:

MUTEC

MUTEC

AUDPL

AUDPR

MUTE

AUDPL

AUSPL

MUTEC

AUSPR

+24V

AUDPR

1 2

R57

4K7

5%

12

C11

470NF

FILM

12

C17

390PF

NPO

PIN

1

NIN

2

AGND

3

EN4BS

5

VPP

6

SW

7

PGND

8

U3

ATA-120

D1

MBRS130LTR

1 2

R15 47K

5%

PIN

1

NIN

2

AGND

3

EN4BS

5

VPP

6

SW

7

PGND

8

U1

ATA-120

1 2

R63

10K

5%

1 2

R48 1k8

5%

C2

100U/35V

1 2

C32

1UF

X5R

C20
10UF

+

12

C23

1000UF/35V

1 2

C30

4.7nF

NPO

12

R36

10K

5%

1 2

R58

4K7

5%

1
2
3
4

J6

4x1 W/HOUSING

12

R23

10K

5%

+

1 2

C38

1000UF/25V

1
2
3
4

J1

4x1 W/HOUSING

1 2

R16

100K

5%

+

5

-

6

OUT

7

U5B

RC4558

1 2

R52 47K

5%

+

12

C25

100UF/25V

1 2

R64

47K

5%

1 2

R49 4K7

5%

12

R18

10K

5%

12

R1

82K

5%

12

C1

22pF NPO

R42

1k

D7

4.7V

1 2

R59

4K7

5%

12

C45

1n

1 2

C9

1UF

X5R

C34

NS

1 2

R2

100K

5%

12

C5

4.7uF

X5R

C24

22pF

C12

100NF

1 2

C31

1UF

X5R

1 2

R65

47K

5%

12

C27

4.7uF

X5R

1 2

C3

1UF

X5R

1 2

R50 4K7

5%

1 2

R54 10K

5%

12

C7

1UF

X7R

12

C46

1n

12

R7

10K

5%

1 2

L5 10uH

12

R37

10K

5%

1 2

R12

4K7
5%

+

12

C10

100UF/25V

1 2

R17

100K

5%

1 2

R60

100K

5%

C41

22pF

1 2

C35

100NF

X7R

1 2

R4

100K

5%

+

3

-

2

OUT

1

U5A

RC4558

1 2

R44

0

5%

12

C21

22pF NPO

+

12

C42

100UF/25V

12

C47

1n

C43

10U/16V

+

12

C4

100UF/25V

12

R8

10

5%

1 2

R51 4K7

5%

1 2

C16

100NF

X7R

1 2

R55 10K

5%

+

5

-

6

OUT

7

U2B

RC4558

12

R22

10

5%

12

R3

10K

5%

1 2

C8

4.7nF

NPO

12

R11

10K

5%

C14

22UF/16V

1 2

C28

100NF

X7R

C19

22UF/16V

D3

MBRS130LTR

12

R40

10K

5%

1 2

C6

100NF

X7R

1 2

R61

47K

5%

D2

6.2V

12

C48

1n

C44

22U/16V

12

R25

10K

5%

1 2

L6 10uH

1 2

C49

22P

12

R9

10K

5%

12

R24

3K

5%

12

R6

10

5%

+

3

-

2

OUT

1

U2A

RC4558

C40
10UF

12

R10

10K

5%

C22

22U/16V

1 2

C37

1UF

X5R

12

R14

82K

5%

1 2

R56

1k8

5%

1 2

R5

100K

5%

1 2

R39

4K75%

C15

NC

1 2

R53

100K

5%

1 2

R19

100K

5%

12

C13

100N

1 2

C50

22P

12

R21

10K

5%

1 2

R62

10K

5%

C26

10U/16V

12

C36

390PF

NPO

12

R20

10

5%

12

C29

1UF

X7R

+

1 2

C39

1000UF/25V

12

R41

10K

5%

1

1

2

2

J8

NS

12

C33

470NF

FILM

1 2

R38

47K

5%

D4

6.2V

AGND

AGND

VCC

+24V

+24V

+24V

AGND

AGND

AGND AGND

AGND

+24V

AGND

+24V

AGND

+24V

A

Audio Input

2

2

3

3

4

4

5

5

9

9

8

8

7

7

6

6

NC

1

M4

GND HOLE

2

2

3

3

4

4

5

5

9

9

8

8

7

7

6

6

NC

1

M3

GND HOLE

AF1_IN

AF1

AF1

TU_12V

TU_VCC

AF1_OUT

SIF1 SIF1_OUT

SIF1_IN SIF1_OUT

1 2

1R14 0

1 2

1R16 0/NC

+

1 2

CE7

33uF/16V

1 2

1R15 0

AF1_OUT

SIF1_OUT TU_12V

TU_VCC

AF1_IN

VCC

SIF1_IN TU_CVBS

TU_SDA

TU_SCL

GND1

TH1

GND2

TH2

VS_TUNER3SCL4AS6SDA52nd SIF OUT11AF-R9AF-L10CVBS12GND3

TH3

GND4

TH4

AF /MPX14VS_IF

13

NC1NC2NC7NC

8

TU1

FQ1236-MK3

GNDS

GNDS

GNDS

FQ1236 / : NTSC TV

IF

ADDRESS

TUNER

TUNER1 IN

TUNER1

C2 86

SIF1

SIF1_IN

12

1R11

0R

12

1L3

1.5uH/1.2uH

1 2

1C5 1NF(22P/27P)

1 2

1L2 3.3UH(47uH/22uH)

1 2

1C4 10nF

+

12

CE6

10uF/25v

1 2

1C6 10nF

12

1R12

82R

1 2

1C1 10nF

1 2

1R9 0

1 2

1C8

820pF/560pF

1 2

1C7

820pF/560pF

12

1R8

1k

12

1R10

220

12

1L4

1.5uH/1.2uH

12

1R7

1.8K

1 2

1C9

NC

GND V

SIF_12V

GND VGND VGND V

GND V GND V

GND VGND V

TUNER1 SIF1 BPF
NTSC 4.5MHz PAL 6MHz

SIF_12VTU_12V

12

CB4

0.1uF

12

CB5

0.1uF

1 2

1L5 FB

1 2

1L6 FB

+

12

CE8
100uF/16V

+

12

CE3

100uF/16V

12

CB6

0.1uF

12

CB3

0.1uF

+

12

CE9
220uF/16V

12

CB7

0.1uF

+

12

CE4

100uF/16V

+

12

CE5

100uF/16V

TU_VCC

TU_12V SIF_12V

VCC

GNDS

GNDS

GNDS

GNDS

GND V

GND V

VIDEO GROUNDAUDIO GROUND

SDA

SCL

AF1_OUT

SIF1_OUT

TV

TV_GND

TV_GND

TVTU_CVBS

12

FB1

0

1 2

1R2 0

1 2

1R4 0

12

FB2

0

1
2
3
4
5
6
7
8
9
10
11
12

1J1

CON12

12

1R3

56

1 2

1R1

18

GNDS

TU_VCC

GNDS

TU_12V

AV , TUNER I/O

2

2

3

3

4

4

5

5

9

9

8

8

7

7

6

6

NC

1

M2

GND HOLE

2

2

3

3

4

4

5

5

9

9

8

8

7

7

6

6

NC

1

M1

GND HOLE

GNDSGNDS

TU_SDA

TU_SCL

1 2

1C2

47pF

1 2

1R5 100

1 2

1R6

100

1 2

1C3

47pF

SCL

SDA

Q5
2N3904

Q6
2N3904

Q2
2N3904

1Q3
2N3904

12

R34

1K

5%

1 2

R35

1K

5%

12

C60

10UF

X5R

12

C59

10UF
X5R

12

R29

1K

5%

MUTE

Q3

2N3904

AGND

12

R13

47K

5%

12

R26

47K

5%

Q7
1015

Q4
1015

Q1
2N3906

R27
1K

LMUTE

AGND

R28
1k

R30

10k

+

12

C18

NC

+

12

C51

220UF/25V

D5

NC

D6

1N4148

D8

1N4148

D9

1N4148

MUTEB

AGND

AGND

R43

4K7

LOUT

ROUT

AGND

AGND

LOUT

ROUT

12

R66

4K7
5%

12

R67

4K7
5%

C541nC55

1n

C521nC53

1n

12

R46

4K7
5%

12

R45

4K7
5%

12

R47

1K8
5%

12

R33

1K8
5%

VIDEO OUT
LMUTE

AGND
AUSPL
AUSPR

1
2
3
4
5
6
7

J11

CON7

VIDEO OUT

LOUT

ROUT

K1

G6A-234P

D10

1N4148

+24V

Q8
2N3904

12

R32
0R
5%

1 2

R31

3K3 5%

1 2

C56
100NF
X7R

PMUTE

LOUT

ROUT

LOUT

ROUT

INTL

INTR

INTL

INTR

EXTL

EXTR

1
2
3
4
5

J2

CON5

PGND

EXTR
PGND

EXTL

INT: 0
EXT: 1

12

R68
NC/0R
5%

1
2
3
4
5
6

J5

CON6

PMUTE

1 2

BL1

600 OHM

D11 SR240 +24V

+

12

C57

1000UF/35V

1 2

L1

2mH

1
2
3

J7

CON3

1 2

R70

0R/NC

5%

1
2
3
4
5
6

J3

CON6

9V

TU_12V

C61
100n

C63
100U/16V

Q9
7805

C62
330U/16V

C58
100n

9V TU_VCC

D13

1N4001
D12

1N4001

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

DV33

+5V

+12V

VOR[0..7]
VOG[0..7]
VOB[0..7]
VOPCLK
VOHSYNC
VOVSYNC
VODE

U2TX

U2RX

U0RX

U0TX

AO1MCLK
AO1LRCK
AO1BCK

REQUEST#
READY#

ORESET#

ASPDIF

ASPDIF

ASPDIF

AO1SDATA0

AUD_CTRL

AO1LRCK

AO1SDATA0

AO1BCK
AO1MCLK

AUD_CTRL

VOR1

VOG3

VOR3

VOB4

VOG2

VOG7

VOB5

U0RX

VOB7

VOB1

U2TX

VOR4

VOG1

READY#

VOG6

REQUEST#

GND

VOB0

VOB3

VOR7

VOG0

VOB6

ORESET#

U2RX

VOB2

U0TX

VOR0

VOR5

VOG4

VOR6

VOG5

VOR2

VODE
VOPCLK

VOVSYNC

VOHSYNC

AO1MCLK

AO1SDATA0

AO1BCK
AO1LRCK

+5V

+12V

+5V

DV33

DV33

DV332,5,6,8

GND2,3,4,5,6,7,8

+5V2,6

+12V2

VOR[0..7]5
VOG[0..7]5
VOB[0..7]5
VOPCLK5
VOHSYNC5,8
VOVSYNC5,8
VODE5

U2TX5,8
U2RX5,8

U0RX5,8
U0TX5,8

AO1MCLK5

AO1BCK5

AO1LRCK5

AO1SDATA05

REQUEST#5
READY#5

ORESET#4,5,8

ASPDIF5

ASPDIF5

AUD_CTRL5

Title

POWER

Size

Document Number

Rev

Date: Sheet

of

Rev DATEP#History

RA-V1 INITIAL VERSIO N 2005/06/15

DEVICETYPENAME

POWER +12V
POWER +5V

POWER +5V
POWER +3V3
POWER +1V8
POWER +3V3
POWER +3V3
POWER +2V5
POWER +1V2

+12V
+5V

+5V_tuner
DV33_DM
DV18
DV33
AV33
DV25
DV12

POWER SUPPLY
POWER SUPPLY

TUNER POWER
MT5111 POWER
MT5111 POWER
MT5351 POWER
MT5351 ANALOG POWER
MT5351 DDR POWER
MT5351 POWER

GLOBAL SIGNAL

01. INDEX AND INTERFACE

02. POWER

03. TUNER

04. MT5111 ASIC

05. MT5351 ASIC

06. MT5351 PERIPHERAL

07. DDR MEMORY

08. NOR FLASH / JTAG / UART

GND GROUND GROUND

MT5111 / MT5351 REFERENCE DESIGN - 4 LAYERS

MT5351RA-V2

NS : NON-STUFF

DIGITAL VIDEO OUTPUT

UART (RS232)

DIGITAL AUDIO INTERFACE

SPDIF CIRCUIT

RA-V2 ADDED AUDIO SWITCH / REFINE POWER CIRCUIT 2005/07/14

POWER INPUT FROM MAIN BOARD

DIGITAL OUTPUT

+3.3V

RN3

33x4 RN0603/SMD

7 8
5 6
3 4
1 2

R2 75

CB2

0.1uF

C0603/SMD

CB142

0.1uF

C0603/SMD

RN10

33x4 RN0603/SMD

7 8
5 6
3 4
1 2

RN8

33x4 RN0603/SMD

7 8
5 6
3 4
1 2

L2 FB

BEAD/SMD/1206

RN6

33x4 RN0603/SMD

7 8
5 6
3 4
1 2

CB1

0.1uF

C0603/SMD

FB1

FB

BEAD/SMD/0603

R3 75

R4

33

R0603/SMD

R50 75

RN7

33x4 RN0603/SMD

7 8
5 6
3 4
1 2

RN9

33x4 RN0603/SMD

7 8
5 6
3 4
1 2

RN5

33x4 RN0603/SMD

7 8
5 6
3 4
1 2

J1

8x1 W/HOUSING

DIP8/W/H/P2.54

1
2
3
4
5
6
7
8

R49 75

RN4

33x4 RN0603/SMD

7 8
5 6
3 4
1 2

U1

NC/IDTQS3VH257

TSSOP16/P0.65/SMD

IA0

2

IB0

5

IC0

11

ID0

14

IA1

3

IB1

6

IC1

10

ID113GND

8

VCC

16

OE

15

S1YA

4

YB

7

YC

9

YD

12

+

CE2
220uF/16v

C220UF16V/D6H11

+

CE1
220uF/16v

C220UF16V/D6H11

RN1

33x4 RN0603/SMD

7 8
5 6
3 4
1 2

P1
S/PDIF OUT

RCA/SPDIF/5P/DIP

G

1

VCC

2

IN

3

K1

4

K2

5

6

6

G

7

8

8

9

9

BOTTOM

HA1

HEADER 50 SMD0.5 BOTTOM

H50S/P0.5

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

L19 FB

L1 FB

BEAD/SMD/1206

R1

4.7K

R0603/SMD

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

GND

+5V

AV33

DV33

DV25
DV12

+5V_TUNER
DV33_DM
DV18

+12V

DV25

AV33

+5V DV25

DV33 DV12

+5V DV33_DM

DV33_DM

DV18

+5V_TUNER

+12V

DV33

+5V DV33

+5V_TUNER+5V

+5V

GND1,3,4,5,6,7,8

+5V1,6

AV335,6

DV331,5,6,8

DV255,6,7
DV125,6

+5V_TUNER3,4
DV33_DM4
DV184

+12V1

Title

Size

Document Number

Rev

Date: Sheet

of

MT5351RA-V2

1

Custom

28Monday, September 26, 2005

POWER

TwinSon Chan

GLOBAL SIGNAL

POWER SUPPLY +2V5 FOR MT5351 AND DDR

1.25 x (1+0/100) = 1.25V

POWER SUPPLY +1V2 FO R MT5351

1.25 x (1+100/100) = 2.5V

POWER SUPPLY +3V3 FOR MT5351 (ANALOG)

1.25 x (1+180/110) = 3.3V

POWER SUPPLY +3V3 FO R MT5111

1.25 x (1+120/270) = 1.8V

POWER SUPPLY +1V8 FO R MT5111

POWER SUPPLY +5V FOR TUNER

1.25 x (1+180/110) = 3.3V

POWER SUPPLY +3V3 FO R MT5351

ADD

9V

Compatible With U6

CB150
10uF

C0805/SMD

CB5

0.1uF

C0603/SMD

+

CE3
220uF/16v

C220UF16V/D6H11

R9
270

R0603/SMD

+

CE7
220uF/16v

C220UF16V/D6H11

+

CE13
220uF/16v

C220UF16V/D6H11

+

CE9
220uF/16v

C220UF16V/D6H11

R7
110

R0603/SMD

+

CE30
470uF/16v/NC

C220UF16V/D6H11

R10
100

R0603/SMD

R5
110

R0603/SMD

+

CE10
220uF/16v

C220UF16V/D6H11

U5

AZ1117/adj

SOT223/SMD

ADJ/GND

1

OUT2IN

3

+

CE6
220uF/16v

C220UF16V/D6H11

L4

FB

BEAD/SMD/0805

U4

AZ1117/adj

SOT223/SMD

ADJ/GND

1

OUT2IN

3

CB9

0.1uF

C0603/SMD

U6

AZ1117/adj

SOT223/SMD

ADJ/GND

1

OUT2IN

3

U2

AZ1117/adj

SOT223/SMD

ADJ/GND

1

OUT2IN

3

+

CE16
220uF/16v

C220UF16V/D6H11

CB6

0.1uF

C0603/SMD

CB146

0.1uF/NC

C0603/SMD

L33FB4.7UH

U21

MP2105

IN

4

GND

2

EN

1

SW

3

FB

5

U3

AP1084/TO220-DIP/5V

TO220/DIP

ADJ

1

IN3OUT

2

VOUT

4

L6

FB

BEAD/SMD/0805

+

CE31
470uF/16v/NC

C220UF16V/D6H11

R14
0

R0603/SMD

R11
120

R0603/SMD

+

CE5
220uF/16v

C220UF16V/D6H11

L17FB

BEAD/SMD/0805/NC

L9

FB

BEAD/SMD/0805

CB151
10uF

C0805/SMD

R6
180

R0603/SMD

+

CE8
220uF/16v

C220UF16V/D6H11

L32

FB

BEAD/SMD/1206/NC

+

CE12
220uF/16v

C220UF16V/D6H11

CB10

0.1uF

C0603/SMD

R112
499k

R0603/SMD

+

CE14
220uF/16v

C220UF16V/D6H11

CB15

0.1uF

C0603/SMD

+

CE4
220uF/16v

C220UF16V/D6H11

R8
180

R0603/SMD

R12
100

R0603/SMD

CB147

0.1uF/NC

C0603/SMD

CB16

0.1uF

C0603/SMD

CB3

0.1uF

C0603/SMD

CB12

0.1uF

C0603/SMD

CB7

0.1uF

C0603/SMD

R113
249k

R0603/SMD

L8

FB

BEAD/SMD/0805

L18

FB

BEAD/SMD/0805/nc

+

CE15
220uF/16v

C220UF16V/D6H11

CB4

0.1uF

C0603/SMD

L7

FB

BEAD/SMD/0805

L5

FB

BEAD/SMD/0805

CB13

0.1uF

C0603/SMD

R13
100

R0603/SMD

L3

FB

BEAD/SMD/0805

CB8

0.1uF

C0603/SMD

U7

AZ1117/adj

SOT223/SMD

ADJ/GND

1

OUT2IN

3

CB14

0.1uF

C0603/SMD

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

GND

+5V_TUNER

RF_AGC

2nd_IF-

2nd_IF+

TUNER_SDAO

IF_AGC

RF_AGC
IF_AGC

2nd_IF-

2nd_IF+

TUNER_SCLO

TUNER_SCLO
TUNER_SDAO

+5V_TUNER

+5V_TUNER

+5V_TUNER

+5V_TUNER

GND1,2,4,5,6,7,8

+5V_TUNER2,4

RF_AGC4
IF_AGC4

2nd_IF-4

2nd_IF+4

TUNER_SCLO4
TUNER_SDAO4

Title

Size

Document Number

Rev

Date: Sheet

of

MT5351RA-V2

1

Custom

38Monday, September 26, 2005

TUNER

TwinSon Chan

GLOBAL SIGNAL

TUNER INTERFACE

ROUTE SYMMETRICALLY

IF SAW FILTER AND AMPLIFIER

R15
10K

R0603/SMD

R19 100

R0603/SMD

C6
1uF

C0603/SMD

L10

FB

BEAD/SMD/0805

CB18

0.1uF

C0603/SMD

C7
1uF

C0603/SMD

L12
NS

L/IND/SMD/0805

+

CE18
10uF/16v

C10UF16V/D5H11

R22
510/1%

R0603/SMD

R17 NS

R0603/SMD

R21
510/1%

R0603/SMD

R18 100

R0603/SMD

R16
10K

R0603/SMD

U9

PORT SAW FILTER X6965D SIP5K

SIP5K/DIP

IN+

1

IN-

2

GND

3

OUT+

5

OUT-

4

+

CE17
10uF/16v

C10UF16V/D5H11

U8

PORT TUNER TD1336/FGHP

GND

TH1

GND

TH2

GND

TH3

GND

TH4

Outdoor PS

1

VS_splitter_+5V

2

OOB_OP

3

NC

4

RF_AGC

5

NC

6

AS

7

SCL

8

SDA

9

NC

10

VS_Tuner_+5V

11

Broad_IF_OP

12

IF_AGC

13

Narrow_IF_OP1

14

Narrow_IF_OP2

15

C4
1nF

C0603/SMD

C5

0.1uF

C0603/SMD

R23

4.7K

R0603/SMD

U10

upc3218

TSSOP8/SMD

VCC_+5V

1

IN_1

2

IN_2

3

VAGC4GND

5

OUT_2

6

OUT_1

7

GND

8

CB17

0.1uF

C0603/SMD

L11

FB

BEAD/SMD/0805

R20

4.7K

R0603/SMD

C3
10nF

C0603/SMD

C8
10nF

C0603/SMD

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

DV18

GND

DV33_DM

RF_AGC
IF_AGC

2nd_IF-

2nd_IF+

TS1ERROR

TS1SYNC
TS1VALID

TS1DATA[0..7]

OSCL_MST

OSDA_MST

TS1CLK

+5V_TUNER

TUNER_SDAO

TUNER_SCLO

TUNER_SDA1

TUNER_SCL1

ORESET#

TUNER_SCLO
TUNER_SDAO

TS1DATA7

TS1DATA7

TS1DATA7_T

TS1SYNC

TS1CLK#

TS1CLK TS1CLK#

TS1DATA7_T TS1ERROR

DVDD33

DVDD18

DVDD33

XTAL2

ORESET#

TS1DATA0

TS1DATA6

AVDD33

DVDD18

AVDD33

VCMEXT

DVDD33

IF_AGCIF_AGCIF_AGC

TS1SYNC

ADVDD33_1

REFBOT

DVDD18

AVDD33

TS1DATA7_T

DVDD33

DVDD18

TS1DATA2

TS1DATA1

2nd_IF+

REFTOP

MT5111_IF_AGC

DVDD33

TS1ERROR

OSDA_MST

AVDD33

AVDD33

TUNER_SDA

DVDD18

AVDD3

TS1DATA4

TS1VALID

AVDD33

TUNER_SCL

RF_AGCRF_AGCRF_AGC

AVDD33

DVDD18

MT5111_IF_AGC

XTAL1

DVDD18

DVDD33

AVDD5

TS1CLK

MT5111_RF_AGC

DVDD33

TS1DATA3

MT5111_RF_AGC

TS1CLK

TS1DATA5

2nd_IF-

ADVDD33_2

IF_AGCIF_AGCIF_AGC

OSCL_MST

TUNER_SDA1

TUNER_SCL

TUNER_SDA

TUNER_SCL1

DVDD33

DV18

DV33_DM

AVDD33DV33_DM AVDD33

DVDD18 DVDD18

AVDD33 AVDD3

AVDD33 AVDD5

AVDD33 AD VDD33_1

AVDD33 AD VDD33_2

DVDD33

DV33_DM

DV33_DM

DVDD18

DVDD33

DV33_DM+5V_TUNER

DV182

GND1,2,3,5,6,7,8

DV33_DM2

RF_AGC3
IF_AGC3

2nd_IF-3

2nd_IF+3

TS1ERROR5

TS1SYNC5
TS1VALID5

TS1DATA[0..7]5

OSDA_MST6
OSCL_MST6

TS1CLK5

+5V_TUNER2,3

ORESET#1, 5,8

TUNER_SCLO3
TUNER_SDAO3

Title

Size

Document Number

Rev

Date: Sheet

of

MT5351RA-V2

1

C

48Monday, September 26, 2005

MT5111 ASIC

TwinSon Chan

GLOBAL SIGNAL

Digital 3.3V Byp ass Caps

Analog 3.3V Bypass Caps

Digital 1.8V Byp ass Caps

TUNER INTERFACE

TS INPUT

MODIFIED IN V3

Close to MT5111

SIF LEVEL SHIFTER

U20B

74HC00

SOP14/SMD

4

5

6

147

R25 4.7K

R0603/SMD/NC

C10
47nF

C0603/SMD

U12B

74HC74

SOP14/SMD

D

12

CLK

11

Q

9

Q

8

VCC

14

PR

10

GND

7

CL

13

CB26

0.1uF

C0603/SMD

L13
NS/220nH

L/IND/SMD/0805

CB35

0.1uF

C0603/SMD

CB25

0.1uF

C0603/SMD

C15 0 .1uF

C0603/SMD

U20C

74HC00

SOP14/SMD

9

10

8

147

R26
1K

R0603/SMD

FB5

FB

BEAD/SMD/0603

L15
FB

BEAD/SMD/0805

CB41

0.1uF

C0603/SMD

C18

0.1uF

C0603/SMD

C16
10uF/10v

C0805/SMD

C17 0 .1uF

C0603/SMD

+

CE20
10uF/16v

C10UF16V/D5H11

CB34

0.1uF

C0603/SMD

CB148

0.1uF

C0603/SMD

C20
18pF

C0603/SMD

CB38

0.1uF

C0603/SMD

CB36

0.1uF

C0603/SMD

R31

4.7K

R0603/SMD

C13
1uF

C0603/SMD

QF2

2N7002

N-MOSFET

2

13

RN12

33x4

RN0603/SMD

1 2
3 4
5 6
7 8

CB32

0.1uF

C0603/SMD

CB24

0.1uF

C0603/SMD

C11
1uF

C0603/SMD

CB23

0.1uF

C0603/SMD

RN13
33x4

RN0603/SMD

1 2

3 4

5 6

7 8

U20D

74HC00

SOP14/SMD

12

13

11

147

R32

4.7K

R0603/SMD

CB30

0.1uF

C0603/SMD

R34
10

R0603/SMD

FB6

FB

BEAD/SMD/0603

CB22

0.1uF

C0603/SMD

CB149

0.1uF

C0603/SMD

QF1

2N7002

N-MOSFET

2

13

CB31

0.1uF

C0603/SMD

CB83

0.1uF

C0603/SMD

FB3

FB

BEAD/SMD/0603

+

CE21
10uF/16v

C10UF16V/D5H11

C9
47nF

C0603/SMD

CB39

0.1uF

C0603/SMD

CB27

0.1uF

C0603/SMD

CB19

0.1uF

C0603/SMD

R29
10K

R0603/SMD

R27 4.7K

R0603/SMD

C12
NS/47pF

C0603/SMD

FB2

FB

BEAD/SMD/0603

C14

0.1uF

C0603/SMD

CB21

0.1uF

C0603/SMD

CB28

0.1uF

C0603/SMD

L14
FB

BEAD/SMD/0805

CB20

0.1uF

C0603/SMD

RN11

33x4

RN0603/SMD

1 2
3 4
5 6
7 8

U20A

74HC00

SOP14/SMD

1

2

3

147

R30
10K

R0603/SMD

R33
10

R0603/SMD

U12A

74HC74

SOP14/SMD

D

2

CLK

3

Q

5

Q

6

VCC

14

PR

4

GND

7

CL

1

MT5111AE

100-LQFP

U11
MT5111AE

NC1NC2AVDD3NC4NC5NC6AVSS7NC8NC9AVDD10AVSS11AVDD12NC13NC14ADVDD3315DGND16DVDD3317DVDD1818DGND19NC20NC21TS_DATA722TS_DATA623TS_DATA524TS_DATA4

25

DVDD33

26

DGND

27

TS_DATA3

28

TS_DATA2

29

DVDD18

30

DGND

31

TS_DATA1

32

TS_DATA0

33

TS_SYNC

34

DVDD33

35

DGND

36

TS_CLK

37

TS_VAL

38

TS_ERR

39

DVDD18

40

DGND

41

DVDD33

42

DGND33

43

HOST_DATA

44

DVDD18

45

DGND

46

HOST_CLK

47

RESET_

48

NC

49

NC

50

DVDD18

75

DGND

74

RF_AGC

73

IF_AGC

72

DGND

71

DVDD33

70

TUNER_CLK

69

TUNER_DATA

68

SA167SA0

66

DGND

65

DVDD18

64

DGND

63

ANTIF

62

DGND

61

DVDD33

60

NC59NC58NC

57

DGND

56

DVDD18

55

NC54NC

53

DVDD33

52

DGND

51

AVSS

100

AVDD

99

AVSS

98

XTAL1

97

XTAL2

96

AVSS

95

AVSS

94

AVDD

93

AVDD

92

AVDD

91

AVDD18

90

AVSS

89

REFTOP

88

VCMEXT

87

REFBOT

86

AVSS

85

NC

84

AVDD

83

IN+

82

IN-

81

AVDD

80

AVSS

79

NC

78

NC

77

ADVDD33

76

R24
1K

R0603/SMD

L16
FB

BEAD/SMD/0805

R111
NS/0

R0603/SMD

CB37

0.1uF

C0603/SMD

CB33

0.1uF

C0603/SMD

Y1

25MHz

CRYS/DIP/SMD

FB4

FB

BEAD/SMD/0603

C19
18pF

C0603/SMD

CB29

0.1uF

C0603/SMD

R28
1M

R0603/SMD

CB40

0.1uF

C0603/SMD

+

CE19
10uF/16v

C10UF16V/D5H11

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

JTRST#
JTDI
JTMS
JTCK
JRTCK
JTDO

READY#

DV12

POWE#

POCE0#
POOE0#

RDQ[0..31]
RDQS[0..3]
RDQM[0..3]
RA[0..13]

RCLK0#
RCS#
RRAS#
RCAS#
RWE#
RCKE

RBA[0..1]

RCLK1
RCLK1#

RCLK0

PDA[0..22]
PDD[0..7]

U2TX
U2RX

U1RX
U1TX

U0RX
U0TX

AO1MCLK
AO1LRCK
AO1BCK

ASPDIF

OSCL0

OSDA0

DV25

DV33

RVREF

OXTALI
OXTALO

DVDDKP

FS

CAPVPLL

RVREF

CAPVGND

AVDDRKP

AVDD_APLL0

AVDD_APLL1

AVDDBGKP

AVDD_DMPLL1
AVDD_VPLL

AVDDYKP

AVDD_DMPLL0

APLLCAP1
APLLCAP0

ATP1
ATP2

OPWM0

REQUEST#

ORESET#

VCXO0

TS1CLK

TS1ERROR

TS1SYNC
TS1VALID

TS1DATA[0..7]

VOR[0..7]
VOG[0..7]
VOB[0..7]
VOPCLK
VOHSYNC
VOVSYNC
VODE

AO1SDATA0

U2CTS

OIRI

AUD_CTRL

AVDD_VPLL

RA7

RA2

RDQM0

JTDO

VOR7

G

R

TS1DATA0

PDA1

AVDDYKP

RCLK1

RCKE

RRAS#

RCAS#

RDQ13

VOB4

TS1ERROR

PDA18

PDA14

PDA2

RDQM3

RDQ19

RA13

RDQ1

DONE

OIRI

VOPCLK

VOG7

VOB5

U2CTS

VCXO0

OPWM0

TS1DATA3

PDA22

OXTALO

RDQ30

RDQ20

RBA0

RDQ10

RCLK0

VOR0

VOG1

AO1BCK

U1RX

U0TX

OSCL0

TS1DATA7

TS1DATA4

PDA9

AVDD_APLL1

RA6

VOR6

PDA0

AVDDBGKP

RDQM2

RA11

RDQ6

JRTCK

VOB3

ASPDIF

OSDA0

PDD3

TS1DATA1

PDA17

AVDD_APLL0

RDQ18

RA12

RWE#

RDQ0

VOG6

PDD0

TS1DATA2

PDA21

RDQ29

RDQ25

RA5

RDQ9

VODE

VOG0

POCE0#

PDD1

APLLCAP1

TS1DATA6

PDA8

PDA6

PDA5

RDQ26

RDQ23

RDQ16

RA0

RCS#

VOR5

AO1LRCK

U1TX

RA9

RA4

RA1

RDQS1

RDQS0

RDQ5

VOR1

VOB2

AO1SDATA0

PDD2

APLLCAP0

FS

PDA16

GND

RDQ17

RDQ15

JTCK

JTMS

JTDI

VOR2

VOG5

AO1MCLK

U2RX

VCXO1

PDA20

CAPVGND

RDQ28

RDQ24

RDQ8

RDQ3

RCLK0#

JTRST#

VOVSYNC

VOB7

TS1DATA5

PDA7

PDA4

DVDDKP

RA10

RDQ12

VOR4

VOG3

PDD6

TS1VALID

PDA13

AVDD_DMPLL1

OXTALI

ATP1

RCLK1#

RA8

RA3

RDQM1

RDQ7

RDQ4

ORESET#

VOB1

POOE0#

POWE#

PDD7

PDD4

TS1CLK

AVDDRKP

AVDD_DMPLL0

RDQ14

READY#

REQUEST#

VOG4

CAPVPLL

B

PDA19

PDA15

RDQ27

RDQS3

RDQ2

VOHSYNC

VOB6

AUD_CTRL

U2TX

U0RX

TS1SYNC

PDA11

PDA3

ATP2

RDQ31

RDQS2

RDQ21

RBA1

RDQ11

VOR3

VOG2

VOB0

TUNER_SW

PDD5

PDA12

PDA10

RDQ22

R
B
G

DV33

DV25

DV12

DV33

DV12

JTRST#8
JTDI8
JTMS8
JTCK8
JRTCK8
JTDO8

GND1,2,3,4,6,7,8

DV122,6

POCE0#8
POOE0#8
POWE#8

RDQ[0..31]7
RDQS[0..3]7
RDQM[0..3]7
RA[0..13]7

RCLK07
RCLK0#7
RCS#7
RRAS#7
RCAS#7
RWE#7
RCKE7

RBA[0..1]7

RCLK17
RCLK1#7

PDA[0..22]8
PDD[0..7]8

U2TX1,8
U2RX1,8

U1RX8
U1TX8

U0RX1,8
U0TX1,8

READY#1

AO1MCLK1

AO1BCK1

AO1LRCK1

AO1SDATA01

ASPDIF1

OPWM06

OSCL06

OSDA06

DV252,6,7

DV331,2,6,8

RVREF6

OXTALI6
OXTALO6

DVDDKP6

FS6

CAPVPLL6
CAPVGND6

AVDDRKP2,6

AVDD_APLL02,6

AVDD_APLL12,6

AVDDBGKP2,6

AVDD_DMPLL12,6
AVDD_VPLL2,6

AVDDYKP2,6

AVDD_DMPLL02,6

APLLCAP16
APLLCAP06

ATP16
ATP26

REQUEST#1

ORESET#1,4,8

VCXO06

TS1CLK4

TS1ERROR4

TS1SYNC4
TS1VALID4

TS1DATA[0..7]4

VOR[0..7]1
VOG[0..7]1
VOB[0..7]1
VOPCLK1
VOHSYNC1,8
VOVSYNC1,8
VODE1

U2CTS6

OIRI6

AUD_CTRL1

R8
B8
G8

Title

Size

Document Number

Rev

Date: Sheet

of

MT5351RA-V2

1

Custom

58Monday, September 26, 2005

MT5351 ASIC

TwinSon Chan

JTAG PORT

GLOBAL SIGNAL

DDR MEMORY

FLASH INTERFACE

UART (RS232)

AUDIO INTERFACE

ANALOG PART

TEST PURPOSE

TS INPUT

DIGITAL VIDEO OUTPUT

Add by Ada

R36
330

R0603/SMD

TP6
TUNER_SW

TP/SMD/D1.0

C118

0.1uF

C0603/SMD

TP5
IR

TP/SMD/D1.0

TP2
IOB_Y5

TP/SMD/D1.0

MT5351

U14

MT5351

BGA471/SMD

PDCD2#

A14

PDIOIS16#

A15

PDA0

B24

PDA1

A24

PDA2

D23

PDA3

C23

PDA4

B23

PDA5

A23

PDA6

D22

PDA7

C22

PDA8

B22

PDA9

A22

PDA10

D21

PDA11

C21

PDA12

B21

PDA13

A21

PDA14

D20

PDA15

C20

PDA16

B20

PDA17

A20

PDA18

D19

PDA19

C19

PDA20

B19

PDA21

A19

PDA22

D18

PDA23

C18

PDA24

B18

PDA25

A18

PDCE1#

D17

PDCE2#

C17

PDOE#

B17

PDIORD#

A17

PDIOWR#

D16

PDWE#

C16

PDIREQ#

B16

PDRESET

A16

PDWAIT#

D15

PDINPACK#

C15

PDREG#

B15

PDENPOD

B14

T0CLK

C14

T0SYNC

D14

T0VALID

A13

T0DATA0

B13

T0DATA1

C13

T0DATA2

D13

T0DATA3

A12

T0DATA4

B12

T0DATA5

C12

T0DATA6

D12

T0DATA7

A11

T1CLK

B11

T1SYNC

C11

T1VALID

D11

T1DATA0

A10

T1DATA1

B10

T1DATA2

C10

T1DATA3

D10

T1DATA4A9T1DATA5B9T1DATA6C9T1DATA7

D9

OPWM0

D8

ORTCVDD

D7

ORTCO

B8

ORTCI

A8

OPWM1

C8

ORTCVSS

C7

FS

A6

CIN_Y0

A7

IOR_Y6

B3

IOB_Y5

A3

IOG_Y4

C4

IOX_Y3B4IOY_Y2

A4

IOC_Y1

C5

CAPVPLL

D5

APLLCAP1D4APLLCAP0

E4

AGND

L11

AGND

L12

AGND

L13

AGND

M11

AGND

M12

AGND

M13

AGND

N11

AGND

N12

AGND

N13

PDD0

A27

PDD1

B26

PDD2

A26

PDD3

C25

PDD4

B25

PDD5

A25

PDD6

D24

PDD7

C24

PDCD1#

A28

CVDDM5CVDDN5CVDDU5CVDD

E10

CVDD

E19

CVDD

M24

CVDD

N24

CVDD

U24

CVDD

AE14

CVDD

AE15

IOVDD

P5

IOVDD

R1

IOVDD

R2

IOVDD

R3

IOVDD

R4

IOVDD

R5

IOVDD

T5

IOVDD

E11

IOVDD

E12

IOVDD

E13

IOVDD

E14

IOVDD

E15

IOVDD

E16

IOVDD

E17

IOVDD

E18

IOVDD

P24

IOVDD

R24

IOVDD

R25

IOVDD

R26

IOVDD

R27

IOVDD

R28

IOVDD

T24

POWE#

B27

POCE0#

B28

POOE0#

C26

POCE1#

C27

POOE1#

C28

POCE2#

D25

POOE2#

D26

OSDA0

E1

OSCL0

F4

OSDA1

E3

OSCL1

E2

U0TX

F3

U0RX

F2

U1TX

F1

U1RX

G4

U2TX

G3

U2RX

G2

U2CTS

G1

U2RTS

H4

AO1SDATA3

H3

AO1SDATA2

H2

AO1SDATA1

H1

AO1SDATA0

J4

AO1LRCK

J3

AO1BCK

J2

AO1MCLK

J1

AO2SDATA0

K1

AO2LRCK

K2

AO2BCK

K3

AO2MCLK

K4

ASPDIF

L3

ASPDIF2

L4

VOB0

L2

VOB1

L1

VOB2

M4

VOB3

M3

VOB4

M2

VOB5

M1

VOB6

N4

VOB7

N3

VOG0

N2

VOG1

N1

VOG2

P4

VOG3

P3

VOG4

P2

VOG5

P1

VOG6

T1

VOG7

T2

VOR0

T3

VOR1

T4

VOR2

U1

VOR3

U2

VOR4

U3

VOR5

U4

VOR6

V1

VOR7

V2

VOPCLK

V3

VOHSYNC

V4

VOVSYNC

W1

VODE

W2

JTRST#

W3

JTDI

W4

JTMS

Y1

JTCK

Y2

JRTCK

Y3

JTDO

Y4

GND

L14

GND

L15

GND

L16

GND

L17

GND

L18

GND

M14

GND

M15

GND

M16

GND

M17

GND

M18

GND

N14

GND

N15

GND

N16

GND

N17

GND

N18

GND

P11

GND

P12

GND

P13

GND

P14

GND

P15

GND

P16

GND

P17

GND

P18

GND

R11

GND

R12

GND

R13

GND

R14

GND

R15

GND

R16

GND

R17

GND

R18

PARB#

D27

PARE#

D28

PACE#

E25

PACLE

E26

PAALE

E27

PAWE#

E28

ELREQ

F25

ECLK

F26

ECNTL0

F27

ECNTL1

F28

EDATA0

G25

EDATA1

G26

EDATA2

G27

EDATA3

G28

EDATA4

H25

EDATA5

H26

EDATA6

H27

EDATA7

H28

ELPS

J25

ELINKON

J26

ORESET#

J27

OIRI

J28

OIRO

K25

ICS1#

K26

ICS0#

K27

IDA2

K28

IDA0

L25

IDA1

L26

IINTRQ

L27

IDMACK#

L28

IIORDY

M25

IDIOR#

M26

IDIOW#

M27

IDMARQ

M28

IDD15

N25

IDD0

N26

IDD14

N27

IDD1

N28

IDD13

P25

IDD2

P26

IDD12

P27

IDD3

P28

IDD11

T28

IDD4

T27

IDD10

T26

IDD5

T25

IDD9

U28

IDD6

U27

IDD8

U26

IDD7

U25

IRESET#

V28

DDETECT

V27

DCLK

V26

DCMD

V25

DDATA0

W28

DDATA1

W27

DDATA2

W26

DDATA3

W25

MDETECT

Y28

MCLK

Y27

MBS

Y26

MDATA0

Y25

MDATA1

AA28

MDATA2

AA27

MDATA3

AA26

STSCLK

AA25

STSDOUT

AB28

STSDIN

AB27

SPWRSEL

AB26

SDETECT

AB25

SCMDVCC

AC28

SRST

AC27

SCLK

AC26

SDATA

AC25

GND

T11

GND

T12

GND

T13

GND

T14

GND

T15

GND

T16

GND

T17

GND

T18

GND

U11

GND

U12

GND

U13

GND

U14

GND

U15

GND

U16

GND

U17

GND

U18

GND

V11

GND

V12

GND

V13

GND

V14

GND

V15

GND

V16

GND

V17

GND

V18

DVREF2

AE8

DVREF0

AE9

DVREF1

AE20

DVREF3

AE21

RDQ32

AA1

RDQ33

AA2

RDQ34

AA3

RDQ35

AB1

RDQ36

AB2

RDQ37

AB3

RDQ38

AC1

RDQ39

AC2

RDQS4

AC3

RDQM4

AD1

RDQM5

AD2

RDQS5

AD3

RDQ40

AE1

RDQ41

AE2

RDQ42

AE3

RDQ43

AF1

RDQ44

AF2

RDQ45

AF3

RDQ46

AG1

RDQ47

AG2

RCLK0

AH1

RCLK0#

AH2

RDQ0

AH3

RDQ1

AG3

RDQ2

AH4

RDQ3

AG4

RDQ4

AF4

RDQ5

AH5

RDQ6

AG5

RDQ7

AF5

RDQS0

AH6

RDQM0

AG6

RDQM1

AF6

RDQS1

AH7

RDQ8

AG7

RDQ9

AF7

RDQ10

AH8

RDQ11

AG8

RDQ12

AF8

RDQ13

AH9

RDQ14

AG9

RDQ15

AF9

RWE#

AH10

RCAS#

AG10

RRAS#

AF10

RCS#

AH11

RBA0

AG11

RBA1

AF11

RA10

AH12

RA0

AG12

RA1

AF12

RA2

AH13

RA3

AG13

RA4

AF13

RA5

AH14

RA6

AG14

RA7

AF14

RA8

AH15

RA9

AG15

RA11

AF15

RA12

AH16

RA13

AG16

RCKE

AF16

RDQ16

AH17

RDQ17

AG17

RDQ18

AF17

RDQ19

AH18

RDQ20

AG18

RDQ21

AF18

RDQ22

AH19

RDQ23

AG19

RDQS2

AF19

RDQM2

AH20

RDQM3

AG20

RDQS3

AF20

RDQ24

AH21

RDQ25

AG21

RDQ26

AF21

RDQ27

AH22

RDQ28

AG22

RDQ29

AF22

RDQ30

AH23

RDQ31

AG23

RCLK1

AF23

RCLK1#

AH24

RDQ48

AG24

RDQ49

AF24

RDQ50

AH25

RDQ51

AG25

RDQ52

AF25

RDQ53

AH26

RDQ54

AG26

RDQ55

AH27

RDQS6

AH28

RDQM6

AG28

RDQM7

AG27

RDQS7

AF28

RDQ56

AF27

RDQ57

AF26

RDQ58

AE28

RDQ59

AE27

RDQ60

AE26

RDQ61

AD28

RDQ62

AD27

RDQ63

AD26

RVDD

AA4

RVDD

AB4

RVDD

AC4

RVDD

AD4

RVDD

AE4

RVDD

AE5

RVDD

AE6

RVDD

AE7

RVDD

AE10

RVDD

AE11

RVDD

AE12

RVDD

AE13

RVDD

AE16

RVDD

AE17

RVDD

AE18

RVDD

AE19

RVDD

AE22

RVDD

AE23

RVDD

AE24

RVDD

AE25

RVDD

AD25

ATP1

D2

AVDD_APLL0C2AVDD_APLL1

B1

AVDD_VPLL

A1

AVDD_DMPLL0

C1

AVDDRKP

C3

AVDDYKP

B5

AVDDBGKP

B6

DACVREF

B7

DVDDKP

C6

OXTALO

A2

OXTALI

B2

NCA5NC

D6

AVDD_DMPLL1

D3

ATP2

D1

CAPVGND

E5

+

CE22
47uF/16v

C10UF16V/D5H11

TP4
VCXO1

TP/SMD/D1.0

TP3
IOG_Y4

TP/SMD/D1.0

R35

4.7K

R0603/SMD

LED1
LED DIP2.54

LED/DIP/P2.54

C116

0.1uF

C0603/SMD

TP1
IOR_Y6

TP/SMD/D1.0

C117

0.1uF

C0603/SMD

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

RVREF

GND

OXTALI
OXTALO

OPWM0

OXTALO

OXTALI

MEM_VREF

FS

APLLCAP1 APLLCAP0

DV25

DV33

DV12

AVDDBGKP

AVDDYKP

AVDDRKP

AVDD_DMPLL0

AVDD_DMPLL1

AVDD_VPLL

AVDD_APLL1

AVDD_APLL0

MEM_VREF RVREF

CAPVPLL

AV33

DVDDKP

FS

CAPVPLL

APLLCAP1
APLLCAP0

ATP1
ATP2

AVDDRKP

AVDD_APLL0

AVDD_APLL1

AVDDBGKP

AVDD_DMPLL1
AVDD_VPLL

AVDDYKP

AVDD_DMPLL0

CAPVGND

ATP1 ATP2

OSCL_MST

OSDA_MSTOSDA0

OSCL0

OSCL_MST
OSDA_MST

OPWM0

OSCL_MST

OSDA_MST

OSCL0

OSDA0

VCXO0

VCXO0

CAPVGND

OXTALI

U2CTS

U2CTS

OIRI

OIRI

+5V

DV25

DV12

DV33

DV33

DVDDKP

AV33

AV33 AV33

DV12

DV33

DV33

DV33

+5V

GND1,2,3,4,5,7,8

DV252,5,7

RVREF5

OXTALI5
OXTALO5

OPWM05

MEM_VREF7

DV331,2,5,8

DV122,5

AV332,5

DVDDKP5

FS5

CAPVPLL5

APLLCAP15
APLLCAP05

ATP15
ATP25

AVDDRKP2,5

AVDD_APLL02,5

AVDD_APLL12,5

AVDDBGKP2,5

AVDD_DMPLL12,5
AVDD_VPLL2,5

AVDDYKP2,5

AVDD_DMPLL02,5

CAPVGND5

OSDA_MST4
OSCL_MST4

OSCL05

OSDA05

VCXO05

U2CTS5

OIRI5

+5V1,2

Title

Size

Document Number

Rev

Date: Sheet

of

MT5351RA-V2

1

Custom

68Monday, September 26, 2005

MT5351 PERIPHERAL

TwinSon Chan

GLOBAL SIGNAL

LEFT SIDE BOTTOM SIDE

LEFT SIDE RIGHT SIDE

LEFT SIDE RIGHT SIDE TOP SIDE

TOP SIDE BOTTOM SIDE

ANALOG PART

MT5351 SYSTEM EEPROM

CB76

0.1uF

C0603/SMD

R45

4.7K

R0603/SMD

CB88

0.1uF

C0603/SMD

C140

0.1uF

C0603/SMD

C22
NS/20pF

C0603/SMD

C31
10uF/10v

C0805/SMD

C183

0.1uF

C0603/SMD

C185

0.1uF

C0603/SMD

CB44

4.7uF

C0603/SMD

CB50

4.7uF

C0603/SMD

CB72

0.1uF

C0603/SMD

R44
NS/10

R0603/SMD

CB75

0.1uF

C0603/SMD

C29
10uF/10v

C0805/SMD

C104

0.1uF

C0603/SMD

X1

VCXO FR270003

OSC/6P/SMD/7X5

CVIN

1

TRI-STATE

2

GND3OUT

4

NC

5

VDD

6

C184

0.1uF

C0603/SMD

JP1

JP2/DIP/P2.54

2x1

1 2

R38
NS/10M

R0603/SMD

C128

0.1uF

C0603/SMD

CB67

0.1uF

C0603/SMD

CB57

4.7uF

C0603/SMD

R40
NS/50

R0603/SMD

CB71

0.1uF

C0603/SMD

R39
NS/10

R0603/SMD

C25
1500pF

C0603/SMD

IR1

IR

NS/IR

123

CB74

0.1uF

C0603/SMD

R43
10

R0603/SMD

C129

0.1uF

C0603/SMD

R47
100

R0603/SMD

OSC1
NS/74.25MHz

OSC/SMD/A

VCC4OUT

3

GND2NC

1

FB7

FB

BEAD/SMD/0603

CB66

0.1uF

C0603/SMD

CB77

0.1uF

C0603/SMD

CB85

0.1uF

C0603/SMD

R46

4.7K

R0603/SMD

CB90

0.1uF

C0603/SMD

CB87

0.1uF

C0603/SMD

CB70

0.1uF

C0603/SMD

R41
NS/50

R0603/SMD

Y2

NS/27MHz

CRYS/DIP/SMD

CB53

0.1uF

C0603/SMD

C101
10uF/10v

C0805/SMD

C138

4.7uF

C0603/SMD

C26
10nF

C0603/SMD

CB48

0.1uF

C0603/SMD

CB52

0.1uF

C0603/SMD

U13

EEPROM 24C16

SOP8/SMD/NC

NC

1

NC

2

NC

3

GND4SDA

5

SCL

6

WP

7

VCC

8

R48
100

R0603/SMD

R42

8.2K

R0603/SMD

R37
NS/560

R0603/SMD

C28
47pF

C0603/SMD

CB54

0.1uF

C0603/SMD

CB69

0.1uF

C0603/SMD

CB81

0.1uF

C0603/SMD

CB89

0.1uF

C0603/SMD

C24
1500pF

C0603/SMD

CB45

0.1uF

C0603/SMD

C186

0.1uF

C0603/SMD

CB42

0.1uF

C0603/SMD

TP7
CAPVGND

TP/SMD/D1.0

CB78

4.7uF

C0603/SMD

CB82

0.1uF

C0603/SMD

CB51

0.1uF

C0603/SMD

CB79

0.1uF

C0603/SMD

CB65

0.1uF

C0603/SMD

CB68

0.1uF

C0603/SMD

C27
1nF

C0603/SMD

C179

0.1uF

C0603/SMD

CB49

0.1uF

C0603/SMD

CB86

0.1uF

C0603/SMD

C21
NS/20pF

C0603/SMD

CB46

0.1uF

C0603/SMD

CB47

4.7uF

C0603/SMD

CB73

0.1uF

C0603/SMD

CB43

0.1uF

C0603/SMD

CB80

0.1uF

C0603/SMD

C23

5600pF

C0603/SMD

L31

FB

L0603/SMD

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DV25

GND

MEM_VREF

MEM_ADDR6
MEM_ADDR5
MEM_ADDR4

MEM_DQ0

MEM_ADDR6
MEM_ADDR5
MEM_ADDR4

MEM_DQ16 MEM_DQ31

MEM_DQ17 MEM_DQ30
MEM_DQ18

MEM_DQ19
MEM_DQ20

MEM_DQ21
MEM_DQ22

MEM_DQ23

MEM_DQS2

MEM_WE#

MEM_DQM2

MEM_CAS#

MEM_CS#

MEM_RAS#

MEM_BA0
MEM_BA1
MEM_ADDR10
MEM_ADDR0
MEM_ADDR1
MEM_ADDR2
MEM_ADDR3

MEM_DQ29

MEM_DQ28
MEM_DQ27

MEM_DQ26
MEM_DQ25

MEM_DQ24

MEM_DQS3

MEM_DQM3
MEM_CLKB#
MEM_CLKB
MEM_CLKEN

MEM_ADDR12
MEM_ADDR11
MEM_ADDR9
MEM_ADDR8
MEM_ADDR7

MEM_DQ15

MEM_DQ1 MEM_DQ14
MEM_DQ2

MEM_DQ3
MEM_DQ4

MEM_DQ5
MEM_DQ6

MEM_DQ7

MEM_DQS0

MEM_WE#

MEM_DQM0

MEM_CAS#

MEM_CS#

MEM_RAS#

MEM_BA0
MEM_BA1
MEM_ADDR10
MEM_ADDR0
MEM_ADDR1
MEM_ADDR2
MEM_ADDR3

MEM_DQ13

MEM_DQ12
MEM_DQ11

MEM_DQ10
MEM_DQ9

MEM_DQ8

MEM_DQS1

MEM_DQM1
MEM_CLKA#
MEM_CLKA
MEM_CLKEN

MEM_ADDR12
MEM_ADDR11
MEM_ADDR9
MEM_ADDR8
MEM_ADDR7

MEM_DQ6

MEM_DQ14

MEM_DQ23

MEM_DQ12

MEM_DQ17

MEM_DQ1

MEM_DQ20

MEM_DQ22

MEM_DQ26

MEM_DQ3
MEM_DQ4

MEM_DQ29

MEM_DQ0

MEM_DQ28

MEM_DQ19

MEM_DQ31

MEM_DQ13

MEM_DQ25

MEM_DQ21

MEM_DQ11

MEM_DQ8

MEM_DQ10

MEM_DQ9

MEM_DQ2

MEM_DQ5

MEM_DQ24

MEM_DQ18

MEM_DQ7

MEM_DQ15

MEM_DQ30

MEM_DQ27

MEM_DQ16

RDQ[0..31]
RDQS[0..3]
RDQM[0..3]
RA[0..13]

RCLK0
RCLK0#
RCS#
RRAS#
RCAS#
RWE#
RCKE

RBA[0..1]

RCLK1
RCLK1#

MEM_DQS0
MEM_DQM0
MEM_DQM1
MEM_DQS1

MEM_DQS2
MEM_DQM2
MEM_DQM3
MEM_DQS3

RDQM1
RDQS1

RDQS0
RDQM0

RDQ0
RDQ1
RDQ2
RDQ3
RDQ4
RDQ5

RDQ7

RDQS2
RDQM2
RDQM3
RDQS3

RDQ8
RDQ9
RDQ10
RDQ11
RDQ12

RDQ14

RDQ17
RDQ18
RDQ19
RDQ20
RDQ21
RDQ22
RDQ23

RDQ16

RDQ15

RDQ24
RDQ25
RDQ26
RDQ27
RDQ28
RDQ29
RDQ30
RDQ31

MEM_CLKA

MEM_CLKA#

RCLK0

RCLK0#

MEM_CLKB

MEM_CLKB#

RCLK1

RCLK1#

MEM_VREF

MEM_VREFMEM_VREF

MEM_ADDR13 MEM_ADDR13

DV25

RA0 MEM_ADDR0

MEM_ADDR8

MEM_ADDR7

MEM_ADDR2

MEM_ADDR4

MEM_ADDR5

RA1

RA2

MEM_ADDR1

MEM_ADDR3

MEM_ADDR6

RA3

RA4

RA5
RA6

RA7

RA13 MEM_ADDR13

MEM_ADDR9RA9

MEM_ADDR12

RA11

RCKE

MEM_ADDR10

RA12

MEM_ADDR11

MEM_CLKEN

MEM_CAS#
MEM_CS#
MEM_BA0

MEM_WE#

MEM_RAS#

RWE#
RCAS#

RRAS#

MEM_BA1

RCS#
RBA0

RBA1

RA10

MEM_ADDR0

MEM_ADDR12

MEM_ADDR10

MEM_ADDR11

MEM_CLKEN

MEM_ADDR2

MEM_ADDR1

MEM_ADDR13

MEM_CS#

MEM_ADDR7

MEM_ADDR3

MEM_CAS#

MEM_ADDR4

MEM_WE#

MEM_ADDR5

MEM_ADDR9

MEM_ADDR6

MEM_ADDR8

MEM_BA1
MEM_BA0

MEM_RAS#

RA8

RDQ6

RDQ13

DV25 DV25 DV25 DV25

DV25

DV25

+1V25_DDR

+1V25_DDR

+1V25_DDR+1V25_DDR

+1V25_DDR

DV25

+1V25_DDR

+1V25_DDR

GND1,2,3,4,5,6,8

DV252,5,6

MEM_VREF6

RDQ[0..31]5
RDQS[0..3]5
RDQM[0..3]5
RA[0..13]5

RCLK05
RCLK0#5
RCS#5
RRAS#5
RCAS#5
RWE#5
RCKE5

RBA[0..1]5

RCLK15
RCLK1#5

Title

Size

Document Number

Rev

Date: Sheet

of

MT5351RA-V2

1

Custom

78Monday, September 26, 2005

DDR MEMORY

TwinSon Chan

GLOBAL SIGNAL

EQUAL LINE LENGTH

BYPASS CAP. FOR DDR

BYPASS CAP. FOR TERMINATOR
(EVERY 2 RESISTOR PUT 1 BYPASS CAP.)

DDR MEMORY

DDR#1 DDR#2

BYPASS CAP. FOR DIMM
+1V25_DDR FOR DDR TERMINATOR
MEM_VREF FOR DDR AND MT5351 VREF

FOR DDR#1

FOR DDR#2

CLOSED TO MT5351 CLOSED TO DDR

CLOSED TO MT5351

CLOSED TO MT5351 CLOSED TO DDR

CLOSED TO DDR

ADD by Ada

R73 47

C174

0.1uF

C0603/SMD

R72 75

C160

0.1uF

C0603/SMD

C141

0.1uF

C0603/SMD

R80 75

C144

0.1uF

C0603/SMD

R102
47

R0603/SMD

R57 47

R56 75

C159

0.1uF

C0603/SMD

RN20 47x4

1 2

3 4

5 6

7 8

R69 47

C170

0.1uF

C0603/SMD

RN14 22x4

1 2

3 4

5 6

7 8

R76 75

C109

0.1uF

C0603/SMD

R107
100

R0603/SMD

U18

16M x 16 DDR TSOP-66

TSOP_0D65_22D6LX9D7W_66SP

VDD

1

DQ0

2

VDDQ

3

DQ1

4

DQ2

5

VSSQ

6

DQ3

7

DQ4

8

VDDQ

9

DQ5

10

DQ6

11

VSSQ

12

DQ7

13

NC

14

VDDQ

15

LDQS

16

NC

17

VDD

18

NC

19

LDM

20

WE

21

CAS

22

RAS

23

CS

24

NC

25

BS0

26

BS1

27

A10/AP

28

A0

29

A1

30

A2

31

A3

32

VDD33VSS

34

A4

35

A5

36

A6

37

A7

38

A8

39

A9

40

A11

41

A12

42

NC

43

CKE

44

CLK

45

CLK

46

UDM

47

VSS

48

VREF

49

NC

50

UDQS

51

VSSQ

52

NC

53

DQ8

54

VDDQ

55

DQ9

56

DQ10

57

VSSQ

58

DQ11

59

DQ12

60

VDDQ

61

DQ13

62

DQ14

63

VSSQ

64

DQ15

65

VSS

66

C161

0.1uF

C0603/SMD

RN22 22x4

1 2

3 4

5 6

7 8

C177

0.1uF

C0603/SMD

RN32 47x4

1 2

3 4

5 6

7 8

R55 47

C146

0.1uF

C0603/SMD

U19

IC LP2996 DDR Termination SOP-8

SOP8/SMD

GND

1

SD

2

VSENSE

3

VREF4VDDQ

5

AVIN

6

PVIN

7

VTT

8

C180

0.1uF

C0603/SMD

C110

0.1uF

C0603/SMD

U15

16M x 16 DDR TSOP-66

TSOP_0D65_22D6LX9D7W_66SP

VDD

1

DQ0

2

VDDQ

3

DQ1

4

DQ2

5

VSSQ

6

DQ3

7

DQ4

8

VDDQ

9

DQ5

10

DQ6

11

VSSQ

12

DQ7

13

NC

14

VDDQ

15

LDQS

16

NC

17

VDD

18

NC

19

LDM

20

WE

21

CAS

22

RAS

23

CS

24

NC

25

BS0

26

BS1

27

A10/AP

28

A0

29

A1

30

A2

31

A3

32

VDD33VSS

34

A4

35

A5

36

A6

37

A7

38

A8

39

A9

40

A11

41

A12

42

NC

43

CKE

44

CLK

45

CLK

46

UDM

47

VSS

48

VREF

49

NC

50

UDQS

51

VSSQ

52

NC

53

DQ8

54

VDDQ

55

DQ9

56

DQ10

57

VSSQ

58

DQ11

59

DQ12

60

VDDQ

61

DQ13

62

DQ14

63

VSSQ

64

DQ15

65

VSS

66

RN28 47x4

1 2

3 4

5 6

7 8

CB133

0.1uF

C0603/SMD

R74 75

+

CE29
220uF/16v

C220UF16V/D6H11

R67 22

C162

0.1uF

C0603/SMD

R103
100

R0603/SMD

CB95

0.1uF

C0603/SMD

RN26 47x4

1 2

3 4

5 6

7 8

C103

0.1uF

C0603/SMD

C147

0.1uF

C0603/SMD

C156

0.1uF

C0603/SMD

+

CE24
47uF/16v

C47UF16V/D5H5

C173

0.1uF

C0603/SMD

RN19 75x4

1 2

3 4

5 6

7 8

R70 75

C152

0.1uF

C0603/SMD

C167

0.1uF

C0603/SMD

+

CE26
220uF/16v

C220UF16V/D6H11

C142

0.1uF

C0603/SMD

RN36 47x4

1 2

3 4

5 6

7 8

RN15 75x4

1 2

3 4

5 6

7 8

C168

0.1uF

C0603/SMD

R71 22

R63 22

+

CE28
220uF/16v

C220UF16V/D6H11

C163

0.1uF

C0603/SMD

C111

0.1uF

C0603/SMD

R108
47

R0603/SMD

RN17 75x4

1 2

3 4

5 6

7 8

RN29 75x4

1 2

3 4

5 6

7 8

C176

0.1uF

C0603/SMD

C148

0.1uF

C0603/SMD

R78 NS/75

RN25 75x4

1 2

3 4

5 6

7 8

R104

4.7K

R0603/SMD

R64 75

CB126

0.1uF

C0603/SMD

C106

0.1uF

C0603/SMD

C154

0.1uF

C0603/SMD

R77 22

R68 75

+

CE25
220uF/16v

C220UF16V/D6H11

R65 22

RN35 75x4

1 2

3 4

5 6

7 8

C157

0.1uF

C0603/SMD

C182

0.1uF

C0603/SMD

C164

0.1uF

C0603/SMD

R79 47

C102

0.1uF

C0603/SMD

C145

0.1uF

C0603/SMD

R62 75

C105

0.1uF

C0603/SMD

C175

0.1uF

C0603/SMD

R106
47

R0603/SMD

C150

0.1uF

C0603/SMD

C107

0.1uF

C0603/SMD

R61 47

+

CE23
220uF/16v

C220UF16V/D6H11

RN33 75x4

1 2

3 4

5 6

7 8

RN31 75x4

1 2
3 4
5 6
7 8

C181

0.1uF

C0603/SMD

C155

0.1uF

C0603/SMD

C143

0.1uF

C0603/SMD

C172

0.1uF

C0603/SMD

RN34 47x4

1 2

3 4

5 6

7 8

C158

0.1uF

C0603/SMD

C165

0.1uF

C0603/SMD

R60 75

RN24 47x4

1 2

3 4

5 6

7 8

R75 47

C139

0.1uF

C0603/SMD

C171

0.1uF

C0603/SMD

C151

0.1uF

C0603/SMD

CB91

0.1uF

C0603/SMD

R59 47

CB125

0.1uF

C0603/SMD

C153

0.1uF

C0603/SMD

C108

0.1uF

C0603/SMD

RN18 22x4

1 2

3 4

5 6

7 8

RN16 47x4

1 2

3 4

5 6

7 8

R105
47

R0603/SMD

C178

0.1uF

C0603/SMD

RN27 75x4

1 2

3 4

5 6

7 8

RN23 75x4

1 2

3 4

5 6

7 8

RN37 75x4

1 2

3 4

5 6

7 8

C169

0.1uF

C0603/SMD

R58 75

R66 75

RN30 22x4

1 2
3 4
5 6
7 8

C166

0.1uF

C0603/SMD

RN21 75x4

1 2

3 4

5 6

7 8

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DV33

ORESET#

PDA0

PDA20

PDA19

PDA18

PDA17

PDA16

PDA15

PDA14

PDA13

PDA12

PDA10
PDA11

PDA9

PDA8

PDA7

PDA6

PDA5

PDA4

PDA3

PDA2

PDA1

PDA21
PDA22
POCE0#
POOE0#
POWE#

NOR_RST#

PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7

NOR_WP#

ORESET#

ORESET#

NOR_RY_BY0#

PDA[0..22]

PDD[0..7]

POWE#

POCE0#
POOE0#

GND

U0TX

U0RX

U1TX

U1RX

JTRST#
JTDI
JTMS
JTCK
JRTCK
JTDO

U2TX
U2RX

U1RX
U1TX

U0RX
U0TX

JRTCK
JTDO

JTAG_DBGACK

JTAG_DBGRQ

JTMS

JTRST#
JTDI

JTCK

TVTREF#1

+5V

U2TX

U2RX

PDA1 PDA2PDA0

R
B
G

G

VOHSYNC
VOVSYNC

VOHSYNC
VOVSYNC

R

B

DV33

DV33

DV33

DV33

DV33

DV33

DV33DV33

GND1,2,3,4,5,6,7

DV331,2,5,6

ORESET#1,4,5

PDA[0..22]5

PDD[0..7]5

POCE0#5
POOE0#5
POWE#5

JTRST#5
JTDI5
JTMS5
JTCK5
JRTCK5
JTDO5

U2TX1,5
U2RX1,5

U1RX5
U1TX5

U0RX1,5
U0TX1,5

+5V1,2,6

R5
B5
G5
VOHSYNC1,5
VOVSYNC1,5

Title

Size

Document Number

Rev

Date: Sheet of

MT5351RA-V2

1

Custom

88Monday, September 26, 2005

NOR FLASH / JTAG / UART

TwinSon Chan

GLOBAL SIGNAL

FLASH INTERFACE

NOR FLASH #0

JTAG PORT

UART (RS232)

FOR SOFTWARE LINK

CLI OUTPUT

SOFTWARE DEBUG PORT

TRAP CIRCUIT

ADD

R85
NS/4.7K

R0603/SMD

C32
NS/10pF

C0603/SMD

J3

10x2

DIP10X2/W/H/IDE/P2.54

1
3
5
7

9
11
13
15
17
19

2
4
6
8
10
12
14
16
18
20

R97 0

R0603/SMD

R98

4.7K

R0603/SMD

R83
NS/4.7K

R0603/SMD

R89

4.7K

R0603/SMD

R84

0

R0603/SMD

J6

CON8

1
2
3
4
5
6
7
8

RN38
1Kx4

RN0603/SMD

1 2

3 4

5 6

7 8

R95

4.7K

R0603/SMD

R93

4.7K

R0603/SMD

+

CE27
10uF/16v

C10UF16V/D5H11

J5

4x1 W/HOUSING

DIP4/W/H/P2.0

1
2
3
4

R92

4.7K

R0603/SMD

U17

IC FLASH MX29LV320 32Mb TSOP-48

TSOP48/SMD

A0

25

A1

24

A2

23

A3

22

A4

21

A5

20

A6

19

A7

18

A8

8

A20

10

OE

28

BYTE

47

A18

16

D0

29

D1

31

D2

33

D3

35

A9

7

CE

26

D4

38

D5

40

D6

42

D7

44

D8

30

D9

32

WP/ACC

14

D11

36

D12

39

D13

41

D14

43

D15/A-1

45

VCC

37

GND1

27

WE

11

A19

9

D10

34

GND2

46

A10

6

A12

4

A11

5

A13

3

A14

2

A15

1

A16

48

A17

17

A21

13

RESET

12

RY/BY

15

R101

4.7K

R0603/SMD

R96 0

R0603/SMD

R94

4.7K

R0603/SMD

CB145

0.1uF

C0603/SMD

R99

4.7K

R0603/SMD

R100

4.7K

R0603/SMD

J4

4x1 W/HOUSING

DIP4/W/H/P2.0

1
2
3
4

R87

4.7K

R0603/SMD

R91
1K

R0603/SMD

R82
NS/4.7K

R0603/SMD

R88

0

R0603/SMD

R86

NS/4.7K

R0603/SMD

C33
10pF

C0603/SMD

R90

4.7K

R0603/SMD

J2

4x1 W/HOUSING

DIP4/W/H/P2.0

1
2
3
4

FB9

FB

BEAD/SMD/0603

Basic Operations & Circuit Description

MODULE

There are 1 pcs panel and 8 pcs PCB including 2 pcs Y/Z Sustainer board, 2 pcs Y Drive
board, 2 pcs X (left and right) Extension PCB, 1 pcs Control (Signal Input) and 1 pcs Power

board in the Module.

SET

There are 6 pcs PCBs including 1 pcs Tuner/Audio board, 1 pcs Keypad board, 1 pcs

Remote Control Receiver board, 1 pcs L/R Speakers and 1 pcs Main (Video) board, 1 pcs ATSC

1 pcs ATSC board in the SET.

Internal Speaker (Right) Power Supply Internal Speaker (Left)

Local Key
remote control
receiver

Main

Tuner/Audio

X Right Extension

Control (Signal Input)

EMI Filter + AC Inlet

Power SW

External Speaker
Terminal

Z-Sustainer

X Left

Extension

Y-Drive
Bottom

Y-Sustainer

Y-Drive Top

ATSC

Parts position

PCB function

1. Power:
(1). Input voltage: AC 110V~240V, 47Hz~63Hz.

Input range: AC 90V(Min)~265V(Max) auto regulation.

(2). To provide power for PCBs.

2. Main board: To converter TV signals, S signals, AV signals, Y Pb/
Cb Pr/Cr signals, DVI signals and D-SUB signals to digital ones and to transmit to
Control board.

3. Control board: Dealing with the digital signal for output to panel.

4. Y-Sustainer / Z-Sustainer board:
(1). Receiving the signals from Control and high voltage supply.
(2). Output scanning waveform for Module.

5. Y-Drive board: Receive signal from Y sustainer, output horizontal scanning wave­form to the panel.

6. X (left and right) extension board: Output addressing signals.

7. Tuner/Audio Board

: :

: :

: Amplifying the audio signal to the internal or external speakers

of which selected.
To convert TV RF signal to video and SIF audio signal to Main board.

8. ATSC Board: Receiver and converter ATSC TV signal to transmit to main board.

PCB failure analysis

1. CONTROL: a. Abnormal noise on screen. b. No picture.

2. MAIN : a. Lacking color, Bad color scale.

b. No voice.
c. No picture but with signals output, OSD and back light.
d. Abnormal noise on screen.

3. POWER: No picture, no power output.

4. Z - Sustainer: a. No picture.

b. Color not enough.
c. Flash on screen.

5. Y - Sustainer: Darker picture with signals.

6. Tuner/Audio : a. No voice. (Make sure status: Mute / Internal, External speaker)

b. Noise

c. No ATV signals

7. Y/Z - Sustainer: The component working temperature is about 55oC.
If the temperature rises abnormal, this may be a error point.

8. ATSC: a. No ATSC TV signal

Basic operation of Plasma Display

1. After turning on power switch, power board sends 5Vst-by Volt to Main
IC MT8205 waiting for ON signals from Key Switch or Remote Receiver.

2. When the ON signal from Key Switch or Remote Receiver is detected, MT8205 will send
ON Control signals to Power. Then Power sends (5Vsc, 9Vsc, 12Vsc, 24V and RLY
ON, Vs ON) to PCBs working. This time VIF will send signals to display back light,
OSD on the panel and start to search available signal sources. If the audio signals
input, them will be amplified by Audio AMP and transmitted to Speakers.

3. If some abnormal signals are detected (for example: over volts, over current, over
temperature and under volts), the system will be shut down by Power off.

Main IC Specifications

- MT8205

- SiI169

- M13S128168A

- MP7720

MT8205/8203

Specifications are subject to change without notice

Application Notes

Page 1 October, 2004

History

2004/09/12 Runma Chen for customer design-in V1.0
2004/09/30 Dragon Chen Add feature list V1.1
2004/09/30 Runma Chen Modify for PIP/POP 444 support V1.2
2004/10/01 Runma Chen PIP/POP hardware limitation-I V1.3
2004/10/18 Dragon Chen &

Wen Hsu

PIP/POP hardware limitation-II & video front end component V1.4

2004/10/20 Dragon Chen Update functional block V1.5
2004/10/21 Dragon Chen Correct function block fault to V1.4 V1.6
2004/11/04 Dragon Chen 1. Delete power spec. (About power spec, please reference another document)

2. Add AC & DC characteristics

3. Add pin description

4. Add audio out mapping rule

V1.7

2004/11/05 Dragon Chen Descript more detail for pin power initial state & remove some description to

another document (MT8205 product brief)

V1.8

MT8205/8203

Specifications are subject to change without notice

Application Notes

Page 2 October, 2004

MT8205/8203 Application Notes

M

T8205/8203 is a highly integrated single chip for LCD TV supporting video input and output format up to HDTV.

It includes 3D comb filter TV Decoder to retrieve the best image from popular composite signals. On-chip
advanced motion adaptive de-interlacer converts accordingly the interlace video into progressive one with overlay
of a 2D Graphic processor. Optional 2

nd

HDTV or SDTV inputs allows user to see multi-programs on same screen.
Flexible scalar provides wide adoption to various LCD panel for different video sources. Its on-chip audio
processor decodes analog signals from Tuner with lip sync control, delivering high quality post-processed sound
effect to customers. On-chip microprocessor reduces the system BOM and shortens the schedule of UI design by
high level C program. MT8205/8203 is a cost-effective and high performance HDTV-ready solution to TV
manufactures.

FEATURES

 Video Input

Input Multiplexing:

 Without external switch, it supports
 1x Component,
 1x S-video,
 1x VGA/Component, (dual function ports)
 1x Digital and
 3x Composite inputs
 All the input sources can be flexibly routed to Main/PIP internally

Input Formats:
 Support VGA input up to SXGA (1280x1024@60Hz

) including SOG VGA

 Support HDTV 480p/720p/1080i input
 Support DVI 24-bit RGB digital input
 Support CCIR-656/601 digital input

 TV decoder

For PIP/POP:

 Dual identical TVD on chip (Single on MT8203)
 3D-Comb for both path.
 Dual VBI decoders for the application of V-Chip

Supporting formats:

 Support PAL (B,G,D,H,M,N,I,Nc), PAL(Nc), PAL, NTSC, NTSC-4.43, SECAM
 Automatic Luma/Chroma gain control
 Automatic TV standard detection
 NTSC/PAL Motion Adaptive 3D comb filter
 Motion Adaptive 3D Noise Reduction
 VBI decoder for Closed-Caption/XDS/ Teletext/WSS/VPS
 Macrovision detection

MT8205

DOCUMENT ARE SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE

Page 3 July, 2004

 2D-Graphic/OSD processor

 Two OSD planes. (For example, Teletext and V-Chip will occupy one planes)
 Support alpha blending among these two planes and video
 Support Text/Bitmap decoder
 Support line/rectangle/gradient fill
 Support bitblt
 Support color Key function
 Support Clip Mask
 65535/256/16/4/2-color bitmap format OSD,


Automatic vertical scrolling of OSD image

 Support OSD mirror and upside down

 Host Micro controller

 Turbo 8032 micro controller
 Built-in internal 373 and 8-bit programmable lower address port
 2048-bytes on-chip RAM
 Up to 4M bytes FLASH-programming interface
 Supports 5/3.3-Volt. FLASH interface
 Supports power-down mode
 Supports additional serial interface
 IR control serial input
 Support RS232 interface
 Support single interface directly supporting SD/MS/MMC memory card
 Support 2 PWM output
 Support DDC2Bi/DDC2B/DDC1/DDCCI
 Maximum 48 programmable GPIO pins
 DRAM Controller
 Supports up to 32M-byte SDR/DDR DRAM
 Supports 16 bit DDR or 32 bit SDR/DDR bus interface
 Build in a DRAM interface programmable clock to optimize the DRAM performance
 Programmable DRAM access cycle and refresh cycle timings
 Maximum DRAM clock rate is 166MHz
 Support 3.3/2.5-Volt SDR/DDR Interface

 Video Processor

Color Management

 Flesh tone and multiple-color enhancement. (For skin, sky, and grass…)
 Gamma/anti-Gamma correction
 Color Transient Improvement (CTI)
 Saturation/hue adjustment

Contrast/Brightness/Sharpness Management

 Sharpness and DLTI/DCTI
 Brightness and contrast adjustment
 Black level extender
 White peak level limiter
 Adaptive Luma/Chroma management

De-interlacing
 Automatic detect film or video source

MT8205

DOCUMENT ARE SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE

Page 4 July, 2004

 3:2/2:2 pull down source detection
 Advanced Motion adaptive de-interlacing

Scaling

 Arbitrary ratio vertical/horizontal scaling of video, from 1/32X to 32X
 Advanced linear and non-linear Panorama scaling.
 Programmable Zoom viewer
 Picture-in-Picture (PIP)
 Picture-Out-Picture (POP)

Display

 12/10, 10/8, 8/6 Dithering processing for LCD display
 10bit gamma correction
 Support Alpha blending for Video and two OSD planes
 Frame rate conversion

 Audio Input/Output

 2 path TV audio in.
 Support AF/SIF decode from Tuner.
 2 channel audio L/R digital line in.
 Total support 12 channel digital outputs optional for general stereo, 2.1 channel with subwoofer, 5.1 channel, and

headphone out.

 Audio Features

 Support BTSC/EIAJ/A2/NICAM decode
 Stereo demodulation, SAP demodulation
 Mode selection (Main/SAP/Stereo)
 Equalizer
 Sub-woofer/Bass enhancement
 MTK proprietary 3D surround processing (Virtual surround)
 Audio and video lip synchronization
 Support Reverberation

 JPEG Decoder

 Decode base-line/progressive JPEG file thru memory card i/f
 SD/MS/MMC, Maximum 1000 files (depend on DRAM size), FW is not finished yet. (10/E will be ready)

 Video Output

 480i/576i/480p/576p/720p/1080i
 Up to (1280x1024@75Hz

) (1366x768@60Hz)

 Dual-channel 6/8-bit LVDS/TTL output
 Support video output mirror and upside down

 DRAM Usage

 For features of 8205, 2pcs of 8x16 DDR166 is necessary
 For features of 8203, 2/1pcs of 8x16 DDR (limited PIP/POP features)
 Here is a comparison chart between (2xDDR) and (1xDDR)

MT8205

DOCUMENT ARE SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE

Page 5 July, 2004

DDR*1(16Mb) DDR*2(32Mb)

NR Y Y

3D-Comb Y Y

MDDi 480i/576i 1080i

PIP *Y Y

POP *Y Y

Display 1024x768 1920x1080

 For 1080i input, 8203 only support bob mode de-interlacing.
 With single DDR, we could support very limited PIP/POP mode.

 Flash Usage

 Flash is used to store FW code, fonts, bitmaps, big tables for VGA, Video, Gamma..
 In our demo system, we can support 2-4 languages within 1MB flash.
 For single country, we need around 20KB to store font data.
 For more bitmaps, we need more flash space to store them.
 2Mbytes is recommended to build a general TV model.

 Outline

 388-pin BGA package
 3.3/1.8-Volt. Dual operating voltages
 0.18um UMC process

MT8205

PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE

Page 6 July, 2004

BLOCK DIAGRAM

ADC

ADC

ADC

ADC

3D TVD

3D TVD

HDTVD

VGAD

DS

PLC

DI

DS

Digital Path

Analog Front End

Main Path

PIP Path

MUX

DRAM

2D Graph

OSD

USColor

CVBS (AV)

YPbPr

S

(Customer)

External

Switches

Digital

VGA (aRGB)

(x3)

Control Signal (GPIO, …)

Gamma

OSD

Merge

Dithering

TTL

LVDS

LVDS Tx

8032

DSP

Analog Path

MDDi

MLC

®

Technology

SiI 169

HDCP PanelLink Receiver

Data Sheet

Document # SiI-DS-0049-B

SiI 169 HDCP PanelLink Receiver
Data Sheet

Silicon Image, Inc.

SiI-DS-0049-B
August 2002

Application Information

To obtain the most updated Application Notes and other useful information for your design, contact your local
Silicon Image sales office. Please also visit the Silicon Image web site at www.siliconimage.com

Copyright Notice

This manual is copyrighted by Silicon Image, Inc. Do not reproduce, transform to any other format, or
send/transmit any part of this documentation without the expressed written permission of Silicon Image, Inc.

Trademark Acknowledgment

Silicon Image, the Silicon Image logo, PanelLink® and the PanelLink® Digital logo are registered trademarks of
Silicon Image, Inc. TMDS
Electronics Standards Association. All other trademarks are the property of their respective holders.

TM

is a trademark of Silicon Image, Inc. VESA® is a registered trademark of the Video

.

Disclaimer

This document provides technical information for the user. Silicon Image, Inc. reserves the right to modify the
information in this document as necessary. The customer should make sure that they have the most recent data
sheet version. Silicon Image, Inc. holds no responsibility for any errors that may appear in this document.
Customers should take appropriate action to ensure their use of the products does not infringe upon any patents.
Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to
infringe upon such rights.

Revision History

Revision Date Comment

A 07/18/2002 Release to Production with complete parametric information.
B 08/14/2002 Correction to DDC bus voltage level-shifting diagram; add Pb-free part number.

© 2002 Silicon Image. Inc.

ii SiI-DS-0049-B

SiI 169 HDCP PanelLink Receiver

Data Sheet

TABLE OF CONTENTS

Functional Description .................................................................................................................................... 2

PanelLink TMDS Core ................................................................................................................................ 2

I2C Interface and Registers ......................................................................................................................... 2

HDCP Decryption Engine and XOR Mask .................................................................................................. 3

HDCP Keys EEPROM................................................................................................................................. 3

Panel Interface Logic and Configuration Logic ........................................................................................... 3

Electrical Specifications .................................................................................................................................. 4

Absolute Maximum Conditions.................................................................................................................... 4

Normal Operating Conditions ...................................................................................................................... 4

DC Specifications ........................................................................................................................................ 5

AC Specifications ........................................................................................................................................ 6

Timing Diagrams ......................................................................................................................................... 8

Input Timing............................................................................................................................................. 8

Output Timing .......................................................................................................................................... 8

Pin Descriptions .............................................................................................................................................11

Digital Output Pins......................................................................................................................................11

Configuration Pins ......................................................................................................................................11

HDCP Pins ................................................................................................................................................ 12

Power Management Pins .......................................................................................................................... 12

Differential Signal Data Pins...................................................................................................................... 12

Reserved Pin............................................................................................................................................. 12

Power and Ground Pins ............................................................................................................................ 13

Feature Information ...................................................................................................................................... 14

HSYNC De-jitter Function ......................................................................................................................... 14

Clock Detect Function ............................................................................................................................... 14

Sync Detect Function ................................................................................................................................ 14

OCK_INV Function.................................................................................................................................... 14

TFT Panel Data Mapping .......................................................................................................................... 16

Power Management .................................................................................................................................. 22

HDCP Operation ....................................................................................................................................... 23

HDCP Authentication............................................................................................................................. 23

SiI 169 HDCP Implementation .............................................................................................................. 24

HDCP DDC / I2C Interface.....................................................................................................................24

Video Requirement for I2C Access ........................................................................................................ 25

I2C Registers.......................................................................................................................................... 25

Using SiI 169 in SiI 161B Designs ............................................................................................................ 28

EXT_RES Resistor Choice ....................................................................................................................... 29

Power Control............................................................................................................................................ 30

Receiver DDC Bus Level-Shifting ............................................................................................................. 30

Voltage Ripple Regulation......................................................................................................................... 31

Decoupling Capacitors .............................................................................................................................. 32

ESD Protection.......................................................................................................................................... 32

Receiver Layout ........................................................................................................................................ 33

EMI Considerations ................................................................................................................................... 33

PCB Thermal Design ................................................................................................................................ 33

Determining Heat Dissipation Requirements ........................................................................................ 33

Implementation Guidelines for Thermal Land Design ........................................................................... 34

Board Mounting Guidelines ................................................................................................................... 36

Stencil Design........................................................................................................................................ 37

Package ........................................................................................................................................................ 38

Ordering Information..................................................................................................................................... 38

SiI-DS-0049-B iii

SiI 169 HDCP PanelLink Receiver
Data Sheet

LIST OF TABLES

Table 1. One Pixel per Clock Mode Data Mapping ....................................................................................... 16

Table 2. Two Pixel per Clock Mode Data Mapping ....................................................................................... 16

Table 3. One Pixel per Clock Input/Output TFT Mode – VESA P&D and FPDI-2TM Compliant.................... 17

Table 4. Two Pixels/Clock Input/Output TFT Mode ...................................................................................... 18

Table 5. 24-bit One Pixel per Clock Input with 24-bit Two Pixel per Clock Output TFT Mode ...................... 19

Table 6. 18-bit One Pixel per Clock Input with 18-bit Two Pixel per Clock Output TFT Mode ...................... 20

Table 7. Two Pixel per Clock Input with One Pixel per Clock Output TFT Mode .......................................... 21

Table 8. Power Management Functionality Table ......................................................................................... 22

Table 9. I2C Register Mapping ...................................................................................................................... 26

Table 10. I2C Register Definitions ................................................................................................................. 27

Table 11. Link Impedance vs EXT_RES Value (all values in Ohms) ............................................................ 29

Table 12. Power Consumption Characteristics ............................................................................................. 30

Table 13. Recommended Components ........................................................................................................ 32

LIST OF FIGURES

Figure 1. SiI 169 Pin Diagram......................................................................................................................... 1

Figure 2. Functional Block Diagram................................................................................................................ 2

Figure 3. Channel-to-Channel Skew Timing ................................................................................................... 8

Figure 4. Digital Output Transition Times ....................................................................................................... 8

Figure 5. Receiver Clock Cycle/High/Low Times............................................................................................ 8

Figure 6. Output Signals Setup/Hold Times.................................................................................................... 9

Figure 7. Output Signals Disabled Timing from PD# Active ........................................................................... 9

Figure 8. Output Signals Disabled Timing from Input Clock Inactive..............................................................9

Figure 9. Input Clock Active to Output Active ................................................................................................ 9

Figure 10. SCDT Timing from DE Inactive/Active......................................................................................... 10

Figure 11. TFT Two Pixels per Clock Staggered Output Timing Diagram .................................................... 10

Figure 12. I2C Data Valid Delay (driving Read Cycle data)........................................................................... 10

Figure 13. Block Diagram for OCK_INV ....................................................................................................... 15

Figure 14. HDCP System Architecture ........................................................................................................ 23

Figure 15. I2C Byte Read .............................................................................................................................. 24

Figure 16. I2C Byte Write .............................................................................................................................. 24

Figure 17. Short Read Sequence ................................................................................................................. 25

Figure 18. Design Using SiI 161B or SiI 169 ................................................................................................ 29

Figure 19. DDC Bus Voltage Level-Shifting using Fairchild NDC7002N ...................................................... 30

Figure 20. Voltage Regulation using Texas Instruments TL431 ................................................................... 31

Figure 21. Voltage Regulation using National Semiconductor LM317.......................................................... 31

Figure 22. Decoupling and Bypass Schematic ............................................................................................. 32

Figure 23. Decoupling and Bypass Capacitor Placement ............................................................................32

Figure 24. DVI to Receiver Routing - Top View ............................................................................................ 33

Figure 25. Bottom View of Thermally Enhanced 100-pin TQFP Package.................................................... 34

Figure 26. TQFP Thermal Land Design on PCB .......................................................................................... 35

Figure 27. Thermal Pad Via Grid .................................................................................................................. 36

Figure 28. Recommended Stencil Design .................................................................................................... 37

Figure 29. Package Diagram ........................................................................................................................ 38

iv SiI-DS-0049-B

SiI 169 HDCP PanelLink Receiver
Data Sheet

General Description Features

The SiI
technology to support HDTV and high-resolution
digital displays for DTV and PC applications. It
features High-bandwidth Digital Content Protection
(HDCP) for secure delivery of high-definition video in
consumer electronics products.

The SiI
HDCP keys, greatly simplifying manufacturing and
providing the highest level of security. For improved
ease of use, the SiI
tolerance and a low-power standby mode.

PanelLink Digital technology is the world’s leading
DVI solution, providing a digital interface solution that
is easy to implement and cost-effective. PanelLink
further simplifies the display interface design by
resolving many of the system level issues associated
with high-speed mixed signal circuits.

169 Receiver uses PanelLink Digital

169 comes with integrated, pre-programmed

169 has enhanced jitter

• Integrated 25-165MHz PanelLink core to support
VGA to UXGA resolutions

• Supports HDTV resolutions (720p/1080i)

• Integrated HDCP decryption engine for viewing

protected content

• Pre-programmed HDCP keys provide highest
level of key security, simplify manufacturing

• Enhanced jitter tolerance

• Time staggered data output for reduced ground

bounce

• High Skew Tolerance: 1 full input clock cycle
(6ns at 165MHz)

• Backwards compatible with SiI

• Sync Detect for “Hot Plugging”

• Flexible low power modes with automatic power

down when input clock is inactive

• Low power 3.3V core operation

• Compliant with DVI 1.0

• Standard and Pb-free packages (see page 38).

SiI 169 Pin Diagram

161B

QO2

51

QO3

52

QO4

53

QO5

QO6

QO7

OVCC 57

OGND 58

QO8 59

QO9 60

QO10

QO11

QO12

QO13

QO14

QO15

VCC

GND 68

QO16 69

QO17

QO18

QO19

QO20

QO21

QO22

54

55

56

61

62

63

64

65

66

67

70

71

72

73

74

75

ODD 8-bits BLUE

ODD 8-bits GREEN

ODD 8-bits RED

QO150

OGND 76

CONTROLS

HSYNC

QO0

48

49

78

77

QO23

OVCC

CLOCK

OUTPUT

DE

VSYNC47

OGND

OVCC

ODCK

43

44

46

45

CTL3

42

HS_DJTR

OCK_INV

41

40

GND39

SiI

100-pin TQFP

(Top View)

82

AVCC

84

AVCC

AGND 83

85

86

RX1-

RX1+

AGND 87

DIFFERENTIAL SIGNALS

80

RX2- 81

RX2+

AGND 79

VCC

38

169

88

AVCC

QE23

37

89

AGND

QE22

36

90

RX0+

EVEN 8-bits RED

QE19

QE20

QE2135

33

34

92

93

RX0- 91

RXC+

AGND

QE18

32

94

RXC-

QE17

31

95

AVCC

QE1325

QE1224

QE1123

QE10

QE9

QE8

OGND19

OVCC18

QE717

QE616

QE5

QE414

QE313

QE2

QE1

QE0

PDO#

SCDT8

STAG_OUT7

VCC

GND

PIXS4

SDA3

PD#

RESET#

EVEN 8-bits GREEN

EVEN 8-bits BLUE

CONFIG. PINS

OGND

OVCC

QE1630

29

97

PVCC

EXT_RES 96

PLL

QE15

28

27

98

99

PGND

RESERVED

QE14

26

22

21

20

15

12

11

10

100

SCL

9

6

5

2

1

SiI-DS-0049-B 1

Figure 1. SiI 169 Pin Diagram

SiI 169 HDCP PanelLink Receiver
Data Sheet

Functional Description

The SiI 169 is a DVI 1.0 compliant digital-output receiver with built-in High-bandwidth Digital Content Protection
(HDCP). It provides a simple, cost effective solution for DTVs implementing DVI-HDCP. Pre-programmed HDCP
keys simplify manufacturing while providing the highest level of security. There is no need to use encrypted keys,
program EEPROMs, or cure epoxy coating.

Figure 2 shows the functional blocks of the chip.

STAG_OUT

PIXS

OCK_INV

HS_DJTR

PD#

RESET#

PDO#

SCLS

SDAS

RXC±

RX0±

RX1±

RX2±

EXT_RES

Configuration Logic

I2C

Slave

PanelLink

TMDS

TM

Digital

Core

Registers

--------------

24

/

encrypted

data

XOR

Mask

control

HDCP

Decryption

Engine

24

/

unencrypted

data

HDCP

Keys

EEPROM

Panel

Interface

Logic

CTL3

QE[23:0]

QO[23:0]

ODCK

DE

HSYNC

VSYNC

SCDT

Figure 2. Functional Block Diagram

PanelLink TMDS Core

The PanelLink TMDS core accepts as inputs the three TMDS differential data lines and the differential clock. The
core senses the signals on the link and properly decodes them providing accurate pixel data. The core outputs
the necessary sync signals (HSYNC, VSYNC), clock (ODCK), and a display enable (DE) signal that drives high
when video pixel data is present. The SCDT signal is output when there is active video on the DVI link and the
PLL has locked on to the video. SCDT can be used to trigger external circuitry, indicating that an active video
signal is present; or used to place the device outputs in power down when no signal is present (by tying SCDT to
PDO#). A resistor tied to the EXT_RES pin is used for impedance matching.

I2C Interface and Registers

The SiI 169 uses a slave I2C interface, capable of running at 400kHz, for communication with the host. HDCP
authentication is managed by reading and writing to registers through the I
the DVI specification, is also tied to the EDID EEPROM that contains information about the display’s capabilities
(resolution, aspect ratio, etc.). The I
5V tolerant and it is recommended that a voltage level shifter be used between the SiI 169 and the DVI connector
as the DDC bus is specified to support 5V signaling.

2 SiI-DS-0049-B

2

C interface. This bus, called DDC in

2

C address of the SiI 169 is 74h as specified by HDCP. This interface is not

SiI 169 HDCP PanelLink Receiver

Data Sheet

HDCP Decryption Engine and XOR Mask

The HDCP decryption engine contains all the necessary logic to decrypt an incoming video signal on a pixel-by­pixel basis. The host system microcontroller initiates an authentication sequence with the receiver to initialize the
SiI 169 HDCP decryption engine. Upon successful completion of the authentication process, the SiI
to decrypt the incoming video via the XOR mask.

Encrypted and unencrypted video will be sent at different times. Therefore the host HDCP transmitter uses the
CTL3 signal to indicate to the SiI

169 receiver whether the incoming video is encrypted or not.

169 is ready

HDCP Keys EEPROM

The SiI 169 comes pre-programmed with a production set of HDCP keys in its internal EEPROM. In this way the
keys are provided the highest level of protection as required by the HDCP specification. Silicon Image manages all
aspects of the key purchasing and programming. There is no need for the customer to purchase HDCP keys from
the licensing authority. For security reasons, the keys cannot be read out of the device.

Samples of the SiI
These are marked with a -PUB part number as noted in the Ordering Information section. Make sure to request
either “Public” or “Production” keys when requesting samples. Before receiving samples of the SiI
production keys a customer must have signed the HDCP license agreement.

169 are available with the B1 public keys as listed in the back of the HDCP specification.

169 with

Panel Interface Logic and Configuration Logic

Unencrypted video data is sent to the display logic by way of a 48-bit output interface. The functionality of this
interface is affected by several of the externally strapped configuration logic options as follows.

• The data output can be presented in either one pixel per clock or two pixels per clock format, depending on
the PIXS configuration setting.

• The polarity of the output clock ODCK can be inverted to accommodate both rising- and falling-edge clocking
through the OCK_INV configuration setting.

• Using the STAG_OUT configuration setting, the odd and even data output groups can be staggered in time to
reduce EMI.

• The HS_DJTR configuration setting can compensate for host-side jitter on the HSYNC input to the transmitter.

• The PD# and PDO# inputs select chip power down modes and allow for disabling of the outputs to the panel.

The RESET# input must be in the HIGH state during normal operation, in both HDCP and non-HDCP modes. Its
primary purpose is to reset the digital block circuitries, including the HDCP engine, and registers at initial chip
power-up time. The VSYNC, HSYNC, DE, and CTL3 signals will be driven low while RESET# is asserted.

necessary to disable the HDCP engine while leaving the chip fully operational for reception of unencrypted video, use the
software reset feature located at bit 0 of register 0xFF by setting it to “1”.

If it is

SiI-DS-0049-B 3

ESMT M13S128168A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2004

Revision : 1.3 1/48

Revision History

Revision 0.1 (15 Jan. 2002)

- Original

Revision 0.2 (19 Nov. 2002)

-changed ordering information & DC/AC characteristics

Revision 0.1 Revision 0.2

M13S128168A - 5T M13S128168A - 6T

M13S128168A - 6T M13S128168A - 7.5AB

Revision 0.3 (8 Aug. 2003)

-Change IDD6 from 3mA to 5mA.

Revision 0.4 (27 Aug. 2003)

-Change ordering information & DC / AC characteristics.

Revision 1.0 (21 Oct. 2003)

-Modify tWTR from 2tck to 1tck.

Revision 1.1 (10 Nov. 2003)

-Correct some refresh interval that is not revised.

-Correct some CAS Lantency that is not revised.

Revision 1.2 (12 Jan. 2004)

-Correct IDD1; IDD4R and IDD4W test condition.

-Correct tRCD; tRP unit

-Add tCCD spec.

-Add tDAL spec.

Revision 1.3 (12 Mar. 2004)

-Add Cas Latency=2; 2.5

ESMT M13S128168A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2004

Revision : 1.3 2/48

DDR SDRAM 2M x 16 Bit x 4 Banks
Double Data Rate SDRAM

Features

 JEDEC Standard

 Internal pipelined double-data-rate architecture, two data access per clock cycle

 Bi-directional data strobe (DQS)

 On-chip DLL

 Differential clock inputs (CLK and CLK )

 DLL aligns DQ and DQS transition with CLK transition

 Quad bank operation

 CAS Latency : 2; 2.5; 3

 Burst Type : Sequential and Interleave

 Burst Length : 2, 4, 8

 All inputs except data & DM are sampled at the rising edge of the system clock(CLK)

 Data I/O transitions on both edges of data strobe (DQS)

 DQS is edge-aligned with data for reads; center-aligned with data for WRITE

 Data mask (DM) for write masking only

 V

DD

= 2.375V ~ 2.75V, V

DDQ

= 2.375V ~ 2.75V

 Auto & Self refresh

 7.8us refresh interval

 SSTL-2 I/O interface

 66pin TSOPII package

Operating Frequencies :

PRODUCT NO. MAX FREQ VDD PACKAGE

M13S128168A -5T 200MHz

M13S128168A -6T 166MHz

2.5V TSOPII

ESMT M13S128168A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2004

Revision : 1.3 3/48

Control Logic

Functional Block Diagram

Pin Arrangement

Bank A

Command Decoder

Bank D

Latch Circuit

Bank B

Bank C

DM

DQ

Mode Register &

Extended Mo de
Register

Column

A

ddress
Buffer
&
Refresh
Counter

Row

A

ddress
Buffer
&
Refresh
Counter

Row Decoder

Sense Amplifier

Column Decoder

Data Control Circuit

Input & Output

Buffer

A

ddress

Clock
Generator

CLK

CLK

CS

RAS

CAS

WE

DLL DQS

CLK, CLK

DQS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33

66 PIN TSOP(II)
(400mil x 875mil)
(0.65 mm PIN PITCH)

VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
V

DDQ

LDQS
NC
V

DD

NC
LDM
WE
CAS
RAS
CS
NC
BA

0

BA1
A10/AP
A

0

A1
A2
A3
VDD

VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
V

SSQ

UDQ S
NC
V

REF

VSS
UDM
CLK
CLK
CKE
NC
NC
A

11

A9
A8
A7
A6
A5
A4
VSS

66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34

x16

x16

Monolithic Power Systems

MP7720

20W Class D Mono

Single Ended Audio Amplifier

PRELIMINARY INFORMATION

General Description

The MP7720 is a mono 20W Class-D Audio
Amplifier. It is one of MPS’ second generation
of fully integrated audio amplifiers which
dramatically reduces solution size by
integrating the following:

 180mΩ power MOSFETs
 Start up / shut down pop elimination
 Short circuit protection circuits
 Mute / Stand By

The MP7720 utilizes a single ended output
structure capable of delivering 20W into 4Ω
speakers. MPS Class-D Audio Amplifiers
exhibit the high fidelity of a Class A/B amplifier
at efficiencies greater than 90%. The circuit is
based on the MPS’ proprietary variable
frequency topology that delivers excellent
PSRR, fast response time and operates on a
single power supply.

Ordering Information

Part Number ∗

MP7720DS SOIC8
MP7720DP PDIP8
EV0030 Evaluation Board

∗ For Tape & Reel use suffix - Z (e.g. MP7720DS-Z)
∗ For Lead Free use suffix - LF (e.g. MP7720DS-LF)

OFF

Audio
Input

Figure 1: Typical Application Circuit

Package Temperature

VDD

PGND

BS

SW

ON

EN
PIN
NIN
AGND

-40°C to + 85°C

-40°C to + 85°C

VDD

7.5V to 24V

Ω

Ω

4

or 8

Features

 20W output at V
 THD+N = 0.04% @ 1W, 8Ω
 93% efficiency at 20W
 Low noise (190µV typical)
 Switching Frequency to 1MHz
 9.5V to 24V operation from single supply
 Integrated Start Up and Shut Down

Pop Elimination Circuit

 Thermal protection
 Integrated 180mΩ switches
 Mute / Standby-mode (Sleep)
 Tiny 8 Pin SOIC or PDIP Package
 Evaluation Board Available

=24V into a 4Ω load

DD

Applications

 Surround Sound DVD Systems
 Televisions
 Flat Panel Monitors
 Multimedia computers
 Home stereo

20

10

5

2

1

0.5

%

0.2

0.1

0.05

0.02

0.01
60m

100m 200m 500m

1 2

W

Figure 2: THD+N vs. Power (24V, 1KHz)

8Ω

5

10 20

4Ω

30

MP7720 Rev 1.5 06/17/04

www.monolithicpower.com 1

Monolithic Power Systems

MP7720

20W Class D Mono

Single Ended Audio Amplifier

PRELIMINARY INFORMATION

Absolute Maximum Ratings (Note 1)

Supply Voltage V
BS Voltage V
Enable Voltage V

, V

PIN

, V

NIN

V

SW

26V

DD

-0.3V to VSW+6.5V

-0.3V to 6V

EN

SW

-1V to VDD+1V

AGND to PGND -0.3V to 0.3V
Junction Temperature 150°C
Lead Temperature 260°C
Storage Temperature -65°C to 150°C

Recommended Operating Conditions (Note 2)

Supply Voltage V
Operating Temperature T

9.5V to 24V

DD

-40°C to 85°C

A

Package Thermal Characteristics

Thermal Resistance Θ
Thermal Resistance Θ
Thermal Resistance Θ
Thermal Resistance Θ

(SOIC8) 105°C/W

JA

(SOIC8) 50°C/W

JC

(PDIP8) 95°C/W

JA

(PDIP8) 55°C/W

JC

Table 1: Electrical Characteristics (VDD=24V, VEN=5V, TA=25°C)

Parameters Condition Typ Max Units

Supply Current

Standby Current VEN = 0V 1 5 µA
Quiescent Current 1.5 3.0 mA

Output Drivers

SW On Resistance Sourcing and Sinking 0.18 Ω
Short Circuit Current Sourcing and Sinking 5.0 A

Inputs

PIN, NIN Input Common Mode
Voltage Range
PIN, NIN Input Current V

EN Enable Threshold Voltage

0

PIN=VNIN

=12V 1 5 µA

VEN Rising 1.4 2.0 V

Falling 0.4 1.2 V

V

EN

EN Enable Input Current VEN = 5V 1 µA

Thermal Shutdown

Thermal Shutdown Trip Point TJ Rising 150
Thermal Shutdown Hysteresis 30

VDD

2

-1.5 V

V

DD

°C
°C

Table 2: Operating Specifications (Circuit of Figure 3, VDD=24V, VEN=5V, TA=25°C)

Standby Current VEN = 0V 130 µA
Quiescent Current 13 mA

Power Output

THD+ Noise

Efficiency

Maximum Power Bandwidth 20 KHz
Dynamic Range 93 dB
Noise Floor A-Weighted 190 µV
Power Supply Rejection f=1KHz 60 dB

Note 1. Exceeding these ratings may damage the device.
Note 2. The device is not guaranteed to function outside its operating rating.

MP7720 Rev 1.5 06/17/04

www.monolithicpower.com 2

f=1KHz, THD+N = 10% , 4Ω Load 20 W
f=1KHz, THD+N = 10% , 8Ω Load 10 W
P

=1W, f=1KHz, 4Ω Load 0.08 %

OUT

=1W, f=1KHz, 8Ω Load 0.04 %

P

OUT

f =1KHz, P
f =1KHz, P

=1W, 4Ω Load 90 %

OUT

=1W, 8Ω Load 95 %

OUT

Monolithic Power Systems

Ω

µ

MP7720

C4

10pF

VDD

PGND

BS

SW

R3

100KΩ

R2

100KΩ

Audio Input

1µF, 16V

C1

OFF

C2

4.7µF,
16V

R1, 10KΩ

ON

C3, 5.6nF

EN
PIN
NIN
AGND

R4, 82K

R6

10KΩ

C10

390pF

C5
1µF, 35V

C7, 0.1µF

MP7720

20W Class D Mono

Single Ended Audio Amplifier

PRELIMINARY INFORMATION

D2, 6.2V

L1, 10

D1
1A, 30V

R5

10kΩ

C6
470µF, 35V

H

VDD

9.5 to 24V

1000µF

25V

C8

0.47µF
50V Metal

C9

RL
4Ω

Figure 3: 20W Mono Typical Application Circuit

MP7720 Rev 1.5 06/17/04 www.monolithicpower.com 3

Product Specification of PDP Module

0. Warnings and Cautions

9 WARNING indicates hazards that may lead to death or injury if ignored.
9 CAUTION indicates hazards that may lead to injury or damage to property if ignored.

WARNING

1) This product use s a high voltage (450 V max.). Do not touch the circuitry of this product with your hands when
power is supplied to the product or immediately after turning off the power. Be sure to con firm that the voltage
is dropped to a sufficiently low level.

2) Do not supply a voltage higher than that specified to this product. This may damage the product and may cause a
fire.

3) Do not use this product in locations where the humidity is extremely high, where it may be splashed with water,
or where flammable materials surround it. Do not install or use the product in a location that does no satisfy the
specified environmental conditions. This may damage the product and may cause a fire.

4) If a foreign substance (such as water, metal, or liquid) gets inside the product, immediately t urn off the power.
Continuing to use the products it may caus e fire or electric shock.

5) If the product emits smoke, an abnormal smell, or makes an abnormal sound, immediately turn off the power. If
noting is displayed or if the display goes out during use, immediately turn off the power. Continuing to use the
product as it is may cause fire or electric shock.

6) Do not disconnect or connect the connector while power to the product is on. It takes some time for the voltage
to drop to a sufficiently low level after the power has been turned off. Confir m that the voltage has dropped to a
safe level before disconnecting or connecting the connector. Otherwise, this may cause fire, electric shock, or
malfunction.

7) Do not pull out or insert the power cable from/to an outlet with wet hands. It may cause electric shock.

8) Do not damage or modify the power cable. It may cause fire or electric shock.

9) If the power cable is damaged, or if the connector is loose, do not use the product; otherwise, this can lead to fire
or electric shock.

10) If the power connector or the connector of the power cable becomes dirty or dusty, wip e it with a dry cloth.
Otherwise, this can lead to fire.

Product Specification of PDP Module

 USE

1) Because this product uses a high voltage, connecting or disconnecting the connectors while power is supplied to
the product may cause malfunctioning. Never connect or disconnect the con nectors while the power is on.
Immediately after power has bee n turned off, a residual voltage remains in the product. Be sure to confirm that
the voltage has dropped to a sufficiently low level.

2) Watching the display for a long time can tire the eyes. Take a break at appropriate intervals.

3) PDP ’s brightness and contrast ratio is lower than that of the CRT. The picture is dimmer with surrounding light
and better for viewing in dark condition.

4) Do not cover or wrap the product with a cloth or other co vering while power is supplied to the product.

5) Before turning on power to the product, check the wiring of the product and confirm that the supply voltage is
within the rated voltage range. If the wiring is wrong or if a voltage outside the rated range is applied, the
product may malfunction or be damaged.

6) Do not store this product in a location where temperature and humidity are high. This may cause the product to
malfunction. Because this product uses a discharge phenomenon, it may take time to light (operation may be
delayed) when the product is used after it has been stored for a long time. In this cas e, it is recommended to light
all cells for about 2hours (aging).

7) If the glass surface of the display becomes dirty, wipe it with a soft cloth moistened with a neutral detergent. Do
not use acidic or alkaline liquids, or organic solvents.

8) Do not tilt or turn upside down while the module packa ge is carried, the product may b e damaged.

9) This product is made from various materials such as glas s, metal, and plastic. When discarding it, be sure to
contact a professional waste disposal operator.

 Repair and Maintenance

Because this product combines the display p anel and driver circuits in a single module, it cannot be repaired or
maintained at user’s office or plant. Arrangements for maintenance and repair will be determined later

Product Specification of PDP Module

1. GENERAL DESCRIPTION

 DESCRIPTION

The PDP42V6#### is a 42-inch 16:9 color plasma display mod ule with resolution of 852(H) × 480(V) pixels.
This is the display device which offers vivid colors with adopting AC plasma technology by LG Electronics Inc.

 FEARURES

High peak brightness (1000cd/m2Typical) and high contrast ratio (3000:1 Typical) enables user to cre a te
high performance PDP SETs.

 APPLICATIONS

9 Public information display
9 Vide o confe rence systems
9 Education and training systems

Product Specification of PDP Module

 ELECTRICAL INTERFACE OF PLASMA DISPLAY

The PDP42V6#### requires only 8bits of digital video signals for each RGB color.
In addition to the video signals, six different DC voltages are required to operate the display.
The PDP42V6#### is equipped with P-CUBE function which analyzes display signals to optimize system
control factor for showing the best display performance.

 GENERAL SPECFICATIONS

9 Model Name
9 Number of Pixels
9 Pixel Pitch
9 Cell Pitch
9 Display Area
9 Outline Dimension
9 Pixel Type
9 Number of Gradations
9 Weight

: PDP42V6#### (42V6#### Model)
: 852(H) × 480(V) (1pixel=3 RGB cells)
: 1080㎛ (H) × 1080㎛ (V)
: 367㎛ (H) × 1080㎛ (V) (Green Cell basis)
: 920.1(H) × 518.4(V) ±0.5mm
: 1005(H) × 597(V) × 61(D)±1mm
: RGB Closed type
: (R)256 × (G)256 × (B)256 (16.7 Mega colors)
: 14.8 Kg ± 0.5 Kg (Net 1EA)

111 Kg ± 5 Kg (5EA/1BOX)

9 Aspect Ratio
9 Peak Brightness
9 Contrast Ratio

: 16:9
: Typical 1000cd/㎡ (1/25 White Window)
: Average 60:1 (In a bright room with 150Lux at center)
: Typical 3000:1 (In a dark room 1/25 White Window pattern at center)

9 Power Consumption
9 Life-time

: Typical 220 W (Full White)
: more than 60,000 Hours of continuous operation

☞ Life-time is defined as the time when the brightness level becomes half of its initial value.

9 Display Dot Diagram

Pixel Pitch(width)

1st pixel
row

2nd pixel
row

3rd pixel
row

479th pixel
row

480th pixel
row

pitch(height)

㎜

1.080

1st
pixel
column

1.080㎜

BGR BGR

BGR BGR

BGR BGR

BGR BGR

BGR BGR

2nd
pixel
column

Cell pitch

R:0.338㎜
G:0.367㎜
B:0.374㎜

851th
pixel
column

cell

BGR BGR

BGR BGR

BGR BGR

BGR BGR

BGR BGR

852th
pixel
column

pixel

Product Specification of PDP Module

7. CONNECTORS and CONNECTIONS

 Power Input Connector

¾ Connector P3001 Pin Assignment

Pin No. Symbol

1
2
3
4

9 Module side connector : 1-1123723-8 (Header)
9 Mating Connector : 1-1123722-8 (Housing)
9 Connector Supplier : AMP

Vs
Vs
nc

GND

Pin No. Symbol

5
6
7
8

¾ Connector P2005 Pin Assignment

Pin No. Symbol

1
2
3
4

5

VS
VS
VS

nc

GND

Pin No. Symbol

6
7

8
9

10

GND

Va

GND

+5V

GND

GND

GND

nc

nc

5678

1-1123723-8 Pin num bers

(Top View, viewed from the pin connection side)

234

1

9 Module side connector : 1-1123723-10 (Header)
9 Mating Connector : 1-1123722 –10 (Housing)
9 Connector Supplier : AMP

5678910

1-1123723-10 Pin num bers

(Top View, viewed from the pin connection side)

234

¾ Connector P2006 Pin Assignment

Pin No. Symbol

1
2

9 Module side connector : 1-1123723-4 (Header)
9 Mating Connector : 1-1123722-4 (Housing)
9 Connector Supplier : AMP

GND

Pin No. Symbol

3
4GND

1

5V
5V

234

1

1-1123723-4 Pin numbers

(Top View, viewed from the pin connection side)

Product Specification of Power Supply Unit

8. Input/Output pin assignment & specification

¨

Pin Assignment

1 2

8 7 6 5 4 3 2 1

10 9 8 7 6 5 4 3 2 1

4 3 2 1

1
2
3
4
5
6
7
8

1
2
3
4
5
6
7
8
9

1
2
3
4
5
6
7
8
9
10
11
12

1
2
3
4

1
2
3
4
5
6
7

#1 : Vs
#2 : Vs
#3 : NC
#4 : GND
#5 : GND
#6 : Va
#7 : GND
#8 : +5V

CN807

CN806

#1 : Va
#2 : Va
#3 : GND
#4 : GND
#5 : GND
#6 : GND
#7 : NC
#8 : Vs
#9 : Vs
#10 : Vs

#1 ~#2
: 5Vctrl
#3 ~ #4
: GND

CN805

CN808

#1 ~ #4
: +5Vctrl
#5 ~ #8
: GND

CN804

CN803

#1 ~ #3 : 5Vsc
#4 ~ #6 : GND
#7, #8 : 12Vsc
#9, #10 : GND
#11, #12 : NC

CN802

#1 ~#2
: 30V or 24V
#3 ~ #4
: GND

CN801

#1 : ACD
#2 : RLY ON
#3 : 5Vst_by
#4 : GND
#5 : Vs ON
#6 : 5VD
#7 : NC

CN02 CN03

CN01

Before connecting with S/W

From inlet

AMP171825-2CN809

AMP171825-8CN808

AMP1-1123723-8CN807

AMP1-1123723-0CN806

AMP1-1123723-4CN805

AMP171825-9CN804

AMP1-171825-2CN803

AMP171825-4CN802

AMP171825-7CN801

AMP3-176976-1(Natural)CN03

AMP3-176976-1(Natural)CN02

AMP3-176976-2(Red)CN01

VendorSpecificationLocation No.

Live

Neutral

Live

Neutral

After connecting with S/W

CN809

1
2

#1 : 9Vsc
#2: GND

1 2

* PSU operation method S/W

Normal : On/Off with Vsc B/D

Auto : Automatic On/Off

without Vsc B/D

Selection S/W

24V 30V

#1 : 9Vsc
#2 : 9Vsc
#3 : GND
#4 : 5Vsc
#5 : 5Vsc
#6 : 5Vsc
#7 : GND
#8 : GND
#9 : GND

1 2

1 2

Product Specification of Power Supply Unit

9. Adjustment detail

¨

Adjustment detail

8 7 6 5 4 3 2 1

1
2
3
4
5
6
7
8
9

1
2
3
4
5
6
7
8
9
10
11
12

1
2
3
4

1
2
3
4
5
6
7

CN807

CN804

CN803

CN802

CN801

CN809

1
2

Selection S/W

24V 30V

1 2

* PSU driving method S/W

Normal(Mode1) : Driving with interface B/D

Auto(Mode2) : Driving without

interface B/D

CN02 CN03

CN01

* Connect with Noisefilter Cable

Live

Neutral

Live

Neutral

1 2

1 2

1 2

* You can select output Audio Voltage(24V or 30V)

Vs adj.

Va adj.

* Vs Voltage Variabe Resistor

- Turn right, increase Voltage
Turn left, decrease Voltage

* Va Voltage Variabe Resistor

- Turn right, increase Voltage
Turn left, decrease Voltage

* Connect with S/W Cable

※ The color of CN01 is red.(The color of CN02, CN03 are natural.)

Selection S/W

Normal
(Mode1)

Auto
(Mode2)

* Connect with S/W Cable

1
2
3
4
5
6
7
8

CN808

10 9 8 7 6 5 4 3 2 1

CN806

CN805

4 3 2 1

8. LABEL

 LABEL Sticking Position

Product Specification of PDP Module

Coner Plate

E/X Tube

Y-SUS

X left

ⓐ

ⓑ ⓒ ⓓ

CONTROLLER

Signal Input

(R,G,B,H/Vsync.)

ⓔ

X right

ⓕ

3211QKE008A

ⓖ

Z-SUS

P/N
(carved)

 Identification Label : LABEL ⓐ

①

②
③

④⑤⑥
① Model Na me
② Bar Code (Code 128, Contains the man ufa c tur e No.)
③ Manufact ure No.
④ The trade name of LG Electronics
⑤ Man uf act ured date ( Ye a r & Month)
⑥ Manufact ured plac e

7.0 ㎝

2.5 ㎝

⑦

Trouble Shooting Manual of PDP Module

- Introduction

- Precautions

- Basic

- Trouble shooting

COMPOSITION OF PDP BOARDS

CONTROL B/D

Y-DRIVE
BOTTOM

Y-SUS

B/D

Y-DRIVE

TOP

X-LEFT B/D

X-RIGHT B/D

Z-SUS B/D

COF

COF

IPM

IPM

1. Introduction

PSU

42” V6 MODEL.

Definitions

Exhaust

hole

long 1

long 2

short 1

short 2

COF long2-1

••••••••

COF long 2-7

■

Definition of MODULE position

6####

2004.02

402K242V6000266.ASLGA

■

Identification label

① Model Name
② Bar Code (Code 128, Contains the manufacture No.)
③ Manufacture No.
④ The trade name of LG Electronics
⑤ Manufactured date (Year & Month)
⑥ The place Origin
⑦ Model Suffix

①

②

③

④⑤⑥

⑦

1. Introduction

* Back side of module

Vsc-VyVsetup

■

Voltage label (Attached on back side of module)

■

Part No. label (Attached on board)

■

COF serial No. label (attached on COF)

1. Introduction

PCB PART NO.

BOARD ASS`Y
PART NO.

BOARD NAME

BOARD SERIAL NO.

COF SERIAL NO.

8

/40

■

Terms of defect

Add short (line on)

Sus open (line off)

Sus short (line on)

Add open (line off)

AppearanceTerm

1. Introduction

9

/40

1. Before repairing there must be a preparation for 10 min.

2. Do not impress a voltage that higher than represented on the product.

3. Since PDP module uses high voltages, Be careful a electric shock

and after removing power some current remains in drive circuit.

so you can touch circuit after 1 min.

4. Drive circuits must be protected from static electricity.

5. The PDP module must be Moved by two man.

6. Be careful with short circuit of PDP boards when measuring any voltages.

2. Precaution

Be sure to read this before service. When using/ handling this PDP module, Please pay attention to the

below warning and cautions.

Safety precautions

Before request service

2. Check the model label. Whether it is boards of same model with label.

3. Before requesting Service, please inform us a detail defect phenomenon and history of module.

it can be helpful to us for a smooth sevice.

Ex) COF long 2-1 fail ,address 1 line open, Y b/d problem , mis-discharge.

1. Check panel surface and appearance of B/D.

SCRATCHING TEARING BEING PUSHED

BENDING CHOPING

2. Precaution

COF is the most important component in the PDP module.

Even a little imperfection of COF can make a serious screen problem.

Handle with care (COF)

X LEFT B/D

X LEFT B/D

X RIGHT B/D

X RIGHT B/D

3. Basic

1. X B/D

<COF Separating>

: receiving LOGIC signal from CONTROL B/D and make ADDRESS

PULSE(generates Address discharge)by ON/OFF operation,

and supplies this waveform to COF(data)

Power partSignal part

Lift up lock as shown
in narrow.

Pull COF
as shown in narrow.

12

/40

: make SUSTAIN PULSE and ERASE PULSE that generates

SUSTAIN discharge in panel by receiving LOGIC signal from

CONTROL B/D.

this waveform is supplied to panel through FPC(Z).

*composed with IPM,FET,DIODE, electrolytic capacitor ,E/R coil.

* IPM (Intelligent Power Module)

E/R(Energy recovery)

Separate the fixed Screw of Z-Board.
Pull out Lock as shown in arrow.

Condition in Lock part is pulled

Pull FPC Connector
as shown in arrow.

<FPC Separating>

2. Z sustain B/D

3. Basic

13

/40

1) This is a path to supply SUSTAIN ,RESET waveform which made

from Y SUSTAIN B/D to panel through SCAN DRIVER IC.

2) Supply a wave form that select Horizontal electrode (Y SUSTAIN electrode)

sequentially.

- potential difference is 0V between GND and Vpp of DRIVER IC

in SUSTAIN period.

- being generated potential difference between GND and Vpp only

in SCAN period.

* In case of 42” V6 use DRIVER IC IC 8 EA (TOP, BOTTOM: each 4EA)

3. Y drive B/D

3. Basic

14

/40

: generates SUSTAIN,RESET waveform, Vsc(SCAN)voltage.

and supplies it Y DRIVER B/D.

* Composed with IPM,DIODE, electrolytic capacitor ,FET.

: creates signal processing (Contour noise,reduction ISM,..)

and an order of many FET on/off of each DRIVER B/D with

R,G,B each 8bit input.

* Use 3.3V/5V 2 kinds of power .

5. Control Board

4. Y sustain B/D

3. Basic

15

/40

: Being impressed 5V, Va ,Vs,

DC/DC converter makes

5V,Va,Vs,Vset_up,Vsc

which is essential for each B/D.

There is no DC/DC B/D in

model 40 〞/42 〞(1 POWER B/D).

* 50 〞60 〞embedded DC/DC B/D

separately because of high power

consumption.

DC/DC con.

part

6. DC/DC Converter part

3. Basic

16

/40

: supply a driving waveform to PANEL by connecting a PAD

electrode of PANEL with PCB(Y and Z).

* there is two type of this for Y B/D. One is single-sided,

another is double-side. These are having pattern on it

* for Z B/D, there is no pattern , single-sided, and Beta

type(all of copper surface).

: for connecting a Logic signal between B/D and B/D.

*There is 0.5mm pitch,50pin type

1mm pitch ,30pin type.

7. FPC (Flexible Printed Circuit)

8. FFC (Flat Flexible Cable)

3. Basic

: supply a waveform which made from X B/D to panel and select

a output pin that is controlled by COF when be on or off.

96 output pin per IC.

─

the more the resolution higher, the less spare space where

can set IC on it in B/D. without using IC PACKAGE,

we can use a BARE IC , so we can get IC with LOW COST

─

because we do not solder IC on PCB directly,

a soldering defect rate decrease.

* composition

1) FPC + Heat /Sink

⇒

FPC for COF must have a Low Spec decline with getting damp

2) CHIP resistor + CHIP CAPACITOR

3) BARE IC (STV7610A/WAF) + GOLD WIRE/AL WIRE

4) EPOXY MOLDING

9. COF (Chip On Film)

Bare IC

* 42 V6 COF is the same as 42V5.

3. Basic

18

/40

: composition

HEATSINK,CAPACITOR

DIODE

IC LINEAR

RESISTORTANSISTOR,FETS.

: description

Attached at Z B/D and Y B/D, make Sustain waveform.

Sustainer : supply a square wave to panel to make a video.

10. IPM(Intelligent Power Module)

IPM

3. Basic

19

/40

4. Trouble shooting.

what kind of defect?

Fast check up

Horizontal defect?

vertical defect?

Mis –discharge

on screen?

No display?

defect

Check model No. of module ,all connectors and cables.

Check panel appearance

Check PSU output (Va,Vs,5v)

Check Y, Z b/dinput voltage

Replace ctrl b/d

Replace Y, Z b/d

Check panel appearance Check COF

Replace ctrl b/d

Replace X b/d

Check FPC Replace Y drv b/d

Replace Y sus b/d

Replace ctrl b/d

Replace Y drv b/d

Replace Y sus b/d

Replace ctrl b/d

20

/40

what kind of defect?

4. Trouble shooting.

Horizontal defect?

vertical defect?

Mis –discharge

on screen?

No display?

Logical judgment

What kind of defect ?

Please follow the no display trouble shooting.

Bar defect appeared?

Line defect

Please follow the mis discharge trouble shooting.

Please follow bar defect trouble shooting.

Please follow the line defect trouble shooting.

21

/40

Confirm every Connector (PSU, Y-SUS, CTRL, Z-SUS)

⇒ module may not be normal by mis-connection which can not send signal and power.

Also Mis connection for a long time has a specific b/d failed.

1. Connector

4. Trouble shooting.

No display

CTRL B/D + Y-SUS CTRL B/D + Z-SUS CTRL B/D + X-B/D Signal input(LVDS)

Check each section with following method if there is problem, replace or repair that part.

If not go to the next section.

22

/40

Confirm exhausting Tip and find Crack with naked eyes to check vacuum state.

If there is problem replace the module .

⇒ in case of vacuum breakdown, module makes a shaking noise because of inside gas ventilation.

(there may be a small crack which could not see with naked eyes. And this noise is different from Capacitor noise. )

2. Exhaust tip Crack

CRACKEDNORMAL

4. Trouble shooting.

1. Check each unit part of PSU inside with naked eyes.

(capacitor, FET, a kind of IC, resistor)

2. Check FUSE and SW1 (on Normal).

3. Check Output voltage which is converted from AC V

to DC V.

voltage Check (5V, Va, Vs)

※ When PSU Protection occurred. Check Short

between Y-SUS, Z-SUS B/D .

3. PSU(Power Supply Unit)

Fuse open check

SW1 Normal

Multi-meter Touch point
(5V, Va ,Vs must accord with Module Label)

Vs Voltage ADJ

(Vs : About 180 ~195 V)

Va, 5V(VCC) Voltage ADJ

■

Va : About 55 ~65 V

■

5V(VCC) : 5V~5.5V)

4. Trouble shooting.

if not same

Confirm

input voltage

Adjust

voltages

1. Confirm LED D17(flashing) ,13 lighting

2. If not CHECK OSC X1 output.

3. Check CTRL input voltage

(CONNECTOR P300)

4. CHECK 3.3V, 5V,15V.

5. Check IC 11 3.3V

IC 3 2.5V

4. Ctrl B/D

4. Trouble shooting.

Check oscillating state.

(normal 100 MHZ)

Be careful with physical shock.

Probe

Touching

point

Input voltage

Diode

OSC(X1)

Check IC 11,13

DMM +

DMM – (GND)

25

/40

5. Y-sus B/D

1. Check FUSE [FS1(5v) ,FS2(Vs)].

2. Check voltages(Vsetup,-Vy, Vscw)

3. Check DIODE between GND and Y SUS output.

[SUSUP(OC2) SUSDN(OC1)].

forward=0.4 ,reverse=OVERLOAD.

4. Check whether output voltages agrees

with voltage that represented in label.

Vsetup

setdn

-Vy

Vscw

setup

4. Trouble shooting.

FS2

FS1

Normal diode value = OL (reverse)Normal diode value= 0.4 (forward)

■

Check whether output voltages agrees with voltage that represented in label.

4. Trouble shooting.

■

Check diode value GND between Y-SUS output.

6. Z-sus B/D

Va FUSE 6.3A Vs FUSE 2A or 4A

5V FUSE

1. Check the FUSE.

2. Check input voltages.(Va, 5V,15V)

3. Check FPC out put diode value.

4. Check ramp waveform.

4. Trouble shooting.

■

Check the FUSE

■

Check input voltages