ViewSonic makes no representations or warranties, either expressed or implied, with
respect to the contents hereof and specifically disclaims any warranty of merchantability or
fitness for any particular purpose. Further, ViewSonic reserves the right to revise this
publication and to make changes from time to time in the contents hereof without obligation
of ViewSonic to notify any person of such revision or changes.
Trademarks
ViewSonic is a registered trademark of ViewSonic Corporation. All other trademarks used
within this document are the property of their respective owners.
Revision History
Revision Date Description Approval
1a12/17/02 Initial Release DCN-2256C.Shen
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TABLE OF CONTENTS
Chapter 1 Precautions and Notices…………………………………………1
6-1 Figures of Wave Form……………………………………….26
6-2 Troubleshooting Flow Chart…………………...……………29
Chapter 7 Schematic Diagrams…………………………………………….33
Chapter 8 PCB Layout…………………………………………………………37
Chapter 9 Exploded Diagram and Mechanical Parts List…………………41
Chapter 10 Recommended Spare Parts List………………………………….43
Chapter 11 Complete Parts List……………………………………………...44
Appendix
Reader's Response
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1. Precautions and Notices
Prior to using this manual, please ensure that you have carefully followed all the
procedures outlined in the user manual for this product.
Read all of these instructions.
Save these instructions for later use.
Follow all warnings and instructions marked on the product.
Do not use this product near water.
This display should be installed on a solid horizontal base.
When cleaning, use only a neutral detergent cleaner with a soft damp cloth. Do not
spray with liquid or aerosol cleaners.
Do not expose this display to direct sunlight or heat. Hot air may cause damage to
the cabinet and other parts.
Adequate ventilation must be maintained to ensure reliable and continued
operation and to protect the display from overheating. Do not block ventilation slots
and openings with objects or install the display in a place where ventilation may be
hindered.
Do not install this display near a motor or transformer where strong magnetism is
generated. Images on the display will become distorted and the color irregular.
Do not allow metal pieces or objects of any kind fall into the display from ventilation
holes.
Slots and openings in the cabinet and the back or bottom are provided for
ventilation, to ensure reliable operation of the product and to protect it from
overheating, those openings must not be blocked or covered. The openings should
never be blocked by placing the product on a bed, sofa, rug, or other similar surface.
This product should never be placed near or over a radiator or heat register. This
product should not be placed in a built-in installation unless proper ventilation is
provided.
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FCC Statement
This equipment has been tested and found to comply with the limits of Class B digital device, pursuant to part
15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference
in a residential installation. This equipment generates and can radiate radio frequency energy, and if
not installed and used in accordance with the instructions, may cause harmful interference to radio
communication. However, there is no guarantee that the interference will not occur in a particular installation.
If this equipment does cause unacceptable interference to radio or television reception, which can be
determined by turning the equipment off and on, the user is encouraged to try to correct the interference by
one or more of following measures
Reorient or relocate the receiving antenna.
Increase the separation between equipment and receiver.
Connect into an outlet on circuit different from that to which the receiver is connected.
Consult the dealer or an experience radio/TV technician for help.
Κ
FCC Warning
To assure continued FCC compliance the user must use a grounded power supply cord and the provided
shielded video interface cable with bonded ferrite cores. Also, unauthorized change s or modifications to
ViewSonic products will void the usercs authority to operate this device. Thus ViewSonic will not be held
responsible for the product and its safety.
CE Certification
This device complies with the requirements of the ECC directive 89/3366/EEC with regard to
sElectromagnetic compatibility.s
Safety Guidelines
Caution: Use a power cable properly grounded. Always use the AC Mains cords listed below for each area
USA
Canada
Germany
Switzerland
Britain
Japan
In other areas, use AC cord which meets the local safety standards.
(UL)
(CSA)
(VDE)
(SEV)
(BASE/BS)
(Electric Appliance Control Act)
(TTL Compatible), Sync. On Green
HorizontalΚ30 to 62KHz
VerticalΚ50 to 75Hz
ConnectorAnalog: 15 Pin Mini D-Sub
Maximum Resolution1024x768
Video Bandwidth85 MHz nominal
Display Area304.1 mm (H) x 228.1 mm (V)
Power Voltage87~264VAC @ 47~63 Hz
Power Consumption40W max. (Adaptor plus monitor)
Operating ConditionsTemperature : 32л to 104л (0к to 40к)
Humidity : 10% to 90% (no condensation)
Altitude : 0 to +3,000 meters
Storage ConditionsTemperature : -4л to +140л (-20к to +60к)
Humidity : 10% to 90% (no condensation)
Altitude : 0 to +12,000 meters
NOTE: MANUFACTURER’S NAME MUST BE ON THE PRINTED SIDE FOR THE INVERTER BOARD TO
BE FACING UP.
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4-4 Theory of Circuit Operation
VG150m/mb is a multi-frequency and multi-mode color TFT LCD monitor. It supports different
resolutions including XGA, SVGA, VGA and other various high resolution up to 1024x768 for IBM, PC
compatibles, Power PC and Macintosh. VG150m uses a TFT LCD panel with a 0.297mm pixel pitch,
provides 16.7 millions color images.
As the previous block diagram illustrates, VG150m uses a highly integrated solution (U1: Mascot V)
that combines a high performance ADC with an advanced image process controller. Using advanced
image scaling algorithms, Mascot V has intelligently adaptive sub-algorithms that will automatically
optimize the display quality for different images – the text is sharper and the graphics is smoother.
Furthermore, each TFT LCD monitor uses the 24LC02 (U14) chip to provide DDC1/2B¥ with
Analog Plug&Play, the DDC data format is EDID v1.3.
Digital process and control system allows users to control OSD menu values to change monitor
settings. The follow sections are major part discussions of the TFT LCD display control board.
POWER SYSTEM
This product uses an external power adapter to provide DC+12V. It is the source of other voltages +5VX,
3.3VX, and VLCD.
The voltage of +5VX is produced by regulator LM2596-5V (U5) and external components that can realize DC
to DC conversion from +12V to +5V. For some chips (MPU, ADC) that are sensitive to any voltage variance,
we need LDO 1084-3.3V (U11) to produce a stable voltage 3.3VX.
There is still an important consideration about power consumption. We must greatly reduce the power
consumption even up to 90% in power saving mode. So we need to switch off the power that needn’t exist
when the system enters to this mode. We use the P-channel MOSFET TRLML6402 (Q1) to control the on/off
state of the panel’s power VLCD.
See FIG1-1.
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FIG1-1
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ANALOG SIGNAL INPUT and EDID
This product uses the internal function of Mascot V (U1) as a signal detector in order to support separate SYNC.
The analog input Horizontal and Vertical Synchronal signals pass through the Schmitt trigger buffer U4 to stabilize
then input to
Then
Mascot will detect the signal type if it is separate SYNC, composite SYNC or SOG. MPU (U6) reads the
input signal type from IIC protocol and does the correct procedure to generate the proper signals to the whole
system.
24LC02 (U14) chip provide DDC1/2B¥ with Analog Plug&Play, and the DDC data format is EDID v1.3.
See FIG1-2.
Mascot U1 pin38 VGA_VSYNC, pin39 VGA_HSYNC or pin40 SOGI and the image processing.
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FIG1-2
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ANALOG to DIGITAL CONVERSION and PROCESSING
General Description of Mascot
Mascot V is a highly integrated solution (U1) that combines a high performance ADC with an advanced image
process controller . Usin g a dvanced image scalin g alg orithms, Mascot V has inte lligently adapt ive sub -algori thms
that will automatically optimize the display quality for different images – the text is sharper a nd the graphics is
smoother.
The build-in analog interface includes an 80MHz, 8-bit 3-channel ADC, pre-amplifier, and VGA, allowing
seamless support to resolution from VGA to XGA. ADC function block diagram, see FIG3-1.
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FIG3-1 ADC Functional Block Diagram
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Clock Re-Generator Functional Block Diagram
FIG3-2 Clock Re-Generator
ADC Block Description
Variable Gain Amplifier (VGA)
The front-end circuit is designed to provide four major functions:
Provide AC coupled interface with single-ended R/G/B input signal, convert single-ended signal to
differential signal, and define common mode voltage.
Define CLAMPING voltage level with respect to ground for image brightness control.
Perform user programmable precision gain amplification.
Provide low impedance differential driver for ADC.
Phase Locked Loop (PLL) and Multi-Phase Generation
The phase locked loop (PLL) generates desired ADC sampling clock frequency (30 MHz to 80 MHz) from
external line clock CKREF. The exact frequency is register programmable and related to the input line clock
CKREF as follows:
Freq (PLL) = Freq (CKREF)* Ndiv <12:0>
To ease the graphic interface, a phase programmable output clock is also generated for external use. The exact
phase delay with respect to VCO output clock is register programmable and can be formulated as follows:
T
= IJ+Tclk * phase<4:0> / 32
DELAY
Where there is a systematic delay. Due to the periodic nature of the clock, user can practically program the ADC
sampling anywhere with respect to data in the step size of Tclk/32.
ADC
Based on the requirements for this ADC (high speed, low power and small size). The su b ranging architecture is
used to minimize the number of comparators. The interpolation technique is also used to reduce the number of
preamplifiers. T wo identical 8bit ADC converters are used to increase the throughput of sub ranging ADC to one
conversion per clock cycle.
Each ADC operates in two-step sub range, i.e. coarse (3 bits) and fine (5 bits). One to four interpolations is
performed in fine conversion step to minimize the number of preamplifier and to improve differential non-linearity
errors (DNL). In addition, in order to prevent potential error occurred during coarse conversion, digital error
correction technique is also used.
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Clock Re-Generator Functional Block Diagram
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FIG3-3 Clock Re-Generator
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Host Interface Control
Host interface controller is an interface between Mascot V and an external CPU. The access to Mascot V internal
internal registers, SRAM, programmable fonts, gamma tables, and ROM is performed by interface controller.
Mascot V provides single read/write and incremental read/write. Mascot V supports I2C bus and SPI protocols.
The bus protocol selection is determined by pin CONFIG[4], and Mascot V slave address is determined by pin
CONFIG[3:0].
GPIO (General Purpose Input/Output)
Gerenal Purpose Input/Output
Mascot V has provided three pins for general purpose input/output(GPIO); these pins can be programmed
as input or output pins; each GPIO pin has three registers for programming: GPIO Input/output control register,
GPIO output data register and GPIO input register; When GPIO is programmed as output pin, GPIO Input/output
control register is programmed as I (output), and the output data is provided by GPIO output data registe r; Whe n
programmed as input pin, GPIO Input/output control register is programmed as 0(input), the input value can be
accessed thrugh GPIO input register.
PWM (Pulse Width Modulation)
Mascot V has provided two sets of PWM, each PWM can generate programmable periodic square waves. The
generated wave consists of low period and high period. The low period and high period can be programmed
separately. Each period can be programmed to be 0Д255 basic cycles. The basic cycle is defined by design,
which also has four kinds of basic cycles can be chosen by programming.
Sync Processor
Sync Processor is used to detect input source (analog RGB or 24-bit RGB) and generate interruption to an
external CPU if input source changes. Then the CPU can program Mascot V correctly according to different input
sources. Sync Processor can generate interruption when there are frequency changes, Hsync and Vsync polarity
changes, and when there is no input signal. Sync processor provides h_counter and v_counter which are stored
in registers CR0B, CR0C, CR0D, and CR0E. V frequency can be calculated by (refclk/64) / v_counter or
187.5kHz/ v_counter for using 12MHz refclk. H frequency is calculated by (refclk/512k) * h_counter or 46.5Hz *
h_counter or 46.5Hz * h_counter for using 12MHz refclk.
Mascot V Sync Processor can also support composite Sync and sync-on-green inputs. If sync Processor detects
the input source is composite sync or sync-on-green input, Mascot V will separate composite sync or sync-on-green
to Hsync and Vsync.
Calibration
Calibration block performs position calibration, color calibration and phase calibration. In position cali bration,
non-zero data are detected horizontally and vertically. The Left most and right most positions and their
corresponding pitch can be found.Also Horizontal Total & Vertical Total are calculated.
Color calibration includes maximum color component detection, color read back from specified position and
maximum color difference in 2 neighboring pixels.
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In maximum color calibration, the pixel which has the maximum color component (based on CRB1[3:0]) can be
found. In color read back calibration, the color component (based on CRB[3:0]) for sp ecific position can be read
back. In maximum color difference calibration, for specific color component, color differences between every 2
neighboring pixels are compared from first till the last pair within a frame. The position which has the largest color
difference with its neighboring data is found.
Phase calibration can report pixel mismatch in up to 32 frames based on 2 specified points.
Capture Controller
Capture Controller is used to generate synchronization signals which are used for internal Mascot V. Within
Capture Controller block(FIG3-4), incoming data are processed, filtered, minimized and aligned with
controlling signals. Important internal synchronization signals include H_cnt, V_cnt, internal blank, and
end_of_frames.
FIG3-4 Capture Controller block
YUV to RGB Block
This block performs color space format conversion. Mascot V can convert 16 Bit YUV, RGB into 24 Bit RGB data
format.
Scaling Down
This block is used to conditionally drop incoming data if the incoming resolution is greater than 1024x768 which
is the physical resolution of the panel. A modified version of the Bresenham line-drawing algorithm is used to
determine which incoming data not to discard.
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Zoom Buffer
Zoom Buffer is used to store input data for scaling (zoom) function.
Zoom Buffer Write Control and Zoom Buffer Read Control
This Block generates write and read control signal to access zoom buffer.
Vertical Zoom Filter and Horizontal Zoom Filter
The
Mascot V scaling engine uses an advanced scaling technology and provides high quality scaling of text
images, graphic images and real-time video.
Display Control
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FIG3-5 Display Control
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On-Screen Display
Mascot V OSD display supports 256 different fonts at size of 12x18, 256 fonts contain 128 fixed fonts that are
stored in internal ROM, other 128 programmable fonts are stored in internal SRAM. OSD also supports Overlay
port interface and color look-up table with 4 color indices from external OSD.
gram listed below is the concept of how OSD retrieve and display OSD Font. See FIG3-6.
Dia
FIG3-6 On-Screen Display
When an OSD key has been pressed, firmware will detect the change and perform the procedure. Once firmware
starts “drawing” OSD, it will program the OSD code and attribute to the OSD SRAM. Chip will look-up the OSD
code then retrieve the character font data that corresponds to the code and then display the character on LCD panel.
There are 320 memory spaces from 0 to 319 in SRAM. It is sequentially mapped to the OSD frame started from
the upper-right corner and goes horizontally to the upper-left corner, and then move to the 2
nd
row and etc. endingat left-bottom corner. OSD frame are divided by 0Д9 in row, total is 32x10=320 characters.
Diagram listed below is the concept of how 24bit RGB OSD character is composed, see FIG3-7 OSD Display
Flow Chart.
Each OSD character font data that is read out from ROM table will use the 4-bit foreground and 4-bit
background color to determine its color. Use these 4-bit color indices to look-up the palette and select related15bit RGB foreground and background color. Add a 3bit "0" to each R, G, and B channel then generate 24-bit
RGB color for the OSD character.
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FIG3-7 OSD Display Flow Chart
Overlay Block
The Overlay Block mixes the scaled image data and osd data…
Overlay block mix mode is following 4 ways listed below:
The RGB offset function is used to adjust brightness of the RGB data. It provides a simple shift (positive or
negative) for each of the 3 color ch annels.
The Gamma Correction Block controls the linearity of RGB data.
It is used to adjust the RGB data according to the individual display characteristics and human eyes favorite. In
addition, the gamma table may be used for contrast, brightness, and white balance (temperature) adjustment.
The Gamma Correction linearity can be programmed through host interface.
Dithering Block
The Dithering Block generates output RGB data for TFT panels that have fewer than 8 bits for R, G and B input.
Mascot V uses a proprietary algorithm to generate smooth shade colors.
Panel Interface
Mascot V chip interfaces with all commonly used active matrix flat panel, e.g. 640x480, 800x600, and 1024x768 .
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FIG3-8 Mascot function block
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MPU
VG150m is controlled by a µ-controlled SM5964.
Description of SM5964
The SM5964 series product is an 8 – bit single chip microcontroller with 64KB flash & 1K byte RAM embedded.
It has In-System Programming (ISP) function and is a derivative of the 8052 microcontroller family. It has
5-channel SPWM build-in. User can access on-chip expanded RAM with easier and faster way by its ‘bank
mapping direct addressing mode’ scheme. With its hardware features and powerful instruction set, it’s straight
forward to make it a versatile and cost effective controller for those applications which demand up to 32 I/O pins
for PDIP package or up to 36 I/O pins for PLCC/QFP package, or applications which need up to 64K byte flash
memory either for program or for data or mixed.
To program the on-chip flash memory, a commercial writer is available to do it in parallel programming method.
The on-chip flash memory can be programmed in either parallel or serial interface with its ISP feature.
Ordering Information
SM5964ihhk (blank chip)
SM5964ihh – yyyk
I: process identifier {C, L}
hh: working clock in MHz {40}.
yyy: production code {001,…,999}
k: package type postfix {as below table}
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FIG4-1 SM5964 Pin Configuration
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Page 24
Features of SM5964
Working voltage: 4.5V through 5.5V
Program voltage: 5V
General 8052 family compatible
12 clocks per machine cycle
64K byte on chip flash memory with In-System Programming (ISP) capability
1024 byte on chip data RAM
Three 16 bit Timers/Counters
One Watch Dog Timer
Four 8-bit I/O ports for PDIP package
Four 8-bit I/O ports + one 4-bit I/O ports for PLCC or QFP package
Full duplex serial channel
Bit operation instruction
Page free jumps
8-bit Unsigned Division
8-bit Unsigned Multiply
BCD arithmetic
Direct Addressing
Indirect Addressing
Nested Interrupt
Two priority level interrupt
A serial I/O port
Power save modes: Idle mode and Power down mode
Code protection function
Low EMI (inhibit ALE)
Reset with address $0000 blank initiate ISP service program
ISP service program space configurable in N*512byte (N=0 to 8) size
Bank mapping direct addressing mode for access on-chip RAM
Five channel Specific PWM (SPWM) build-in
Direct LED drive output at port 4
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Page 25
FIG4-2 MPU Control Block
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AUDIO
VG150m/mb use AN7512 for stereo system, AN7512 is a dual 2-W BTL (Balanced
Transformer-Less) audio power amplifier IC. Speakers and microphone will stay on, while the rest of
the monitor is in power saving. See FIG5-1.
FIG5-1 Audio block diagram
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5. Adjustment
On Screen Display
OSD (On Screen Display) function is supported on each of the TFT
LCD analog display monitors and is controlled by easy to use Button 1,
Down, Up, Button 2, Power (Soft Switch), Mute, Volume – and Volume +.
(Power, 1, 2 and mute button should be one shot logic operation).
MAIN MENU Sub-FunctionValue
AUTO IMAGE ADJUST
CONTRAST/ BRIGHTNESS Adjustment Bar
COLOR ADJUST 6500K(default)
9300K (default)
USER
RED Adjustment Bar
GREEN Adjustment Bar
BLUE Adjustment Bar
INFORMATION
LANGUAGE ENGLISH
FRANCAIS
DEUTSCH
ITALIANO
ESPANOL
SUOMI
JAPANESE
CHINESE TRADITIONAL
CHINESE SIMPLIFIED
MANUAL IMAGE ADJUST H SIZE
H/V POSITION
FINE TUNE
SHARPNESS ON/OFF
SETUP MENU RESOLUTION NOTICE ENABLE/DISABLE
BACKGROUND ON/OFF
MEMORY RECALL
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OSD POSITION H/V Adjustment Bar
OSD TIME OUT 5S/15S/30S/60S
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OSD Lock short cuts function for the buttons
1. The OSD lock will be activated by pressing the front panel control buttons "(1), & (up)" for
10 seconds. If the user then tries to access the OSD by pressing any of the buttons "1",
"down", "up", "2" a message will appear on the screen for 3 seconds showing "OSD
Locked". The OSD lock will be deactivated by pressing the front panel control buttons "(1),
& (up)" again for 10 seconds.
Note 1: LED flashes orange when the OSD has been Locked or Unlocked.
2. The power button lock will be activated by pressing the front panel control buttons "(1), &
(down)" for 10 seconds. Locking the power button means that the user won't be able to
turn off the LCD while the power button is locked. If the user presses the power button
while it is locked, a message will appear on the screen for 3 seconds showing "Power
Button Locked". It also means that with the power button locked, the LCD would
automatically turn back "On" when power is restored after a power failure. If the power
button is not in the locked mode, then power should return to its previous state when
power is restored after a power failure. The power button lock will be deactivated by
pressing the front panel control buttons "(1), & (down)" again for 10 seconds.
Note: LED flashes orange when the power button has been Locked or Unlocked.
Short Cut Keys:
Auto Image Adjust: press button [2]
Contrast / Brightness: press buttons Up or Down
[DOWN] + [UP] arrows = recall Contrast and Brightness while in the Contrast or Brightness
adjustment, or when the OSD is not open.
[Audio-] + [Audio+] = recall volume to 50% whether or not the OSD is open.
OSD lock and unlock: press two buttons [1] & [Up] simultaneously for 10 seconds.
Power lock and unlock: press two buttons [1] & [Down] simultaneously for 10 seconds.
Memory Recall is to recall the following functions to factory setting:
Contrast, brightness, h size, h/v position, color temperature @ 6500K, OSD position,
sharpness, OSD timeout, volume, and Resolution Notice.
Note: Memory Recall should have no effect for Mute, Language, or User Color Settings.
B-MB-0201-0725 3150-1102-0150 LCD MAIN BD ASS'Y VG150m(ADI)(MRT)
ITEMVIEWSONIC P/NDESCRIPTIONREFERENCE
NUMBER
1 E-C-0404-4794E/C GEN. 330UF 16V 105' 8*9mm F (SX TYPE)0101-0331-1211C1101
2E/C GEN. 220uF 16V 105' 8*9mm F (SX TYPE)0101-0221-1211C151
3E/C GEN. 220uF 16V 105' 8*9mm F (SX TYPE)0101-0221-1211C291
4E/C GEN. 220uF 16V 105' 8*9mm F (SX TYPE)0101-0221-1211C371
5E/C GEN. 10UF 16V 105' 4*7mm F (SX TYPE)0101-0100-1211C471
6E/C GEN. 10UF 16V 105' 4*7mm F (SX TYPE)0101-0100-1211C481
7 E-C-0404-4794E/C GEN. 330UF 16V 105' 8*9mm F (SX TYPE)0101-0331-1211C491
8E/C GEN. 220uF 16V 105' 8*9mm F (SX TYPE)0101-0221-1211C571
9E/C GEN. 330UF 25V 105' N-F0101-1331-1310C661
10E/C GEN. 330UF 25V 105' N-F0101-1331-1310C671
11 E-C-0404-4794E/C GEN. 330UF 16V 105' 8*9mm F (SX TYPE)0101-0331-1211C711
12 E-C-0404-4794E/C GEN. 330UF 16V 105' 8*9mm F (SX TYPE)0101-0331-1211C731
13E/C GEN. 220uF 16V 105' 8*9mm F (SX TYPE)0101-0221-1211C741
14E/C GEN. 220uF 16V 105' 8*9mm F (SX TYPE)0101-0221-1211C761
15E/C GEN. 220uF 16V 105' 8*9mm F (SX TYPE)0101-0221-1211C901
16 E-D-0403-1743SCHOTTKY DIODE SB340 T0390-6000-9172D41
17 E-FS-0410-0084PICO FUSE 125V 3.5A 3*7MM (R25103.5)0182-1352-3703FUSE11
18 E-L-0407-1057DRUM CORE L:70UH 2A(10*16)0361-1000-0120L171
19 E-L-0407-0547FERRITE CORE RH 3.5X6X1.0(W)X20370-0000-1010L71
20 M-MS-0808-7905CONN. B TO FPC IL-FHR 36P (IL-FHR-F36S-HF)0303-1000-0363P11
21 M-MS-0808-8055CONN. B TO FPC FH12-36S-0.5SH 36PIN0303-1000-0364CS
22 M-MS-0808-2118WAFER 2.00MM 4P 90' KINK0451-2000-0464P101
23 M-MS-0808-8056CONN. B TO FPC IL-FHR 40P (IL-FHR-F40S-HF)0303-1000-0403P21
24 M-MS-0808-8057CONN. B TO FPC FH12-40S-0.5SH 40PIN0303-1000-0404CS
25 M-MS-0808-1765WAFER 2.00MM 5P 90' KINK0451-2000-0564P31
26WAFER 2.00MM 11P 90' KINK0451-2000-1164P51
27 M-MS-0808-8054DC POWER JACK 180 °0302-1360-0026P61
28PHONE JACK 3.5 ψ 7PIN 180' (PC99) +SHIELDING0302-0350-0070P71
29 M-MS-0808-8053D-SUB FEMALE 180' 15P 3ROW 5mm (PC99)0300-1213-3150P81
30 E-IC-0401-2522IC AN7512 DIP 16PIN0430-4007-2168U71
31 E-IC-0401-1888IC 24LC08B/P DIP 8PIN0430-3000-4117U81
32 E-IC-0401-2513IC ST24C08 DIP 8PIN0430-3000-4107CS
33 E-IC-0401-2514IC S24C08ADP DIP 8PIN0430-3000-4147CS
34 E-IC-0401-2515IC M24C08-BN6 DIP 8PIN0430-3000-6107CS
35 M-MS-0808-0305IC SOCKET 2.54MM 8PIN0201-2540-8000U8S1
36 E-T-0408-0465X'TAL 12MHZ 49/US CL:30PF0280-1200-0015Y11
37 E-T-0408-0465X'TAL 12MHZ 49/US CL:30PF0280-1200-0015Y21
38ARRAY CAP 22P 50V NPO 8PIN0111-5220-5111CP11
39ARRAY CAP 22P 50V NPO 8PIN0111-5220-5111CP101
40ARRAY CAP 22P 50V NPO 8PIN0111-5220-5111CP111
41ARRAY CAP 22P 50V NPO 8PIN0111-5220-5111CP121
42ARRAY CAP 22P 50V NPO 8PIN0111-5220-5111CP21
43ARRAY CAP 22P 50V NPO 8PIN0111-5220-5111CP31
44ARRAY CAP 22P 50V NPO 8PIN0111-5220-5111CP41
45ARRAY CAP 22P 50V NPO 8PIN0111-5220-5111CP51
46ARRAY CAP 22P 50V NPO 8PIN0111-5220-5111CP61
47ARRAY CAP 22P 50V NPO 8PIN0111-5220-5111CP71
48ARRAY CAP 22P 50V NPO 8PIN0111-5220-5111CP81
49ARRAY CAP 22P 50V NPO 8PIN0111-5220-5111CP91
50 E-C-0404-3712C/M MULTI. 0.1UF 25V Y5V 06030111-3104-2536C11
3150-1112-0150 LCD MAIN BD ASS'Y VG150mb(ADI)(MRT)
ITEMVIEWSONIC P/NDESCRIPTIONREFERENCE
NUMBER
1 E-C-0404-4794E/C GEN. 330UF 16V 105' 8*9mm F (SX TYPE)0101-0331-1211C1101
2E/C GEN. 220uF 16V 105' 8*9mm F (SX TYPE)0101-0221-1211C151
3E/C GEN. 220uF 16V 105' 8*9mm F (SX TYPE)0101-0221-1211C291
4E/C GEN. 220uF 16V 105' 8*9mm F (SX TYPE)0101-0221-1211C371
5E/C GEN. 10UF 16V 105' 4*7mm F (SX TYPE)0101-0100-1211C471
6E/C GEN. 10UF 16V 105' 4*7mm F (SX TYPE)0101-0100-1211C481
7 E-C-0404-4794E/C GEN. 330UF 16V 105' 8*9mm F (SX TYPE)0101-0331-1211C491
8E/C GEN. 220uF 16V 105' 8*9mm F (SX TYPE)0101-0221-1211C571
9E/C GEN. 330UF 25V 105' N-F0101-1331-1310C661
10E/C GEN. 330UF 25V 105' N-F0101-1331-1310C671
11 E-C-0404-4794E/C GEN. 330UF 16V 105' 8*9mm F (SX TYPE)0101-0331-1211C711
12 E-C-0404-4794E/C GEN. 330UF 16V 105' 8*9mm F (SX TYPE)0101-0331-1211C731
13E/C GEN. 220uF 16V 105' 8*9mm F (SX TYPE)0101-0221-1211C741
14E/C GEN. 220uF 16V 105' 8*9mm F (SX TYPE)0101-0221-1211C761
15E/C GEN. 220uF 16V 105' 8*9mm F (SX TYPE)0101-0221-1211C901
16 E-D-0403-1743SCHOTTKY DIODE SB340 T0390-6000-9172D41
17 E-FS-0410-0084PICO FUSE 125V 3.5A 3*7MM (R25103.5)0182-1352-3703FUSE11
18 E-L-0407-1057DRUM CORE L:70UH 2A(10*16)0361-1000-0120L171
19 E-L-0407-0547FERRITE CORE RH 3.5X6X1.0(W)X20370-0000-1010L71
20 M-MS-0808-7905CONN. B TO FPC IL-FHR 36P (IL-FHR-F36S-HF)0303-1000-0363P11
21 M-MS-0808-8055CONN. B TO FPC FH12-36S-0.5SH 36PIN0303-1000-0364CS
22 M-MS-0808-2118WAFER 2.00MM 4P 90' KINK0451-2000-0464P101
23 M-MS-0808-8056CONN. B TO FPC IL-FHR 40P (IL-FHR-F40S-HF)0303-1000-0403P21
24 M-MS-0808-8057CONN. B TO FPC FH12-40S-0.5SH 40PIN0303-1000-0404CS
25 M-MS-0808-1765WAFER 2.00MM 5P 90' KINK0451-2000-0564P31
26WAFER 2.00MM 11P 90' KINK0451-2000-1164P51
27 M-MS-0808-8054DC POWER JACK 180 °0302-1360-0026P61
28PHONE JACK 3.5 ψ 7PIN 180' (PC99) +SHIELDING0302-0350-0070P71
29 M-MS-0808-8053D-SUB FEMALE 180' 15P 3ROW 5mm (PC99)0300-1213-3150P81
30 E-IC-0401-2522IC AN7512 DIP 16PIN0430-4007-2168U71
31 E-IC-0401-1888IC 24LC08B/P DIP 8PIN0430-3000-4117U81
32 E-IC-0401-2513IC ST24C08 DIP 8PIN0430-3000-4107CS
33 E-IC-0401-2514IC S24C08ADP DIP 8PIN0430-3000-4147CS
34 E-IC-0401-2515IC M24C08-BN6 DIP 8PIN0430-3000-6107CS
35 M-MS-0808-0305IC SOCKET 2.54MM 8PIN0201-2540-8000U8S1
36 E-T-0408-0465X'TAL 12MHZ 49/US CL:30PF0280-1200-0015Y11
37 E-T-0408-0465X'TAL 12MHZ 49/US CL:30PF0280-1200-0015Y21
38ARRAY CAP 22P 50V NPO 8PIN0111-5220-5111CP11
39ARRAY CAP 22P 50V NPO 8PIN0111-5220-5111CP101
40ARRAY CAP 22P 50V NPO 8PIN0111-5220-5111CP111
41ARRAY CAP 22P 50V NPO 8PIN0111-5220-5111CP121
42ARRAY CAP 22P 50V NPO 8PIN0111-5220-5111CP21
43ARRAY CAP 22P 50V NPO 8PIN0111-5220-5111CP31
44ARRAY CAP 22P 50V NPO 8PIN0111-5220-5111CP41
45ARRAY CAP 22P 50V NPO 8PIN0111-5220-5111CP51
46ARRAY CAP 22P 50V NPO 8PIN0111-5220-5111CP61
47ARRAY CAP 22P 50V NPO 8PIN0111-5220-5111CP71
48ARRAY CAP 22P 50V NPO 8PIN0111-5220-5111CP81
49ARRAY CAP 22P 50V NPO 8PIN0111-5220-5111CP91
50 E-C-0404-3712C/M MULTI. 0.1UF 25V Y5V 06030111-3104-2536C11