Circle
241
on
inquiry card.
DA.TA
PLOTTING
SOFTWARE
FOR
MICROS
'
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$ IC,l.I'
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21
Programs
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BASIC
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Apple
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PIE CHARTS • BAR CHARTS
STOCK MARKET CHARTS
3D SURFACES
• HISTOGRAMS
LOG PLOTS •
CURVE
FiniNG
REGRESSION ANALYSIS
DATA MANAGEMENT
STATISTICAL ANALYSIS
TEXT ON GRAPH ICS
All
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.3
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Th
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Structural
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230 November 1982 ©
BYTE Pub
lications Inc
Pin Signal 1
/0
Description
50
A19 1/0
Bu
ffered-address bits 8 to 19. These
1 A18
1
/0
lines
are driv
en
fr om the 8088 during
49
A1
7 1
/0
normal operation a
nd
are valid from
2
A16
1/0
the falling edge of address-latch
48
A15
1
/0
enable (ALE
) to the rising edge of t
he
3
A14
1
/0
next
ALE
. If an external device takes
47
A13 1
/0
cont rol of the system v
ia
HOLD and
4 A12
1
/0
HOLD ACKNOWLEDGE, the
se
lines
46 A
11
I
/O
are tri-stat
ed.
5 A10 1
/0
45
A9
1/
0
6
A8
I
/O
29
BD
7
I
/O
Time multiplexed buffered addressl
22
BD
6 I/O
data bus. During norm al operation,
28 B
D5
1
/0
the lower 8 bits of addre
ss (AD
O-
23 B
D4
I
/O
AD7) are valid
on
the falling edge of
27
BD
3
I/
O
ALE.
24
BD
2
I/
O
26
BD
1
I/
O
25 B
OO
I/O
9 ALE
0
Buffered addre
ss-
latc h enable. Processor signa
l that indicates
BDO-BD
7 cont ain valid addresses. Typically used to l
atc
h low-
orde r 8 bits of address.
11 RD
0
Buffered read strobe . Processor signal ind icating
'a read cycle.
14
WR
0 Buffered write strobe. Processor signal
in
dicating a write
cyc le.
8
D
EN
0 Buffered data enab
le. Provid
ed by the processor for use
as
an
enable for transceivers.
33
DL
ATCH
0 Data latch. The falling edge of this signal m
ay
be used
to
st robe data genera
ted from a processor read access.
30
EX
TI
O
Externa l I/O. Contr
ol
line that prevents internal data-bus bu
ffers from conflicting with external buffers when mapping external I
/O into address space EOOOO
to EFFFF hexadecimal.
CS
EN
should be used as a control signal to disabl
e internal
buffe rs via EXTIO and enable external buffers if usin
g address
space
EOOOO
to EFFFF. Addresses used
by the
system cannot
be
disabled by EXTIO.
19
CS
EN
0 Chip
se
lect enable.
This line is synchronized to PHASE2.
It is
true from a
fa
lling edge of
PHA
SE2 to the next fall
ing
edge of
PHASE
2,
when address space E
OOOO
to EFFFF hexadecimal
is accessed.
40 CLK15B
0
15-MH
z clock. S
ign
al from which all system timing
is
derived.
Its period is 66.6 ns with a 5
0%
± 1
0%
duty cycle.
38 CL
K5
0
5-M
Hz clock. Signal is
in phase with the 8088 clock input. I
ts
period
is
200
ns
with a 33% duty
cyc
le.
20
PHASE2
0
1-MHz clock. Signal
is
asynchronous with CLK5.
Its period
is
11'
s with a 40/60% duty cycle. Useful to interface 6800-type
I/
O c ircuit s.
21
XA
CK
External acknowledge. This line
is normally hi
gh and may
be
pulled low by external devices resulting in pulli
ng
the 8088
READ
Y input low, gener ating wait states.
This line is resyn-
chro
nized by the system logi
c.
17
HO
LD
Input to the 8088. This is an external
request for control of t
he
system buses.
18
HLDA
0 Buff ered ho
ld
acknowledge.
Sys
tem respon
se
to HOLD re-
ques
t. When true (high) the following signals are tri-stated:
A8-A19,
BDO-BD7, ALE,
10
1M,
RD, WR,DT
IR,
DEN
, SSO, and
INTA
DLATCH is co ntrolled by extern al
logic.
41
RE
ADY
0 Status line. This line reflects
the sy
nchronized
READY in
put to
th
e 8088.
10
10 iM
0 Buffered 8088 sta
tu
s line. Distinguishes between a memory or
I
/O
bus cycle.
7
SSO
0 Buffered 8088 status line.
Conti
nued on page 234
Tabl
e 1: The s
ig
nal names and descriptions for the Victor 9000 expansio n
bus
. The
expansion bus
is
basicall
y a buffe red extension of the
sys
tem's 8088 processor plus
add
itional timi ng
and contr
ol signals re
quir
ed to interface the system. The expansion
bus consists
of a mult
iplexed buffered data bus (BDO-BD7
),
a buffered
addr
ess bus
(A8-A19), and vari
ous timing, control, interrupt,
and powe
r lines.