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vicorpower.com 800-735-6200 V•I Chip Voltage Transformation Module V048K060T040 Rev. 1.0
Page 1 of 15
PRELIMINARY
Product Description
The V048K060T040 V•I Chip Voltage Transformation
Module (VTM) excels at speed, density and efficiency to
meet the demands of advanced DSP, FPGA, and ASIC at
the point of load (POL) while providing isolation from
input to output. It achieves a response time of less than
1 µs and delivers up to 40.0 A in a volume of less than
0.25 in
3
with unprecedented efficiency. It may be
paralleled to deliver hundreds of amps at an output
voltage settable from 3.25 to 6.87 Vdc.
The VTM V048K060T040’s nominal output voltage is
6 Vdc from a 48 Vdc input Factorized Bus, Vf, and is
controllable from 3.25 to 6.87 Vdc at no load, and from
2.95 to 6.60 Vdc at full load, over a Vf input range of
26 to 55 Vdc. It can be operated either open- or closedloop depending on the output regulation needs of the
application. Operating open-loop, the output voltage
tracks its Vf input voltage with a transformation ratio,
K = 1/8 , for applications requiring a programmable
output voltage at high current and high efficiency.
Closing the loop back to an input Pre-Regulation Module
(PRM) or DC-DC converter enables tight load regulation.
The 6 V VTM achieves a power density of 974 W/in
3
in a
V•I Chip package compatible with standard pick-andplace and surface mount assembly processes. The
V•I Chip BGA package supports in-board mounting with
a low profile of 0.16" (4 mm) over the board. A J-lead
package option supports on-board surface mounting
with a profile of only 0.25" (6 mm) over the board. The
VTM’s fast dynamic response and low noise eliminate the
need for bulk capacitance at the load, substantially
increasing the POL density while improving reliability and
decreasing cost.
Parameter Values Unit Notes
+In to -In -1.0 to 60 Vdc
+In to -In 100 Vdc For 100 ms
PC to -In -0.3 to 7.0 Vdc
VC to -In -0.3 to 19.0 Vdc
+Out to -Out -0.1 to 15.0 Vdc
Isolation voltage 2,250 Vdc Input to Output
Output current 40.0 A Continuous
Peak output current 60.0 A For 1 ms
Output power 240 W Continuous
Peak output power 360 W For 1 ms
Case temperature 208 °C During reflow
Operating junction temperature
(1)
-40 to 125 °C T - Grade
-55 to 125 °C M - Grade
Storage temperature
-40 to 150 °C T - Grade
-65 to 150 °C M - Grade
V•I ChipTM– VTM
Voltage Transformation Module
•48V to 6 V V•I Chip Converter
• 40.0 A (60.0 A for 1 ms)
•High density – 974 W/in
3
•Small footprint – 220 W/in
2
• Low weight – 0.5 oz (14 g)
• Pick & Place / SMD
• 125°C operation
•1 µs transient response
• 3.5 million hours MTBF
•Typical efficiency 95%
• No output filtering required
• Surface mount BGA or J-Lead
packages
V048K060T040
Actual size
©
VTM
Note:
(1) The referenced junction is defined as the semiconductor having the highest temperature.
This temperature is monitored by a shutdown comparator.
K indicates BGA configuration. For other
mounting options see Part Numbering below.
Output Current
Designator
(=I
OUT)
V 048 K 060 T 040
Voltage
Transformation
Module
Input Voltage
Designator
Product Grade Temperatures (°C)
Grade Storage Operating
T -40 to150 -40 to125
M -65 to150 -55 to125
Configuration Options
F=On-board (Figure 15)
K=In-board (Figure 14)
Output Voltage
Designator
(=VOUT x10)
Part Numbering
Vf = 26 - 55 V
V
OUT = 3.25 - 6.87 V
I
OUT
= 40.0 A
K = 1/8
R
OUT = 7.5 mΩ max
Absolute Maximum Ratings
查询V048F060M040供应商
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vicorpower.com 800-735-6200 V•I Chip Voltage Transformation Module V048K060T040 Rev. 1.0
Page 2 of 15
V•I Chip Voltage Transformation Module
PRELIMINARY
Electrical Specifications
Parameter Min Typ Max Unit Note
Input voltage range 26 48 55 Vdc Operable down to zero V with VC voltage applied
Input dV/dt 1 V/µs
Input overvoltage turn-on 55.0 Vdc
Input overvoltage turn-off 59.0 Vdc
Input current 5.5 Adc
Input reflected ripple current 275 mA p-p Using test circuit in Figure 16; See Figure 1
No load power dissipation 2.3 3.5 W
Internal input capacitance 4.0 µF
Internal input inductance 20 nH
Input Specs (Conditions are at 48 Vin, full load, and 25°C ambient unless otherwise specified)
Parameter Min Typ Max Unit Note
Output voltage
3.25 6.87 Vdc No load
2.95 6.60 Vdc Full load
Rated DC current 0 40.0 Adc 26 - 55 VIN
Peak repetitive current 60.0 A
Max pulse width 1ms, max duty cycle 10%,
baseline power 50%
Short circuit protection set point 42.8 49.9 55.0 Adc Module will shut down
Current share accuracy 5 10 % See Parallel Operation on Page 10
Efficiency
Half load 94.3 95.8 % See Figure 3
Full load 93.8 94.8 % See Figure 3
Internal output inductance 1.1 nH
Internal output capacitance 55.0 µF Effective value
Output overvoltage setpoint 6.9 Vdc Module will shut down
Output ripple voltage
No external bypass 230 300 mV See Figures 2 and 5
10 µF bypass capacitor 12.5 mV See Figure 6
Effective switching frequency 2.0 2.5 3.0 MHz Fixed, 1.25 MHz per phase
Line regulation
K 0.1238 1/8 0.1263 VOUT = K•VIN at no load
Load regulation
ROUT
5.5 7.5 mΩ See Figure 19
Transient response
Voltage overshoot 180 mV 40.0 A load step with 100 µF CIN; See Figures 7 and 8
Response time 200 ns See Figures 7 and 8
Recovery time 1 µs See Figures 7 and 8
Output Specs (Conditions are at 48 Vin, full load, and 25°C ambient unless otherwise specified)
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vicorpower.com 800-735-6200 V•I Chip Voltage Transformation Module V048K060T040 Rev. 1.0
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PRELIMINARY
Figure 1— Input reflected ripple current at full load and 48 Vf.
Figure 3— Efficiency vs. output current at 48 Vf.
Figure 4—Power dissipation as a function of output current at 48 Vf.
Waveforms
Figure 6—Output voltage ripple at full load and 6 Vout with 10 µF ceramic
external bypass capacitance and 20 nH distribution inductance.
Figure 5— Output voltage ripple at full load and 6 Vout; without any
external bypass capacitor.
Figure 2— Output voltage ripple vs. output current at 6 Vout with no POL
bypass capacitance.
Electrical Specifications (continued)
Output Ripple (mVpk-pk)
Ripple vs. Output Current
220
200
180
160
140
120
100
80
60
40
20
0481216 20 24 28 32 36 40
Output Current (A)
Efficiency vs. Output Current
96
95.5
95
94.5
94
93.5
93
Efficiency (%)
92.5
92
91.5
91
04812162024 28323640
Output Current (A)
Power Dissipation
14
13
12
11
10
9
8
7
6
5
4
Power Dissipation (W)
3
2
0481216 20 24 28 32 36 40
Output Current (A)
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vicorpower.com 800-735-6200 V•I Chip Voltage Transformation Module V048K060T040 Rev. 1.0
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V•I Chip Voltage Transformation Module
PRELIMINARY
Parameter Min Typ Max Unit Note
Primary Control (PC)
DC voltage 4.8 5.0 5.2 Vdc
Module disable voltage 2.4 2.5 Vdc
Module enable voltage 2.5 2.6 Vdc VC voltage must be applied when module is enabled using PC
Current limit 2.4 2.5 2.9 mA Source only
Disable delay time 10 µs PC low to Vout low
VTM Control (VC)
External boost voltage 12.0 14.0 19.0 Vdc Required for VTM start up without PRM
External boost duration 10 ms Vin > 26 Vdc. VC must be applied continuously
if Vin < 26 Vdc.
Auxiliary Pins (Conditions are at 48 Vin, full load, and 25°C ambient unless otherwise specified)
Parameter Min Typ Max Unit Note
MTBF
MIL-HDBK-217F 3.5 Mhrs 25°C, GB
Isolation specifications
Voltage 2,250 Vdc Input to Output
Capacitance 3,000 pF Input to Output
Resistance 10 MΩ Input to Output
Agency approvals (pending)
cTÜVus UL/CSA 60950, EN 60950
CE Mark Low voltage directive
Mechanical parameters See Mechanical Drawing, Figures 10 and 12
Weight 0.5 / 14.0 oz / g
Dimensions(BGA version)
Length 1.26 / 32 in / mm
Width 0.85 / 21.5 in / mm
Height 0.23 / 5.9 in / mm
General
Figure 7— 0-40.0 A step load change with 100 µF input capacitance and
no output capacitance.
Figure 8— 40.0-0 A step load change with 100 µF input capacitance and
no output capacitance.
Electrical Specifications (continued)
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vicorpower.com 800-735-6200 V•I Chip Voltage Transformation Module V048K060T040 Rev. 1.0
Page 5 of 15
PRELIMINARY
V•I Chip Stress Driven Product Qualification Process
Symbol Parameter Min Typ Max Unit Note
Over temperature shutdown 125 130 135 °C Junction temperature
Thermal capacity 0.61 Ws/°C
RθJC Junction-to-case thermal impedance 1.1 °C/W
RθJB Junction-to-BGA thermal impedance 2.1 °C/W
RθJA
Junction-to-ambient
(1)
6.5 °C/W
RθJA
Junction-to-ambient
(2)
5.0 °C/W
Thermal
Notes:
(1) V048K060T040 surface mounted in-board to a 2" x 2" FR4 board, 4 layers 2 oz Cu, 300 LFM.
(2) V048K060T040 with optional 0.25"H Pin Fins surface mounted on FR4 board, 300 LFM.
Test Standard Environment
High Temperature Operational Life (HTOL) JESD22-A-108-B 125°C, Vmax, 1,008 hrs
Temperature cycling JESD22-A-104B -55°C to 125°C, 1,000 cycles
High temperature storage JESD22-A-103A 150°C, 1,000 hrs
Moisture resistance JESD22-A113-B Moisture sensitivity Level 5
Temperature Humidity Bias Testing (THB) EIA/JESD22-A-101-B 85°C, 85% RH, Vmax, 1,008 hrs
Pressure cooker testing (Autoclave) JESD22-A-102-C 121°C, 100% RH, 15 PSIG, 96 hrs
Highly Accelerated Stress Testing (HAST) JESD22-A-110B 130°C, 85% RH, Vmax, 96 hrs
Solvent resistance/marking permanency JESD22-B-107-A Solvents A, B & C as defined
Mechanical vibration JESD22-B-103-A 20g peak, 20-2,000 Hz, test in X, Y & Z directions
Mechanical shock JESD22-B-104-A 1,500g peak 0.5 ms pulse duration, 5 pulses in 6 directions
Electro static discharge testing – human body model EIA/JESD22-A114-A Meets or exceeds 2,000 Volts
Electro static discharge testing – machine model EIA/JESD22-A115-A Meets or exceeds 200 Volts
Highly Accelerated Life Testing (HALT)
Per Vicor Internal
Operation limits verified, destruct margin determined
Test Specification
(1)
Dynamic cycling
Per Vicor internal
Constant line, 0-100% load, -20°C to 125°C
test specification
(1)
Note:
(1) For details of the test protocols see Vicor’s website.
Test Standard Environment
BGA solder fatigue evaluation
IPC-9701 Cycle condition: TC3 (-40 to +125°C)
IPC-SM-785 Test duration: NTC-B (500 failure free cycles)
Solder ball shear test IPC-9701 Failure through bulk solder or copper pad lift-off
V•I Chip Ball Grid Array Interconnect Qualification
Electrical Specifications
(continued)
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vicorpower.com 800-735-6200 V•I Chip Voltage Transformation Module V048K060T040 Rev. 1.0
Page 6 of 15
V•I Chip Voltage Transformation Module
PRELIMINARY
Pin/Control Functions
+IN/-IN DC Voltage Ports
The VTM input should not exceed the maximum specified. Be aware of
this limit in applications where the VTM is being driven above its
nominal output voltage. If less than 26 Vdc is present at the +In and -In
ports, a continuous VC voltage must be applied for the VTM to process
power. Otherwise VC voltage need only be applied for 10 ms after the
voltage at the +In and -In ports has reached or exceeded 26 Vdc. If the
input voltage exceeds the overvoltage turn-off, the VTM will shutdown.
The VTM does not have internal input reverse polarity protection.
Adding a properly sized diode in series with the positive input or a
fused reverse-shunt diode will provide reverse polarity protection.
TM – For Factory Use Only
VC – VTM Control
The VC port is multiplexed. It receives the initial V
CC voltage from an
upstream PRM, synchronizing the output rise of the VTM with the
output rise of the PRM. Additionally, the VC port provides feedback to
the PRM to compensate for the VTM output resistance. In typical
applications using VTMs powered from PRMs, the PRM’s VC port
should be connected to the VTM VC port.
In applications where a VTM is being used without a PRM, 14 V must
be supplied to the VC port for as long as the input voltage is below 26 V
and for 10 ms after the input voltage has reached or exceeded 26 V. The
VTM is not designed for extended operation below 26 V. The VC port
should only be used to provide V
CC voltage to the VTM during startup.
PC – Primary Control
The Primary Control (PC) port is a multifunction port for controlling the
VTM as follows:
Disable – If PC is left floating, the VTM output is enabled. To
disable the output, the PC port must be pulled lower than 2.4 V,
referenced to -In. Optocouplers, open collector transistors or relays
can be used to control the PC port. Once disabled, 14 V must be
re-applied to the VC port to restart the VTM.
Primary Auxiliary Supply – The PC port can source up to 2.4 mA
at 5 Vdc.
+OUT/-OUT DC Voltage Output Ports
The output and output return are through two sets of contact
locations. The respective +Out and –Out groups must be connected in
parallel with as low an interconnect resistance as possible. Within the
specified input voltage range, the Level 1 DC behavioral model shown
in Figure 19 defines the output voltage of the VTM. The current source
capability of the VTM is shown in the specification table.
To take full advantage of the VTM, the user should note the low output
impedance of the device. The low output impedance provides fast
transient response without the need for bulk POL capacitance. Limitedlife electrolytic capacitors required with conventional converters can be
reduced or even eliminated, saving cost and valuable board real estate.
Figure 9—VTM BGA configuration
Signal Name BGA Designation
+In A1-L1, A2-L2
–In AA1-AL1, AA2-AL2
TM P1, P2
VC T1, T2
PC V1, V2
+Out
A3-G3, A4-G4,
U3-AC3, U4-AC4
–Out
J3-R3, J4-R4,
AE3-AL3, AE4-AL4
+Out
-Out
+Out
-Out
4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
Bottom View
+In
TM
VC
PC
-In
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vicorpower.com 800-735-6200 V•I Chip Voltage Transformation Module V048K060T040 Rev. 1.0
Page 7 of 15
PRELIMINARY
Mechanical Drawings
Figure 10—VTM BGA mechanical outline; Inboard mounting
Figure 11— VTM BGA PCB land/VIA layout information; Inboard mounting
IN-BOARD MOUNTING
BGA surface mounting requires a
cutout in the PCB in which to recess the V•I Chip
SOLDER BALL
#A1 INDICATOR
32,0
1.26
3,9
0.15
INPUT
21,5
0.85
TOP VIEW (COMPONENT SIDE)
15,6
0.62
OUTPUT
SEATING PLANE
5,9
0.23
1,00
0.039
0.020
0.51
1,00
0.039
SOLDER BALL
TYP
16,0
0.63
mm
inch
OUTPUT
(106) X Ø
28,8
1.13
1,6
0.06
NOTES:
1- DIMENSIONS ARE .
2- UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:
.X/[.XX] = +/-0.25/[.01]; .XX/[.XXX] = +/-0.13/[.005]
3- PRODUCT MARKING ON TOP SURFACE
18,00
0.709
9,00
0.354
C
L
BOTTOM VIEW
1,00
0.039
SOLDER BALL #A1
INPUT
C
L
15,00
0.591
1,00
0.039
30,00
1.181
1,00
0.039
0.354
+IN
PC
-IN VC TM
(2) X
10,00
0.394
20,00
0.787
SOLDER PAD #A1
17,00
15,00
0.669
0.591
(106) X ø
SOLDER MASK
DEFINED PAD
13,00
0.512
0,51
0.020
18,00
0.709
9,00
PCB CUTOUT
8,08
0.318
16,16
0.636
1
31
1,00
0.039
+OUT1
-OUT1
+OUT2 -OUT2
(4) X R
8,00
0.315
1,6
0.06
16,00
0.630
(4) X
24,00
0.945
6,00
0.236
0,37
0.015
29,26
1.152
1,50
0.059
1,00
( )
0.039
0,50
0.020
0,51
( ø )
0.020
SOLDER MASK
DEFINED PADS
RECOMMENDED LAND AND VIA PATTERN
NOTES:
1- DIMENSIONS ARE .
2- UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:
.X/[.XX] = +/-0.25/[.01]; .XX/[.XXX] = +/-0.13/[.005]
(COMPONENT SIDE SHOWN)
mm
inch
0,53
ø PLATED VIA
0.021
CONNECT TO
INNER LAYERS
0,50
0.020
1,00
0.039
1,00
( )
0.039
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vicorpower.com 800-735-6200 V•I Chip Voltage Transformation Module V048K060T040 Rev. 1.0
Page 8 of 15
V•I Chip Voltage Transformation Module
PRELIMINARY
Mechanical Drawings (continued)
Figure 12—VTM J-Lead mechanical outline; Onboard mounting
Figure 13— VTM J-Lead PCB land layout information; Onboard mounting
32,0
1.26
22,0
0.87
INPUT
TOP VIEW (COMPONENT SIDE)
OUTPUT
0.24
NOTES:
1- DIMENSIONS ARE mm/[INCH].
2- UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:
.X/[.XX] = +/-0.25/[.01]; .XX/[.XXX] = +/-0.13/[.005]
3- PRODUCT MARKING ON TOP SURFACE
6,1
(4) PL.
7,10
0.280
24,00
0.945
16,00
0.630
0,45
0.018
15,55
0.612
3,01
0.118
8,00
0.315
OUTPUT
15,99
0.630
C
L
BOTTOM VIEW
INPUT
C
L
3,01
0.118
12,94
0.509
14,94
0.588
16,94
0.667
11,10
0.437
20,00
0.787
(2) PL.
3,26
0.128
1,38
TYP
0.054
11,48
(4) X
(2) X
0.452
20,00
0.787
(2) X
16,94
0.667
(6) X
(2) X
1,60
0.063
14,94
0.588
(2) X
12,94
0.509
RECOMMENDED LAND PATTERN
(COMPONENT SIDE SHOWN)
PC VC TM +IN
-IN
15,74
0.620
+OUT1 -OUT1 +OUT2 -OUT2
3,26
0.128
0,51
0.020
(2) X
TYP
8,00
0.315
(2) X
7,48
(8) X
0.295
24,00
(2) X
0.945
16,00
0.630
NOTES:
1- DIMENSIONS ARE mm/[INCH].
2- UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:
.X/[.XX] = +/-0.25/[.01]; .XX/[.XXX] = +/-0.13/[.005]
Page 9
vicorpower.com 800-735-6200 V•I Chip Voltage Transformation Module V048K060T040 Rev. 1.0
Page 9 of 15
PRELIMINARY
Configuration Options
Configuration Inboard
(1)
Onboard
(1)
Inboard with 0.25" Onboard with 0.25"
(Figure 14) (Figure 15) Pin Fins
(2)
Pin Fins
(2)
Effective power density 1400 W/in
3
880 W/in
3
550 W/in
3
440 W/in
3
Junction-Board
2.1 °C/W 2.4 °C/W 2.1 °C/W 2.4 °C/W
thermal resistance
Junction-Case 1.1 °C/W 1.1 °C/W N/A N/A
thermal resistance
Junction-Ambient
6.5 °C/W 6.8 °C/W 5.0 °C/W 5.0 °C/W
thermal resistance 300LFM
Notes:
(1) Surface mounted to a 2" x 2" FR4 board, 4 layers 2 oz Cu
(2) Pin Fin heat sink available as a separate item
Figure 14—Inboard mounting – package K
ONBOARD MOUNT
22.0
0.87
32.0
1.26
6.3
0.25
Figure 15—Onboard mounting – package F
mm
in
mm
in
21.5
0.85
32.0
1.26
4.0
0.16
INBOARD MOUNT
(V•I Chip recessed into PCB)
Page 10
vicorpower.com 800-735-6200 V•I Chip Voltage Transformation Module V048K060T040 Rev. 1.0
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V•I Chip Voltage Transformation Module
PRELIMINARY
Figure 16—VTM test circuit
Application Note
Parallel Operation
In applications requiring higher current or redundancy, VTMs can be
operated in parallel without adding control circuitry or signal lines. To
maximize current sharing accuracy, it is imperative that the source and
load impedance on each VTM in a parallel array be equal. If VTMs are
being fed by an upstream PRM, the VC nodes of all VTMs must be
connected to the PRM VC.
To achieve matched impedances, dedicated power planes within the PC
board should be used for the output and output return paths to the
array of paralleled VTMs. This technique is preferable to using traces of
varying size and length.
The VTM power train and control architecture allow bi-directional
power transfer when the VTM is operating within its specified ranges.
Bi-directional power processing improves transient response in the
event of an output load dump. The VTM may operate in reverse,
returning output power back to the input source. It does so efficiently.
Thermal Management
The high efficiency of the VTM results in low power dissipation
minimizing temperature rise, even at full output current. The heat
generated within the internal semiconductor junctions is coupled
through very low thermal resistances, Rθ
JC and RθJB (see Figure 17),
to the PC board allowing flexible thermal management.
CASE 1 Convection via optional Pin Fins to air (Pin Fins available as a
separate item.)
In an environment with forced convection over the surface of a PCB
with 0.4" of headroom, a VTM with Pin Fins offers a simple thermal
management option. The total Junction to Ambient thermal resistance
of a surface mounted V048K060T040 with pin fins attached is 4.8 ºC/W
in 300 LFM airflow, (see Figure 18).
At 6 Vout and full rated current (40.0A), the VTM dissipates
approximately 13 W per Figure 4. This results in a temperature rise of
approximately 62 ºC, allowing operation in an air temperature of
63 ºC without exceeding the 125 ºC max junction temperature.
CASE 2 Conduction via the PC board to air
The low Junction to BGA thermal resistance allows the use
of the PC board as a means of removing heat from the VTM.
Convection from the PC board to ambient, or conduction to a cold
plate, enable flexible thermal management options.
With a VTM mounted on a 2.0 in
2
area of a multi-layer PC board with
appropriate power planes resulting in 8 oz of effective copper weight,
the Junction-to-BGA thermal resistance, Rθ
JA, is 6.5 ºC/W in 300 LFM
of air. With a maximum junction temperature of 125 ºC and 13 W of
dissipation at full current of 40.0 A, the resulting temperature rise of
85 ºC allows the VTM to operate at full rated current up to a 40 ºC
ambient temperature. See thermal resistances on Page 9 for additional
details on this thermal management option.
Adding low-profile heat sinks to the PC board can lower the thermal
resistance of the PC board surrounding the VTM. Additional cooling
may be added by coupling a cold plate to the PC board with low
thermal resistance stand offs.
CASE 3 Combined direct convection to the air and conduction to the
PC board.
A combination of cooling techniques that utilize the power planes and
dissipation to the air will also reduce the total thermal impedance. This
is the most effective cooling method. To estimate the total effect of the
combination, treat each cooling branch as one leg of a parallel resistor
network.
Notes:
C3 should be placed close
to the load
R3 may be ESR of C3 or a
seperate damping resistor.
C3
10 µF
R3
10 mΩ
C1
100 µF
Al electrolytic
7A
Fuse
CONFIGURATION OPTIONS (continued)
Input reflected ripple
measurement point
F1
C2
0.47 µF
ceramic
+In
TM
VTM
VC
PC
K
-In
Ro
14 V
+
–
+Out
-Out
+Out
-Out
+
Load
–
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vicorpower.com 800-735-6200 V•I Chip Voltage Transformation Module V048K060T040 Rev. 1.0
Page 11 of 15
PRELIMINARY
Q
47 mA
Figure 18—Junction-to-ambient thermal resistance of VTM with 0.25"
Pin Fins. (Pin Fins are available as a separate item.)
Application Note (continued)
Figure 17—Thermal resistance
V•I Chip VTM Level 1 DC Behavioral Model for 48 V to 6 V, 40.0 A
Figure 19—This model characterizes the DC operation of the V•I Chip VTM, including the converter transfer function and its losses. The model enables estimates
or simulations of output voltage as a function of input voltage and output load, as well as total converter power dissipation or heat generation.
©
V•I Chip VTM Level 2 Transient Behavioral Model for 48 V to 6 V, 40.0 A
Figure 20—This model characterizes the AC operation of the V•I Chip VTM including response to output load or input voltage transients or steady state
modulations. The model enables estimates or simulations of input and output voltages under transient conditions, including response to a stepped load
with or without external filtering elements.
©
5.5 mΩ
1/8 • Vin
1/8 • Iout
47 mA
1/8 • Iout 1/8 • Vin
5.5 mΩ
LIN = 20 nH
R
C
IN
1.5 mΩ
3.2 nH
10 mΩ
R
C
OUT
0.15 mΩ
55.0 µF
LOUT = 1.1 nH
4.0 µF
10
Tja
VTM with optional 0.25'' Pin Fins
9
8
7
6
5
4
3
0 100 200 300 400 500 600
Airflow (LFM)
IOUT
+
VIN
V•I
+
I
–
K
+
–
–
ROUT
+
VOUT
–
IN
= 20 nH
L
IOUT
ROUT
+
VIN
CIN
R
C
IN
COUT
+
–
V•I
+
–
IQ
R
C
OUT
+
VOUT
K
–
–
Page 12
vicorpower.com 800-735-6200 V•I Chip Voltage Transformation Module V048K060T040 Rev. 1.0
Page 12 of 15
V•I Chip Voltage Transformation Module
PRELIMINARY
Figure 21 — The PRM controls the factorized bus voltage, V
f
, in proportion to output current to compensate for the output resistance, Ro, of the VTM. The VTM
output voltage is typically within 1% of the desired load voltage (V
L) over all line and load conditions.
FPA Adaptive Loop
Figure 22 — An external error amplifier or Point-of-Load IC (POLIC) senses the load voltage and controls the PRM output – the Factorized Bus – as a function of
output current, compensating for the output resistance of the VTM and for distribution resistance.
FPA Non-isolated Remote Loop
In Figures 21 – 23;
K = VTM Transformation Ratio V
f = PRM Output (Factorized Bus Voltage)
R
O = VTM Output Resistance VO = VTM Output
V
L
= Desired Load Voltage
FPA Isolated Remote Loop
Figure 23—An external error amplifier or Point-of-Load IC (POLIC) senses the load voltage and controls the PRM output – the factorized bus – as a function of
output current, compensating for the output resistance of the VTM and for distribution resistance. The Factorized Bus voltage (V
f) increases in proportion to load
current. The remote feedback loop is isolated within the PRM to support galvanic isolation and hipot compliance at the system level.
Application Note (continued)
+Out
–Out
VH
SC
SG
OS
ROS
NC
CD
RCD
Vf =
Vin
VC
PC
TM
IL
NC
PR
PRM-AL
+In
–In
Factorized
Bus (Vf)
V
L
+
K
(
Io•Ro
K
Vo = VL ± 1.0%
+Out
+In
L
O
A
D
VTM
K
Ro
-Out
+Out
-Out
TM
VC
)
PC
-In
Remote
Loop
Vin
VC
PC
TM
IL
NC
PR
PRM-AL
+In
–In
+Out
–Out
Control
VH
SC
SG
OS
NC
CD
Factorized
Power Bus
V
= f (Vs)
f
TM
VC
PC
+In
-In
VTM
K
Ro
+Out
-Out
+Out
-Out
Vo = VL ± 0.4%
+S
L
O
A
–S
D
Remote
Loop
Vin
VC
PC
TM
IL
NC
PR
PRM-IF
+In
–In
+Out
–Out
Control
VS
FB
FG
NC
NC
NC
Factorized
Power Bus
V
= f (Vs)
f
TM
VC
PC
+In
-In
VTM
K
Ro
+Out
-Out
+Out
-Out
Vo = VL ± 0.4%
+S
L
O
A
–S
D
Page 13
vicorpower.com 800-735-6200 V•I Chip Voltage Transformation Module V048K060T040 Rev. 1.0
Page 13 of 15
PRELIMINARY
Application Note (continued)
V•I Chip soldering recommendations
V•I Chip modules are intended for reflow soldering processes. The
following information defines the processing conditions required for
successful attachment of a V•I Chip to a PCB. Failure to follow the
recommendations provided can result in aesthetic or functional failure
of the module.
Storage
V•I Chip modules are currently rated at MSL 5. Exposure to ambient
conditions for more than 72 hours requires a 24 hour bake at 125ºC to
remove moisture from the package.
Solder paste stencil design
Solder paste is recommended for a number of reasons, including
overcoming minor solder sphere co-planarity issues as well as simpler
integration into overall SMD process.
63/37 SnPb, either no-clean or water-washable, solder paste should be
used. Pb-free development is underway.
The recommended stencil thickness is 6 mils. The apertures should be
20 mils in diameter for the Inboard (BGA) application and 0.9-0.9:1 for
the Onboard (J-Leaded).
Pick and place
Inboard (BGA) modules should be placed as accurately as possible
to minimize any skewing of the solder joint; a maximum offset of
10 mils is allowable. Onboard (J-Leaded) modules should be placed
within ±5 mils.
To maintain placement position, the modules should not be subjected
to acceleration greater than 500 in/sec
2
prior to reflow.
Reflow
There are two temperatures critical to the reflow process; the solder
joint temperature and the module’s case temperature. The solder joint’s
temperature should reach at least 220ºC, with a time above liquidus
(183ºC) of ~30 seconds.
The module’s case temperature must not exceed 208 ºC at anytime
during reflow.
Because of the ∆T needed between the pin and the case, a forced-air
convection oven is preferred for reflow soldering. This reflow method
generally transfers heat from the PCB to the solder joint. The module’s
large mass also reduces its temperature rise. Care should be taken to
prevent smaller devices from excessive temperatures. Reflow of
modules onto a PCB using Air-Vac-type equipment is not recommended
due to the high temperature the module will experience.
Inspection
For the BGA-version, a visual examination of the post-reflow solder
joints should show relatively columnar solder joints with no bridges. An
inspection using x-ray equipment can be done, but the module’s
materials may make imaging difficult.
The J-Lead versions solder joints should conform to IPC 12.2
•Properly wetted fillet must be evident.
• Heel fillet height must exceed lead thickness plus solder thickness.
Removal and rework
V•I Chip modules can be removed from PCBs using special tools such
as those made by Air-Vac. These tools heat a very localized region of
the board with a hot gas while applying a tensile force to the
component (using vacuum). Prior to component heating and removal,
the entire board should be heated to 80-100ºC to decrease the
component heating time as well as local PCB warping. If there are
adjacent moisture-sensitive components, a 125ºC bake should be used
prior to component removal to prevent popcorning. V•I Chip modules
should not be expected to survive a removal operation.
Figure 24—Thermal profile diagram
Figure 25— Properly reflowed V•I Chip J-Lead
239
Joint Temperature, 220ºC
183
165
degC
91
16
Soldering Time
Case Temperature, 208ºC
Page 14
vicorpower.com 800-735-6200 V•I Chip Voltage Transformation Module V048K060T040 Rev. 1.0
Page 14 of 15
V•I Chip Voltage Transformation Module
PRELIMINARY
Input Impedance Recommendations
To take full advantage of the VTM’s capabilities, the impedance of the
source (input source plus the PC board impedance) must be low over a
range from DC to 5 MHz. The input of the VTM (factorized bus) should be
locally bypassed with a 8 µF low Q aluminum electrolytic capacitor.
Additional input capacitance may be added to improve transient
performance or compensate for high source impedance. The VTM has
extremely wide bandwidth so the source response to transients is usually
the limiting factor in overall output response of the VTM.
Anomalies in the response of the source will appear at the output of the
VTM, multiplied by its K factor of 1/8 . The DC resistance of the source
should be kept as low as possible to minimize voltage deviations on the
input to the VTM. If the VTM is going to be operating close to the high
limit of its input range, make sure input voltage deviations will not trigger
the input overvoltage turn-off threshold.
Input Fuse Recommendations
V•I Chips are not internally fused in order to provide flexibility in
configuring power systems. However, input line fusing of V•I Chips must
always be incorporated within the power system. A fast acting fuse is
required to meet safety agency Conditions of Acceptability. The input line
fuse should be placed in series with the +In port.
Warranty
Vicor products are guaranteed for two years from date of shipment against defects in material or workmanship when in normal use and service. This
warranty does not extend to products subjected to misuse, accident, or improper application or maintenance. Vicor shall not be liable for collateral or
consequential damage. This warranty is extended to the original purchaser only.
EXCEPT FOR THE FOREGOING EXPRESS WARRANTY, VICOR MAKES NO WARRANTY, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
Vicor will repair or replace defective products in accordance with its own best judgement. For service under this warranty, the buyer must contact Vicor
to obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be returned to the
buyer. The buyer will pay all charges incurred in returning the product to the factory. Vicor will pay all reshipment charges if the product was defective
within the terms of this warranty.
Information published by Vicor has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. Vicor
reserves the right to make changes to any products without further notice to improve reliability, function, or design. Vicor does not assume any liability
arising out of the application or use of any product or circuit; neither does it convey any license under its patent rights nor the rights of others. Vicor
general policy does not recommend the use of its components in life support applications wherein a failure or malfunction may directly threaten life or
injury. Per Vicor Terms and Conditions of Sale, the user of Vicor components in life support applications assumes all risks of such use and indemnifies
Vicor against all damages.
Application Note (continued)
Page 15
vicorpower.com 800-735-6200 V•I Chip Voltage Transformation Module V048K060T040 Rev. 1.0
2/05
Vicor’s comprehensive line of power solutions includes high density AC-DC
and DC-DC modules and accessory components, fully configurable AC-DC
and DC-DC power supplies, and complete custom power systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for
its use. Vicor components are not designed to be used in applications, such as life support systems, wherein a failure or
malfunction could result in injury or death. All sales are subject to Vicor’s Terms and Conditions of Sale, which are
available upon request.
Specifications are subject to change without notice.
Intellectual Property Notice
Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent
applications) relating to the products described in this data sheet. Interested parties should contact Vicor's
Intellectual Property Department.
Vicor Corporation
25 Frontage Road
Andover, MA, USA 01810
Tel: 800-735-6200
Fax: 978-475-6715
email
Vicor Express: vicorexp@vicr.com
Technical Support: apps@vicr.com
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