Via VT82C686B User Manual

Data Sheet

VT82C686B South Bridge

Revision 2.37 November 10, 2004

VIA TECHNOLOGIES, INC.

No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise without the prior written permission of VIA Technologies Incorporated.

VT82C686A, VT82C686B and Super South may only be used to identify products of VIA Technologies, Inc.

ia a registered trademark of VIA Technologies, Incorporated.

PS/2 Pentium Corporation. Windows 95 Corporation. PCI All trademarks are the properties of their respective owners.

is a registered trademark of International Business Machines Corporation.

, Pentium-ProTM, Pentium-IITM, Pentium-IIITM, CeleronTM, and GTL+TM are registered trademarks of Intel

, Windows 98TM, Windows NTTM, and Plug and PlayTM are registered trademarks of Microsoft

is a registered trademark of the PCI Special Interest Group.

Disclaimer Notice:

No license is granted, implied or otherwise, under any patent or patent rights of VIA Technologies. VIA Technologies makes no warranties, implied or otherwise, in regard to this document and to the products described in this document. The information provided by this document is believed to be accurate and reliable as of the publication date of this document. However, VIA Technologies assumes no responsibility for any errors in this document. Furthermore, VIA Technologies assumes no responsibility for the use or misuse of the information in this document and for any patent infringements that may arise from the use of this document. The information and product specifications within this document are subject to change at any time, without notice and without obligation to notify any person of such change.

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Web: http://www.via.com.tw

VT82C686B "Super South" South Bridge

REVISION HISTORY

Document Release Date Revision Initials

1.72 6/15/00 Fixed SA pin description; fixed 686B part # in figures 1 & 7 Added 1.5V interface note to FERR# and APCD1-0 Removed RTC ports 72-73 and Rx75[6] (and fixed GPO6 description) Fixed Func 1 Rx45[5-4] & default, PM I/O Rx20-25[5], 2A[10] Added Func 2/3/4 Rx6[4]/Rx34, F4Rx68-6F power management capabilities Added Func 4 SMB I/O Rx54, 90-93, D2-D6 and Func 5/6 Rx48[3] Fixed mechanical drawing for proper orientation of marking relative to pin 1

1.8 8/1/00 Removed Super-I/O “high speed baud rate support” Fixed VREF pin direction and voltage, Added F4 Rx55[3] Removed ambient temp spec and added max power dissipation

1.9 12/8/00 Changed GPOWE# pin name to GPOWE; Updated VCCH/GNDH descriptions Function 0 – Added Rx34 Capability Pointer, added note to Rx43 Function 1 – Fixed default values of Rx40, 41, 45, 54; Changed Rx4[7,1], 6[4],

10[2-0], 14[1-0], 18[2-0], 1C[1-0], 20[3-0], 40[3-2], 42[7-6], 44[7], 45[5]

Function 4 – Removed incorrect notes from Rx54[3-2]

1.91 1/2/01 Fixed typo in table of contents, Fixed Function 1 Rx43[3-0], 45[2] DH

1.92 2/2/01 Added EXTSMI#, ACSDIN, ACSDIN2 to suspend power; Fixed PMIO Rx10[10] DH

1.93 3/2/01 Removed ATEST/DTEST; Fixed F4 Rx4C[0] & PMIO Rx10[9], 2C[3] DH

2.0 3/19/01 Removed incorrect SMBus I/O Rx93-90 & D2-D6 and fixed reg summary table Fixed SMB RxD2[1-0] bit descriptions

2.1 4/27/01 Removed temp sensor 3 (HWM Rx42[7],44[7-6],49[7-6],4B[5-4], & I/O Rx1D-1F) DH

2.2 7/2/01 Updated company address; Added changes for chip version “CE” Updated F0Rx46[2],49[7],84[4]; F4Rx4C[1],55[3],57[1]; PMIO Rx20[7-6,4-2]

2.21 10/17/01 Added SuperIO Config RxD0-DB; Function 5 IO Base 3 Rx0-FF Moved SB/Game port reg summary tables after other legacy regs Added APIC reg summary table; Fixed F0 Rx46[2], 58, PMIO Rx20/22/24[2] Moved APIC regs to before PCI config I/O, fixed Rx1, added Rx3

2.22 2/12/02 Updated logos and formatting; Fixed PMIO Rx21-20[7] DH

2.23 2/13/02 Fixed mech diagram & regenerated pdf to fix printing bug; changed page header DH

2.24 3/11/02 Updated Function 0 Rx5A[3] DH

2.25 12/19/02 Updated VIA logos on cover and page headers Updated Port 61 (bits 7-6 and 3-2), Port 92 (bits 7-6 and 3), and Func 1 Rx54[1]

2.26 2/3/03 Updated VIA USA street address; Removed Function 0 Rx5A[3] DH

2.27 4/8/03 Fixed IDE Interrupt Pin default (Function 1 Rx3D) Fixed incorrect JEDEC-specification reference in mechanical spec

2.28 6/9/03 Updated Func 0 Rx76[3], Func 4 Rx41[1], 4C[7-4], 4D[6-4], PMIO Rx10[3-0] DH

2.29 9/5/03 Re-added RTC ports 72-73 and updated PCI Function 0 Rx58[7] and 5B[1] AL

2.30 9/9/03 Fixed typographical errors and updated Function 0 Rx5B[1] AL

2.31 12/3/03

2.32 12/30/03 Updated pin description DRQ2 and DACK2# VL

2.33 3/26/04 Removed Power Characteristics in Electrical Spec section VL

2.34 7/9/04 Added lead-free package to mechanical specification section VL

2.35 8/17/04 Updated lead free package in mechanical specification section VL

2.36 10/06/04 Updated bit definition for Function 0 Rx85[5] and Function 4 Rx40[5]

2.37 11/10/04 Updated Rx69-68[1:0] bit definition VL

Removed FDCIRQ and FDCDRQ signals in pin G5, H3 and G1 Updated Miscellaneous / General Purpose IO Rx75[3] Updated top marking in mechanical specification

Added Function 4 PMIO Rx5A-54

Revision 2.37, November 10, 2004 -i- Revision History

VT82C686B "Super South" South Bridge

TABLE OF CONTENTS

REVISION HISTORY .......................................................................................................................................................................I

TABLE OF CONTENTS.................................................................................................................................................................. II

LIST OF FIGURES .........................................................................................................................................................................IV

LIST OF TABLES ...........................................................................................................................................................................IV

PRODUCT FEATURES ................................................................................................................................................................... 1

OVERVIEW....................................................................................................................................................................................... 4

PINOUTS............................................................................................................................................................................................ 6

PIN DIAGRAM ................................................................................................................................................................................ 6

PIN LISTS ....................................................................................................................................................................................... 7

PIN DESCRIPTIONS......................................................................................................................................................................... 9

REGISTERS..................................................................................................................................................................................... 27

REGISTER OVERVIEW ................................................................................................................................................................. 27

REGISTER DESCRIPTIONS............................................................................................................................................................ 39

Legacy I/O Ports ................................................................................................................................................................... 39

Keyboard Controller Registers .............................................................................................................................................................. 40

DMA Controller I/O Registers .............................................................................................................................................................. 42

Interrupt Controller Registers................................................................................................................................................................ 43

Timer / Counter Registers .....................................................................................................................................................................43

CMOS / RTC Registers......................................................................................................................................................................... 44

Super-I/O Configuration Index / Data Registers............................................................................................................... 45

Keyboard / Mouse Controller Configuration Registers.................................................................................................... 45

Super-I/O Configuration Registers..................................................................................................................................... 46

Super-I/O I/O Ports.............................................................................................................................................................. 48

Floppy Disk Controller Registers .......................................................................................................................................................... 48

Parallel Port Registers ........................................................................................................................................................................... 49

Serial Port 1 Registers ........................................................................................................................................................................... 50

Serial Port 2 Registers ........................................................................................................................................................................... 51

SoundBlaster Pro Port Registers......................................................................................................................................... 52

FM Registers ......................................................................................................................................................................................... 52

Mixer Registers ..................................................................................................................................................................................... 52

Sound Processor Registers .................................................................................................................................................................... 52

Game Port Registers............................................................................................................................................................. 53

APIC Registers...................................................................................................................................................................... 54

Memory Mapped I/O APIC Registers ................................................................................................................................................... 54

Indexed I/O APIC 32-Bit Registers....................................................................................................................................................... 54

PCI Configuration Space I/O .............................................................................................................................................. 56

Function 0 Registers - PCI to ISA Bridge .......................................................................................................................... 57

PCI Configuration Space Header ..........................................................................................................................................................57

ISA Bus Control .................................................................................................................................................................................... 57

Plug and Play Control............................................................................................................................................................................ 61

Distributed DMA / Serial IRQ Control .................................................................................................................................................63

Miscellaneous / General Purpose I/O .................................................................................................................................................... 64

Function 1 Registers - Enhanced IDE Controller.............................................................................................................. 70

PCI Configuration Space Header ..........................................................................................................................................................70

IDE-Controller-Specific Confiiguration Registers ................................................................................................................................ 72

IDE I/O Registers .................................................................................................................................................................................. 75

Function 2 Registers - USB Controller Ports 0-1............................................................................................................... 76

Revision 2.37, November 10, 2004 -ii- Table of Contents

VT82C686B "Super South" South Bridge

PCI Configuration Space Header ..........................................................................................................................................................76

USB-Specific Configuration Registers.................................................................................................................................................. 77

USB I/O Registers................................................................................................................................................................................. 78

Function 3 Registers - USB Controller Ports 2-3............................................................................................................... 79

PCI Configuration Space Header ..........................................................................................................................................................79

USB-Specific Configuration Registers.................................................................................................................................................. 80

USB I/O Registers................................................................................................................................................................................. 81

Function 4 Regs - Power Management, SMBus and HWM ............................................................................................. 82

PCI Configuration Space Header ..........................................................................................................................................................82

Power Management-Specific PCI Configuration Registers................................................................................................................... 83

Hardware-Monitor-Specific Configuration Registers............................................................................................................................ 90

System Management Bus-Specific Configuration Registers................................................................................................................. 90

Power Management I/O-Space Registers .............................................................................................................................................. 91

System Management Bus I/O-Space Registers ...................................................................................................................................100

Hardware Monitor I/O Space Registers............................................................................................................................................... 103

Function 5 & 6 Registers - AC97 Audio & Modem Codecs............................................................................................ 107

PCI Configuration Space Header – Function 5 Audio......................................................................................................................... 107

PCI Configuration Space Header – Function 6 Modem ...................................................................................................................... 108

Function 5 & 6 Codec-Specific Configuration Registers .................................................................................................................... 109

I/O Base 0 Registers –Audio/Modem Scatter/Gather DMA................................................................................................................ 111

I/O Base 1 Registers – Audio FM NMI Status Registers ....................................................................................................................115

I/O Base 2 Registers – MIDI / Game Port........................................................................................................................................... 115

I/O Base 3 Registers – Codec Register Shadow.................................................................................................................................. 115

FUNCTIONAL DESCRIPTIONS................................................................................................................................................ 116

POWER MANAGEMENT.............................................................................................................................................................. 116

Power Management Subsystem Overview.......................................................................................................................................... 116

Processor Bus States............................................................................................................................................................................ 116

System Suspend States and Power Plane Control ...............................................................................................................................117

General Purpose I/O Ports................................................................................................................................................................... 117

Power Management Events ................................................................................................................................................................. 118

System and Processor Resume Events ................................................................................................................................................118

Legacy Power Management Timers.................................................................................................................................................... 119

System Primary and Secondary Events ............................................................................................................................................... 119

Peripheral Events................................................................................................................................................................................. 119

ELECTRICAL SPECIFICATIONS ............................................................................................................................................ 120

ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................... 120

DC CHARACTERISTICS ............................................................................................................................................................. 120

PACKAGE MECHANICAL SPECIFICATIONS...................................................................................................................... 121

Revision 2.37, November 10, 2004 -iii- Table of Contents

VT82C686B "Super South" South Bridge

LIST OF FIGURES

FIGURE 1. PC SYSTEM CONFIGURATION USING THE VT82C686B ................................................................................ 5

FIGURE 2. VT82C686B BALL DIAGRAM (TOP VIEW) .......................................................................................................... 6

FIGURE 3. VT82C686B PIN LIST (NUMERICAL ORDER)..................................................................................................... 7

FIGURE 4. VT82C686B PIN LIST (ALPHABETICAL ORDER) .............................................................................................. 8

FIGURE 5. STRAP OPTION CIRCUIT...................................................................................................................................... 62

FIGURE 6. POWER MANAGEMENT SUBSYSTEM BLOCK DIAGRAM ........................................................................ 116

FIGURE 8. MECHANICAL SPECIFICATIONS – 352 PIN BALL GRID ARRAY PACKAGE........................................ 121

FIGURE 9. LEAD-FREE MECHANICAL SPECIFICATIONS – 352 PIN BALL GRID ARRAY PACKAGE................ 122

LIST OF TABLES

TABLE 1. PIN DESCRIPTIONS .................................................................................................................................................... 9

TABLE 2. SYSTEM I/O MAP....................................................................................................................................................... 27

TABLE 3. REGISTERS ................................................................................................................................................................. 28

TABLE 4. KEYBOARD CONTROLLER COMMAND CODES.............................................................................................. 41

TABLE 5. CMOS REGISTER SUMMARY ................................................................................................................................ 44

Revision 2.37, November 10, 2004 -iv- Table of Contents

VT82C686B "Super South" South Bridge

VT82C686B PSIPC

PCI SUPER-I/O INTEGRATED PERIPHERAL CONTROLLER

PC99 COMPLIANT PCI-TO-ISA BRIDGE

WITH INTEGRATED SUPER-I/O (FDC, LPT, COM1/2, AND IR),

NTEGRATED HARDWARE SOUNDBLASTER/DIRECT SOUND AC97 AUDIO,

LTRADMA-33/66/100 MASTER MODE PCI-EIDE CONTROLLER,

USB C

ACPI, E

EMPERATURE, VOLTAGE, AND FAN-SPEED MONITORING

PRODUCT FEATURES

• Inter-operable with VIA and other Host-to-PCI Bridges

− Combine with VT82C598 for a complete Super-7 (66/75/83/100MHz) PCI / AGP / ISA system (Apollo MVP3)

− Combine with VT8501 for a complete Super-7 system with integrated 2D / 3D graphics (Apollo MVP4)

− Combine with VT82C693 for a complete 66 / 100 / 133 MHz Socket-370 or Slot-1 system (Apollo Pro133)

− Combine with VT8601 for a complete 66 / 100 / 133 MHz Socket-370 or Slot-1 system with integrated 2D / 3D

graphics (Apollo ProMedia)

− Inter-operable with Intel or other Host-to-PCI bridges for a complete PC99 compliant PCI / AGP / ISA system

• PCI to ISA Bridge

− Integrated ISA Bus Controller with integrated DMA, timer, and interrupt controller

− Integrated Keyboard Controller with PS2 mouse support

− Integrated DS12885-style Real Time Clock with extended 256 byte CMOS RAM and Day/Month Alarm for ACPI

− Integrated USB Controller with root hub and four function ports

− Integrated UltraDMA-33/66/100 master mode EIDE controller with enhanced PCI bus commands

− PCI-2.2 compliant with delay transaction and remote power management

− Eight double-word line buffer between PCI and ISA bus

− One level of PCI to ISA post-write buffer

− Supports type F DMA transfers

− Distributed DMA support for ISA legacy DMA across the PCI bus

− Serial interrupt for docking and non-docking applications

− Fast reset and Gate A20 operation

− Edge trigger or level sensitive interrupt

− Flash EPROM, 4Mb EPROM and combined BIOS support

− Supports positive and subtractive decoding

ONTROLLER, KEYBOARD CONTROLLER, RTC,

ISTRIBUTED DMA, SERIAL IRQ, PLUG AND PLAY,

NHANCED POWER MANAGEMENT, SMBUS, AND

Revision 2.37, November 10, 2004 -1- Product Features

VT82C686B "Super South" South Bridge

• UltraDMA-100 / 66 / 33 Master Mode PCI EIDE Controller

− Dual channel master mode PCI supporting four Enhanced IDE devices

− Transfer rate up to 33MB/sec to cover PIO mode 4, multi-word DMA mode 2 drives, and UltraDMA-33 interface

− Increased reliability using UltraDMA-66 transfer protocols

− Increased performance using UltraDMA-100 mode 5

− Thirty-two levels (doublewords) of prefetch and write buffers

− Dual DMA engine for concurrent dual channel operation

− Bus master programming interface for SFF-8038I rev.1.0 and Windows-95 compliant

− Full scatter gather capability

− Support ATAPI compliant devices including DVD devices

− Support PCI native and ATA compatibility modes

− Complete software driver support

• Integrated Super IO Controller

− Supports 2 serial ports, IR port, parallel port, and floppy disk controller functions

− Two UARTs for Complete Serial Ports

− Programmable character lengths (5,6,7,8)

− Even, odd, stick or no parity bit generation and detection

− Programmable baud rate generator

− Independent transmit/receiver FIFOs

− Modem Control

− Plug and play with 96 base IO address and 12 IRQ options

− Infrared-IrDA (HPSIR) and ASK (Amplitude Shift Keyed) IR port multiplexed on COM2

− Multi-mode parallel port

− Standard mode, ECP and EPP support

− Plug and play with 192 base IO address, 12 IRQ and 4 DMA options

− Floppy Disk Controller

− 16 bytes of FIFO

− Data rates up to 1Mbps

− Perpendicular recording driver support

− Two FDDs with drive swap support

− Plug and play with 48 base IO address, 12 IRQ and 4 DMA options

• SoundBlaster Pro Hardware and Direct Sound Ready AC97 Digital Audio Controller

− Dual full-duplex Direct Sound channels between system memory and AC97 link

− PCI master interface with scatter / gather and bursting capability

− 32 byte FIFO of each direct sound channel

− Host based sample rate converter and mixer

− Standard v1.0 or v2.0 AC97 Codec interface for single or cascaded AC97 Codec’s from multiple vendors

− Loopback capability for re-directing mixed audio streams into USB and 1394 speakers

− Hardware SoundBlaster Pro for Windows DOS box and real-mode DOS legacy compatibility

− Plug and play with 4 IRQ, 4 DMA, and 4 I/O space options for SoundBlaster Pro and MIDI hardware

− Hardware assisted FM synthesis for legacy compatibility

− Direct two game ports and one MIDI port interface

− Complete software driver support for Windows-95/98/2000 and Windows-NT

• Voltage, Temperature, Fan Speed Monitor and Controller

− Five positive voltage (one internal), three temperature (one internal) and two fan-speed monitoring

− Programmable control, status, monitor and alarm for flexible desktop management

− External thermister or internal bandgap temperature sensing

− Automatic clock throttling with integrated temperature sensing

− Internal core VCC voltage sensing

− Flexible external voltage sensing arrangement (any positive supply and battery)

Revision 2.37, November 10, 2004 -2- Product Features

VT82C686B "Super South" South Bridge

• Universal Serial Bus Controller

− USB v.1.1 and Intel Universal HCI v.1.1 compatible

− Eighteen level (doublewords) data FIFO with full scatter and gather capability

− Root hub and four function ports

− Integrated physical layer transceivers with optional over-current detection status on USB inputs

− Legacy keyboard and PS/2 mouse support

• System Management Bus Interface

Host interface for processor communications

−

− Slave interface for external SMBus masters

• Sophisticated PC99-Compatible Mobile Power Management

− Supports both ACPI (Advanced Configuration and Power Interface) and legacy (APM) power management

− ACPI v1.0 Compliant

− APM v1.2 Compliant

− CPU clock throttling and clock stop control for complete ACPI C0 to C3 state support

− PCI bus clock run, Power Management Enable (PME) control, and PCI/CPU clock generator stop control

− Supports multiple system suspend types: power-on suspends with flexible CPU/PCI bus reset options,

suspend to DRAM, and suspend to disk (soft-off), all with hardware automatic wake-up

− Multiple suspend power plane controls and suspend status indicators

− One idle timer, one peripheral timer and one general purpose timer, plus 24/32-bit ACPI compliant timer

− Normal, doze, sleep, suspend and conserve modes

− Global and local device power control

− System event monitoring with two event classes

− Primary and secondary interrupt differentiation for individual channels

− Dedicated input pins for power and sleep buttons, external modem ring indicator, and notebook lid open/close for

system wake-up

− Up to 12 general purpose input ports and 23 output ports

− Multiple internal and external SMI sources for flexible power management models

− One programmable chip select and one microcontroller chip select

− Enhanced integrated real time clock (RTC) with date alarm, month alarm, and century field

− Thermal alarm on either external or any combination of three internal temperature sensing circuits

− Hot docking support

− I/O pad leakage control

• Plug and Play Controller

− PCI interrupts steerable to any interrupt channel

− Steerable interrupts for integrated peripheral controllers: USB, floppy, serial, parallel, audio, soundblaster, MIDI

− Steerable DMA channels for integrated floppy, parallel, and soundblaster pro controllers

− One additional steerable interrupt channel for on-board plug and play devices

− Microsoft Windows 98

, Windows NTTM, Windows 95

and plug and play BIOS compliant

• Integrated I/O APIC (Advanced Peripheral Interrupt Controller)

• Built-in NAND-tree pin scan test capability

• 0.35um, 3.3V, low power CMOS process

• Single chip 27x27 mm, 352 pin BGA

Revision 2.37, November 10, 2004 -3- Product Features

VT82C686B "Super South" South Bridge

OVERVIEW

The VT82C686B PSIPC (PCI Super-I/O Integrated Peripheral Controller) is a high integration, high performance, power-efficient, and high compatibility device that supports Intel and non-Intel based processor to PCI bus bridge functionality to make a complete Microsoft PC99-compliant PCI/ISA system. In addition to complete ISA extension bus functionality, the VT82C686B includes standard intelligent peripheral controllers:

a) Master mode enhanced IDE controller with dual channel DMA engine and interlaced dual channel commands. Dedicated

FIFO coupled with scatter and gather master mode operation allows high performance transfers between PCI and IDE devices. In addition to standard PIO and DMA mode operation, the VT82C686B also supports the UltraDMA-33 standard to allow reliable data transfer rates up to 33MB/sec throughput. The VT82C686B also supports the UltraDMA-66 and UltraDMA-100 (ATA-100) standards. The IDE controller is SFF-8038I v1.0 and Microsoft Windows-family compliant.

b) Universal Serial Bus controller that is USB v1.1 and Universal HCI v1.1 compliant. The VT82C686B includes the root hub

with four function ports with integrated physical layer transceivers. The USB controller allows hot plug and play and isochronous peripherals to be inserted into the system with universal driver support. The controller also implements legacy keyboard and mouse support so that legacy software can run transparently in a non-USB-aware operating system environment.

c) Keyboard controller with PS2 mouse support.

d) Real Time Clock with 256 byte extended CMOS. In addition to the standard ISA RTC functionality, the integrated RTC

also includes the date alarm, century field, and other enhancements for compatibility with the ACPI standard.

e) Notebook-class power management functionality compliant with ACPI and legacy APM requirements. Multiple sleep states

(power-on suspend, suspend-to-DRAM, and suspend-to-Disk) are supported with hardware automatic wake-up. Additional functionality includes event monitoring, CPU clock throttling and stop (Intel processor protocol), PCI bus clock stop control, modular power, clock and leakage control, hardware-based and software-based event handling, general purpose I/O, chip select and external SMI.

f) Hardware monitoring subsystem for managing system / motherboard voltage levels, temperatures, and fan speeds

g) Full System Management Bus (SMBus) interface.

h) Two 16550-compatible serial I/O ports with infrared communications port option on the second port.

i) Integrated PCI-mastering dual full-duplex direct-sound AC97-link-compatible sound system. Hardware soundblaster-pro

and hardware-assisted FM blocks are included for Windows DOS box and real-mode DOS compatibility. Loopback capability is also implemented for directing mixed audio streams into USB and 1394 speakers for high quality digital audio.

j) Two game ports and one MIDI port

k) ECP/EPP-capable parallel port

l) Standard floppy disk drive interface

m) Distributed DMA capability for support of ISA legacy DMA over the PCI bus. Serial IRQ is also supported for docking and

non-docking applications.

n) Plug and Play controller that allows complete steerability of all PCI interrupts and internal interrupts / DMA channels to any

interrupt channel. One additional steerable interrupt channel is provided to allow plug and play and reconfigurability of onboard peripherals for Windows family compliance.

o) Internal I/O APIC (Advanced Programmable Interrupt Controller)

Revision 2.37, November 10, 2004 -4- Overview

VT82C686B "Super South" South Bridge

(

)

The VT82C686B also enhances the functionality of the standard ISA peripherals. The integrated interrupt controller supports both edge and level triggered interrupts channel by channel. The integrated DMA controller supports type F DMA in addition to standard ISA DMA modes. Compliant with the PCI-2.2 specification, the VT82C686B supports delayed transactions and remote power management so that slower ISA peripherals do not block the traffic of the PCI bus. Special circuitry is built in to allow concurrent operation without causing dead lock even in a PCI-to-PCI bridge environment. The chip also includes eight levels (doublewords) of line buffers from the PCI bus to the ISA bus to further enhance overall system performance.

CPU / Cache

Sideband Signals:

Init / CPUreset

IRQ / NMI

SMI / StopClk

FERR / IGNNE

Slot-1

SLP#

Boot ROM

Expansion

Cards

RTC Crystal

ISA

CA CD

North Bridge

VT82C686B

352 BGA

MA/Command

PCI

SMB

USB Ports 0-3 Keyboard / Mouse MIDI / Game Ports Parallel Port Serial Ports 1 and 2 Infrared Comm Port IDE Primary and Secondary Floppy Disk Interface AC97 Link Hardware Monitor Inputs GPIO, Power Control, Reset

System Memory

DIMM Module ID

Expansion

Cards

Figure 1. PC System Configuration Using the VT82C686B

Revision 2.37, November 10, 2004 -5- Overview

VT82C686B "Super South" South Bridge

PINOUTS

Pin Diagram

Figure 2. VT82C686B Ball Diagram (Top View)

Key 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

CTS

DCD

SMEM

IOCH

SMEM

ROM

CS#

DACK

MCS

16# S BHE#

IRQ6

SLPB

TC BALE

RST

DRV

IRQ

DRQ 5 SD 9 DACK

SA14

SDD14

SA9

SDD9

SA5

SDD5

SA2

SDD2

SA0

SDD0

SD 0 SD 1 SD 3 SD 6 RTC

USB

RDY

P0+

USB

AEN

P0-

USB

CLK

DACK

DRQ 3 USB

DRQ

RFSH# OSC

IOCS

16#

IRQ 5 IRQ 4 IRQ 3 DACK

DRQ2

SIRQ

IRQ

DACK

DRQ 0 DACK

DACK

SDD13

SA13

SA12

SDD12

SA8

SA7

SDD8

SDD7

SA4

SA3

SDD4

SDD3

SA1

SD 5 MEM

SDD1

SD 2 SD 4 SD 7 RTC

USB

P2+

USB

P2-

P3+

USB

P1+

P1-

KB CK

IRQ

CHK#

DRQ 7 SD

SA11

SDD11

SA6

SDD6

MEM

IRQ 9 B

CLK

IRQ

DRQ

SA15

SDD15

SA10

SDD10

XDIR INIT SLP#

SOE# SMI# NMI

SPKR

WRT

DATA#

PRT#

DATA# W GATE#

DSK

CHG#

SEL#

DRV

DEN1

DEX#

USB

P3-

GND VCC

GND

VCC H H VCC

VCC J GND GND GND GND J VCC

VCC K GND GND GND GND K VCC

GND L GND GND GND GND L GND

VCC M GND GND GND GND M VCC

VCC N N VCC

GND P7 8 9 10 11 12 13 P14 GND

GND VCC

RSM

FERR#

RST#

PWR

CLK#

VBAT

DTR

MTR

DIR#

TRK

STEP#

00#

GNDU VCC

G7 8 9 10 11 12 13 G14 GND

VCC

GPO 0 SMB

GPIOD SMB

CPU

RST#

STP

INTR

A20

IGN NE#

RI 2#

DRV

DEN0

MTR

VCCS VCC

DATA

CLK

SUS

ALRT#

SUS

TXD 1 DCD

RXD 2 RTS

DSR

TXD 2 DTR

VCC GND VCC VCC VCC GND

CLK

ST1#

SMB

EXT

SMI#

RTS

SUS

LID

SUS

CTS

RI 1#

VCC

THRM

PME#

BAT

LOW#

RING#

IRQ8#

RUN#T SENS1V SENS3

PWR

BTN#

PD 7 PD

RXD

ACK#

DSR

BUSY

SLCT

VCCH GND

FAN

VREF

FAN 2 V

SENS1

PCI

STP#V SENS2

PCK

CPU STP#T SENS2V SENS4

PD 3 PD 0 PCI

PD 4 P

PD 5 PD 1 STR

PD 6 SLCT

VCC GND

GPIOA SDD10

JBX

GPI23

GPIOC JAX

PIRQ

ERR#

AUTO

INIT#

OBE#

IN# P CLK

JAB2

ACRS JBB2

SYNC SDI

GPO23

JBY

GPI22

JAY

GPO22

PIRQ

RST#

PIRQ

FD#

PIRQ

C/BE

DEV

SEL#

AD 6 AD 5 AD 4 AD 3 AD

AD 1 AD

CS3#

RDY

PDD 0 PDD

PDD

PDD 5 PDD 9 PDD 6 PDD 8 PDD

JAB1 JBB1 BTCK

SDO SDI2 MSO MSI

FRM#

STOP# SERR# PAR CBE1#

AD 9 AD 8 C/BE

PREQ# PGNT

IOR#

IOW#

PDD 1 PDD

PDD 3 PDD

CS1#

CS3#

SD A1

C/BE

RDY#T RDY#

DRQ

DACK#

IOR#

SEL

CS1#

DACK#

PDD

PDD 4 PDD

RDY

IOW#

DRQ

Note: Some of the pins above have alternate functions and alternate names. The table above contains only one name (usually the most often used function), but the pin lists and pin descriptions contain all names.

Revision 2.37, November 10, 2004 -6- Pinouts

VT82C686B "Super South" South Bridge

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Pin Lists

Figure 3. VT82C686B Pin List (Numerical Order)

Pin Pin Name Pin Pin Name Pin Pin Name Pin Pin Name Pin Pin Name

A01 O SMEMR# D12 IO IRRX / GPO15 H19 IO AD12 A02 I IOCHRDY D13 I PE / WDATA# H20 IO AD11 A03 IO USBP0+ D14 IO PD5 J01 O RSTDRV N16 I PDRDY U15 O ACRST A04 IO USBP2+ D15 IO PD1 / TRK00# J02 IO LA23 N17 O PDIOR# U16 I JBB2 A05 IO KBDT / KBRC D16 IO STROBE# J03 IO LA22 N18 O PDIOW# U17 O SDCS1# A06 I WRTPRT# D17 I PIRQB# J04 IO LA21 N19 I PDDRQ U18 O SDCS3# A07 O WDATA# D18 IO AD23 J05 IO LA20 N20 IO PDD15 U19 O SDA0 A08 O DS1# D19 IO AD22 A09 I CTS2# D20 IO AD21 A10 I DCD2# E01 O DACK1# / IDEIRQB A11 O TXD1 E02 I DRQ1 A12 I DCD1# E03 IO RFSH# A13 IO PD7 E04 I OSC A14 IO PD2 / WRTPRT# E05 IO KBCK/A20GATE J16 IO AD10 A15 I ERROR#/HDSL# E06 IO USBP3- J17 IO AD09 P16 IO PDD00 V07 I FERR# A16 I PIRQA# E07 I TRK00# J18 IO AD08 P17 IO PDD14 V08 OD CPURST A17 IO AD31 E08 O STEP# J19 IO CBE0# P18 IO PDD01 V09 O SUSA#/O1/APD0 A18 IO AD28 E09 O MTR0# J20 IO AD07 P19 IO PDD13 V10 O SUSST1# / GPO3 A19 IO AD26 E10 O RTS2# K01 IO SA19 P20 IO PDD02 V11 I RING# / GPI7 A20 IO AD25 E11 I RI1# K02 IO SA18 R01 IO SA14 / SDD14 V12 O PCISTP#/GPO5 B01 O SMEMW# E12 O IRTX / GPO14 K03 I IRQ10 R02 IO SA13 / SDD13 V13 I VSENS2 (2.5V B02 O AEN E13 I SLCT / WGATE# K04 I IRQ11 R03 IO SA12 / SDD12 V14 IO GPIOC(10)/CHAS B03 IO USBP0- E14 IO PD6 K05 I IRQ15 R04 IO SA11 / SDD11 V15 I JAX / GPO23 B04 IO USBP2- E15 IO SLCTIN# / STEP# B05 IO USBP3+ E16 I PCLK B06 I RDATA# E17 IO AD20 B07 O WGATE# E18 IO AD19 B08 O DS0# E19 IO AD18 B09 O DTR2# E20 IO AD17 B10 I RXD2 F01 I MCS16# K16 IO AD06 B11 O RTS1# F02 IO SBHE# K17 IO AD05 B12 I RXD1 F03 I IOCS16# K18 IO AD04 B13 I ACK# / DS1# F04 I IOCHCK# / GPI0 K19 IO AD03 B14 IO PD3 / RDATA# F05 I IRQ7 K20 IO AD02 B15 IO PD0 / INDEX# B16 O PCIRST# B17 I PIRQD# B18 IO AD29 B19 IO AD27 B20 IO AD24 C01 I ROMCS#/KBCS# C02 IO IOW# C03 I USBCLK C04 IO USBP1+ C05 IO MSDT / IRQ12 F16 IO AD16 C06 I DSKCHG# F17 IO CBE2# L16 IO AD01 T07 OD SLP# / GPO7 W18 I ACBTC C07 O HDSEL# F18 IO FRAME# L17 IO AD00 T08 O GPO0 / SLOWCLK W19 O SDIOR# C08 O MTR1# F19 IO IRDY# L18 O PREQ# T09 IO SMBDATA W20 O SDIOW# C09 I RI2# F20 IO TRDY# L19 I PGNT# T10 O SUSCLK / APICD1 Y01 IO SD00 C10 I DSR2# G01 I IRQ6/I4/SLPBTN# L20 O PDCS1# T11 I THRM / PME# / GI5 Y02 IO SD01 C11 I CTS1# G02 I IRQ5 M01 I DRQ5 T12 I FAN1 Y03 IO SD03 C12 I DSR1# G03 I IRQ4 M02 IO SD09 C13 I BUSY / MTR1# G04 I IRQ3 M03 O DACK6#/UA T14 IO GPIOA/8/GPOWE Y05 I RTCX1 C14 IO PD4 / DSKCHG# G05 O DACK2#/I13/O25/OC0# M04 IO SD10 T15 I JAB2 C15 IO PINIT# / DIR# C16 IO AUTOFD#/DRV0 C17 I PIRQC# G16 IO DEVSEL# C18 IO AD30 G17 IO STOP# C19 IO CBE3# G18 I SERR# C20 I IDSEL G19 IO PAR D01 IO IOR# G20 IO CBE1# D02 O DACK3#/ACIRQ H01 O TC M16 O PDCS3# U03 IO SA03 / SDD3 Y14 I VSENS4 (12V D03 I DRQ3 H02 O BALE M17 O PDA0 U04 IO MEMR# Y15 I JAY / GPO22 D04 IO USBP1- H03 I DRQ2/I12/O24/SQ/OC1# M18 O PDA2 U05 O SOE#/O13/MCCS# Y16 O ACSDO D05 IO MSCK / IRQ1 H04 I IRQ9 M19 O PDA1 U06 OD SMI# Y17 I ACSDI2 D06 O DRVDEN1 H05 O BCLK M20 O PDDACK# U07 OD NMI Y18 O MSO D07 I INDEX# D08 O DIR# D09 O DRVDEN0 H16 IO AD15 N03 IO SD12 U10 I LID / GPI3 / WSC# D10 O TXD2 H17 IO AD14 N04 I DRQ7 U11 I BATLOW#/GPI2 D11 O DTR1# H18 IO AD13 N05 IO SD13 U12 IO FAN2/GPIOB(9)

F06 P GND F07 P VCC F08 P GNDU F09 P VCCU F10 P VCC F11 P GND L06 P GND F12 P VCC L09 P GND F13 P VCC L10 P GND F14 P VCC L11 P GND F15 P GND L12 P GND

G06 P GND G15 P GND M06 P VCC

H06 P VCC H15 P VCC

J06 P VCC J09 P GND J10 P GND J11 P GND J12 P GND J15 P VCC P06 P GND

K06 P VCC K09 P GND R06 P GND K10 P GND R07 P VCC K11 P GND R08 P VCC K12 P GND R09 P VCCS K15 P VCC R10 P VCCS

L01 I IRQ14 R16 IO PDD12 W07 OD STPCLK# L02 O DACK0#/IA R17 IO PDD03 W08 OD INTR L03 I DRQ0 R18 IO PDD11 W09 O SUSB# / GPO2 L04 O DACK5#/MI R19 IO PDD04 W10 I SMBALRT#/GPI6 L05 IO SD08 R20 IO PDD10 W11 I IRQ8#/GPI1

L15 P GND

M05 I DRQ6 T16 IO PDD05 Y07 OD A20M#

M09 P GND M10 P GND M11 P GND M12 P GND M15 P VCC

N01 IO SD11 U08 IO GPIOD/SO#/MCCS# Y19 I MSI N02 O DACK7#/UB U09 IO SMBCL

N06 P VCC N15 P VCC

P01 IO SD14 U20 O SDA2 P02 IO SD15 V01 IO SA02 / SDD2 P03 IO SA17 V02 IO SA01 / SDD1 P04 IO SA16 V03 IO SD05 / KBIN4 P05 IO SA15 / SDD15 V04 IO MEMW#

P15 P GND

R05 IO SA10 / SDD10 V16 O ACSYNC

R11 P VCC R12 P VCCH R13 P GNDH R14 P VCC R15 P GND

T01 IO SA09 / SDD9 W12 IO PCKRUN# T02 IO SA08 / SDD8 W13 I TSENS1 T03 IO SA07 / SDD7 W14 I VSENS3 (5V) T04 IO SA06 / SDD6 W15 I JBY / GPI22 T05 O XDIR/O12/PCS0# W16 I JAB1 T06 OD INIT W17 I JBB1

T13 O VREF

T17 IO PDD09 Y08 OD IGNNE# T18 IO PDD06 Y09 O SUSC# T19 IO PDD08 Y10 IOD EXTSMI# T20 IO PDD07 Y11 I PWRBTN# U01 IO SA05 / SDD5 Y12 O CPUSTP#/GPO4 U02 IO SA04 / SDD4 Y13 I TSENS2

U13 I VSENS1 (2.0V) U14 I JBX / GPI23

V05 IO SPKR V06 I RSMRST#

V17 I ACSDI V18 O SDA1 V19 O SDDACK# V20 I SDRDY W01 IO SA00 / SDD0 W02 IO SD02 W03 IO SD04 / KBIN3 W04 IO SD07 / KBIN6 W05 O RTCX2 W06 I PWRGD

Y04 IO SD06 / KBIN5

Y06 P VBAT

Y20 I SDDRQ

Revision 2.37, November 10, 2004 -7- Pinouts

VT82C686B "Super South" South Bridge

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Figure 4. VT82C686B Pin List (Alphabetical Order)

Pin Pin Name Pin Pin Name Pin Pin Name Pin Pin Name Pin Pin Name

Y07 OD A20M# N04 I DRQ7 K05 I IRQ15 A16 I PIRQA# T07 OD SLP# / GPO7 B13 I ACK# / DS1# D09 O DRVDEN0 D12 IO IRRX / GPO15 D17 I PIRQB# W10 I SMBALRT# / GPI6 W18 I ACBTCK D06 O DRVDEN1 E12 O IRTX / GPO14 C17 I PIRQC# U09 IO SMBCL U15 O ACRST B08 O DS0# W16 I JAB1 B17 I PIRQD# T09 IO SMBDATA V17 I ACSDI A08 O DS1# T15 I JAB2 L18 O PREQ# A01 O SMEMR# Y17 I ACSDI2 C06 I DSKCHG# V15 I JAX / GPO23 Y11 I PWRBTN# B01 O SMEMW# Y16 O ACSDO C12 I DSR1# Y15 I JAY / GPO22 W06 I PWRGD U06 OD SMI# V16 O ACSYNC C10 I DSR2# W17 I JBB1 B06 I RDATA# U05 O SOE#/GPO13/MCCS# L17 IO AD00 D11 O DTR1# U16 I JBB2 E03 IO RFSH# V05 IO SPKR L16 IO AD01 B09 O DTR2# U14 I JBX / GPI23 E11 I RI1# E08 O STEP# K20 IO AD02 A15 I ERROR#/HDSEL# W15 I JBY / GPI22 C09 I RI2# G17 IO STOP# K19 IO AD03 Y10 IOD EXTSMI# E05 IO KBCK / A20G V11 I RING# / GPI7 W07 OD STPCLK# K18 IO AD04 T12 I FAN1 A05 IO KBDT / KBRC C01 O ROMCS#/KBCS# D16 IO STROBE# K17 IO AD05 U12 IO FAN2/GPIOB(9) J05 IO LA20 V06 I RSMRST# V09 O SUSA# / O1 / APICD0 K16 IO AD06 V07 I FERR# J04 IO LA21 J01 O RSTDRV W09 O SUSB# / GPO2

J20 IO AD07 F18 IO FRAME# J03 IO LA22 Y05 I RTCX1 Y09 O SUSC# J18 IO AD08 J17 IO AD09

J16 IO AD10 H20 IO AD11 H19 IO AD12 H18 IO AD13 H17 IO AD14 H16 IO AD15

F16 IO AD16 E20 IO AD17 E19 IO AD18 E18 IO AD19 E17 IO AD20 D20 IO AD21 D19 IO AD22 D18 IO AD23 B20 IO AD24 A20 IO AD25 A19 IO AD26 B19 IO AD27 A18 IO AD28 B18 IO AD29 C18 IO AD30 A17 IO AD31 B02 O AEN C16 IO AUTOFD#/DR0 H02 O BALE U11 I BATLOW#/GPI2 H05 O BCLK C13 I BUSY / MTR1# T14 IO GPIOA(8)/GPOWE L20 O PDCS1# Y03 IO SD03

J19 IO CBE0# V14 IO GPIOC(10)/CHAS M16 O PDCS3# W03 IO SD04 / KBIN3 G20 IO CBE1# U08 IO GPIOD(11)/MCCS# P16 IO PDD00 V03 IO SD05 / KBIN4

F17 IO CBE2# T08 O GPO0 / SLOWCLK P18 IO PDD01 Y04 IO SD06 / KBIN5 C19 IO CBE3# C07 O HDSEL# P20 IO PDD02 W04 IO SD07 / KBIN6 V08 OD CPURST C20 I IDSEL R17 IO PDD03 L05 IO SD08 Y12 O CPUSTP#/GPO4 Y08 OD IGNNE# R19 IO PDD04 M02 IO SD09 C11 I CTS1# D07 I INDEX# T16 IO PDD05 M04 IO SD10 A09 I CTS2# T06 OD INIT T18 IO PDD06 N01 IO SD11 L02 O DACK0#/IDEA W08 OD INTR T20 IO PDD07 N03 IO SD12 E01 O DACK1#/IDEB F04 I IOCHCK# / GPI0 T19 IO PDD08 N05 IO SD13 G05 O DAK2#/I13/O25 A02 I IOCHRDY T17 IO PDD09 P01 IO SD14 D02 O DACK3#/AIRQ F03 I IOCS16# R20 IO PDD10 P02 IO SD15 L04 O DACK5#/MIRQ D01 IO IOR# R18 IO PDD11 U19 O SDA0 M03 O DACK6#/USBIA C02 IO IOW# R16 IO PDD12 V18 O SDA1 N02 O DACK7#/USBIB F19 IO IRDY# P19 IO PDD13 U20 O SDA2 U13 I VSENS1 (2.0V A12 I DCD1# G04 I IRQ3 P17 IO PDD14 U17 O SDCS1# V13 I VSENS2 A10 I DCD2# G03 I IRQ4 N20 IO PDD15 U18 O SDCS3# W14 I VSENS3 (5V) G16 IO DEVSEL# G02 I IRQ5 M20 O PDDACK# V19 O SDDACK# Y14 I VSENS4 D08 O DIR# G01 I IRQ6/I4/SLPBTN# N19 I PDDR L03 I DRQ0 F05 I IRQ7 N17 O PDIOR# W19 O SDIOR# B07 O WGATE# E02 I DRQ1 W11 I IRQ8# / GPI1 N18 O PDIOW# W20 O SDIOW# A06 I WRTPRT# H03 I D2/I12/O24/SQ H04 I IRQ9 N16 I PDRDY V20 I SDRDY T05 O XDIR/GPO12/PCS0# D03 I DRQ3 M01 I DRQ5 K04 I IRQ11 L19 I PGNT# E13 I SLCT / WGATE# M05 I DRQ6 L01 I IRQ14 C15 IO PINIT# / DIR# E15 IO SLCTIN#/STEP#

F06 P GND F11 P GND F15 P GND G06 P GND G15 P GND J09 P GND J10 P GND J11 P GND J12 P GND K09 P GND K10 P GND K11 P GND K12 P GND L06 P GND L09 P GND L10 P GND L11 P GND L12 P GND

L15 P GND M09 P GND M10 P GND M11 P GND M12 P GND

P06 P GND

P15 P GND

R06 P GND

R15 P GND

R13 P GNDH

F08 P GNDU

03 I IRQ10 D13 I PE / WDATA# G18 I SERR#

J02 IO LA23 W05 O RTCX2 T10 O SUSCLK / APICD1 U10 I LID/GPI3/WSC# B11 O RTS1# V10 O SUSST1# / GPO3 F01 I MCS16# E10 O RTS2# H01 O TC U04 IO MEMR# B12 I RXD1 T11 I THRM / PME# / GI5 V04 IO MEMW# B10 I RXD2 F20 IO TRDY# D05 IO MSCK / IRQ1 W01 IO SA00 / SDD0 E07 I TRK00# C05 IO MSDT / IRQ12 V02 IO SA01 / SDD1 W13 I TSENS1 Y19 I MSI V01 IO SA02 / SDD2 Y13 I TSENS2 Y18 I MSO U03 IO SA03 / SDD3 A11 O TXD1 E09 O MTR0# U02 IO SA04 / SDD4 D10 O TXD2 C08 O MTR1# U01 IO SA05 / SDD5 C03 I USBCL U07 OD NMI T04 IO SA06 / SDD6 B03 IO USBP0E04 I OSC T03 IO SA07 / SDD7 A03 IO USBP0+ G19 IO PAR T02 IO SA08 / SDD8 D04 IO USBP1-

W12 IO PCKRUN# T01 IO SA09 / SDD9 C04 IO USBP1+

E16 I PCL B16 O PCIRST# R04 IO SA11 / SDD11 A04 IO USBP2+ V12 O PCISTP#/GPO5 R03 IO SA12 / SDD12 E06 IO USBP3B15 IO PD0 / INDEX# R02 IO SA13 / SDD13 B05 IO USBP3+ D15 IO PD1 / TRK00# R01 IO SA14 / SDD14 A14 IO PD2 / WRTPRT# P05 IO SA15 / SDD15 B14 IO PD3 / RDATA# P04 IO SA16 C14 IO PD4 / DSKCHG# P03 IO SA17 D14 IO PD5 K02 IO SA18 E14 IO PD6 K01 IO SA19 A13 IO PD7 F02 IO SBHE#

M17 O PDA0 Y01 IO SD00 M19 O PDA1 Y02 IO SD01 M18 O PDA2 W02 IO SD02

R05 IO SA10 / SDD10 B04 IO USBP2-

Y06 P VBAT F07 P VCC F10 P VCC F12 P VCC F13 P VCC F14 P VCC H06 P VCC H15 P VCC

J06 P VCC

J15 P VCC K06 P VCC K15 P VCC

M06 P VCC M15 P VCC

N06 P VCC N15 P VCC R07 P VCC R08 P VCC R11 P VCC R14 P VCC R12 P VCCH R09 P VCCS R10 P VCCS F09 P VCCU T13 O VREF

Y20 I SDDR

A07 O WDATA#

2.2V

12V

Revision 2.37, November 10, 2004 -8- Pinouts

VT82C686B "Super South" South Bridge

Pin Descriptions

Table 1. Pin Descriptions

PCI Bus Interface

Signal Name Pin # I/O Signal Description

AD[31:0]

C/BE[3:0]#

FRAME#

IRDY# TRDY# STOP# DEVSEL#

PAR SERR#

IDSEL

PIRQA-D#

PREQ# PGNT#

PCLK PCKRUN#

PCIRST#

(see pin list) IO

C19, F17,

G20, J19

F18 IO

F19 IO F20 IO G17 IO G16 IO

G19 IO G18 I

C20 I

A16, D17,

C17, B17

L18 O L19 I

E16 I

W12 IO

B16 O

Address/Data Bus. The standard PCI address and data lines. The address is driven with FRAME# assertion and data is driven or received in following cycles.

Command/Byte Enable. The command is driven with FRAME# assertion. Byte enables corresponding to supplied or requested data are driven on following clocks.

Frame. Assertion indicates the address phase of a PCI transfer. Negation indicates that one more data transfer is desired by the cycle initiator.

Initiator Ready. Asserted when the initiator is ready for data transfer. Target Ready. Asserted when the target is ready for data transfer. Stop. Asserted by the target to request the master to stop the current transaction. Device Select. The VT82C686B asserts this signal to claim PCI transactions through

positive or subtractive decoding. As an input, DEVSEL# indicates the response to a VT82C686B-initiated transaction and is also sampled when decoding whether to subtractively decode the cycle.

Parity. A single parity bit is provided over AD[31:0] and C/BE[3:0]#. System Error. SERR# can be pulsed active by any PCI device that detects a system

error condition. Upon sampling SERR# active, the VT82C686B can be programmed to generate an NMI to the CPU.

Initialization Device Select. IDSEL is used as a chip select during configuration read and write cycles. Connect this pin to AD18 using a 100 Ω resistor.

PCI Interrupt Request. These pins are typically connected to the PCI bus INTA#INTD# pins as follows: PIRQA# PCI Slot 1 INTA# INTB# INTC# INTD# PCI Slot 2 INTB# INTC# INTD# INTA# PCI Slot 3 INTC# INTD# INTA# INTB# PCI Slot 4 INTD# INTA# INTB# INTC#

PCI Request. This signal goes to the North Bridge to request the PCI bus. PCI Grant. This signal is driven by the North Bridge to grant PCI access to the

VT82C686B.

PCI Clock. PCLK provides timing for all transactions on the PCI Bus. PCI Bus Clock Run. This signal indicates whether the PCI clock is or will be stopped

(high) or running (low). The VT82C686B drives this signal low when the PCI clock is running (default on reset) and releases it when it stops the PCI clock. External devices may assert this signal low to request that the PCI clock be restarted or prevent it from stopping. Connect this pin to ground using a 100 Ω resistor if the function is not used. Refer to the “PCI Mobile Design Guide” and the VIA “Apollo MVP4 Design Guide” for more details.

PCI Reset. Active low reset signal for the PCI bus. The VT82C686B will assert this pin during power-up or from the control register.

PIRQB# PIRQC# PIRQD#

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VT82C686B "Super South" South Bridge

CPU Interface

Signal Name Pin # I/O Signal Description

CPURST

INTR

NMI

INIT

STPCLK#

SMI#

FERR#

IGNNE#

SLP# / GPO7

A20M#

Note: Connect each of the above signals to 4.7K Ω pullup resistors to VCC3.

V8 OD

W8 OD

U7 OD

T6 OD

W7 OD

U6 OD

V7 I

Y8 OD

T7 OD

Y7 OD

CPU Reset. The VT82C686B asserts CPURST to reset the CPU during power-up.

CPU Interrupt. INTR is driven by the VT82C686B to signal the CPU that an interrupt request is pending and needs service.

Non-Maskable Interrupt. NMI is used to force a non-maskable interrupt to the CPU. The VT82C686B generates an NMI when either SERR# or IOCHK# is asserted.

Initialization. The VT82C686B asserts INIT if it detects a shut-down special cycle on the PCI bus or if a soft reset is initiated by the register

Stop Clock. STPCLK# is asserted by the VT82C686B to the CPU to throttle the processor clock. System Management Interrupt. SMI# is asserted by the VT82C686B to the CPU in response to different Power-Management events. Numerical Coprocessor Error. This signal is tied to the coprocessor error signal on the CPU. Internally generates interrupt 13 if active. 1.5V interface. Ignore Numeric Error. This pin is connected to the “ignore error” pin on the CPU.

Sleep (Rx75[7] = 0). Used to put the CPU to sleep. Used with slot-1 CPUs only. Not currently used with socket-7 CPUs.

A20 Mask. Connect to A20 mask input of the CPU to control address bit-20 generation. Logical combination of the A20GATE input (from internal or external keyboard controller) and Port 92 bit-1 (Fast_A20).

Advanced Programmable Interrupt Controller (APIC)

Signal Name Pin # I/O Signal Description

WSC# / GPI3 / LID

APICD0 / GPO1 / SUSA# APICD1 / SUSCLK

For programming information, refer to Function 0 Rx74, 77, Function 4 Rx54[3-2], and Memory Mapped / Indexed APIC registers. Rx77[4] is “Internal APIC Enable”. The clock source used by the chip to clock the internal I/O APIC is OSC (14.31818 MHz), so OSC must be externally connected to the CPU I/O APIC clock input.

U10 I

V9 IO

T10 IO

Write Snoop Complete. Asserted by the north bridge to indicate that all

snoop activity on the CPU bus initiated by the last PCI-to-DRAM write is complete and that it is safe to perform an APIC interrupt.

APIC Data 0. 1.5V interface. APIC Data 1. 1.5V interface.

Revision 2.37, November 10, 2004 -10- Pinouts

VT82C686B "Super South" South Bridge

Universal Serial Bus Interface

Signal Name Pin # I/O Signal Description

USBP0+ USBP0USBP1+ USBP1USBP2+ USBP2USBP3+ USBP3USBCLK USBOC0# / GPO25 / DACK2#

USBOC1# / GPO24 / DRQ2 / SERIRQ

USBOC0# (SD2 & RFSH#) USBOC1# (SD1 & RFSH#) USBOC2# (SD0 & RFSH#) USBOC3# (SD3 & RFSH#)

USBIRQA / DACK6# USBIRQB / DACK7#

A3 IO

B3 IO

C4 IO D4 IO A4 IO

B4 IO

B5 IO

E6 IO

C3 I G5 I

H3 I

(W2) I

(Y2) I (Y1) I (Y3) I

M3 O N2 O

USB Port 0 Data + USB Port 0 Data USB Port 1 Data + USB Port 1 Data USB Port 2 Data + USB Port 2 Data USB Port 3 Data + USB Port 3 Data USB Clock. 48MHz clock input for the USB interface USB Port 0 Over Current Detect. Port 0 is disabled if low. USBOC0# if Rx76[7] = 1 and Rx76[6] = 0 USB Port 1 Over Current Detect. Port 1 is disabled if this input

is low. Direct inputs are provided for overcurrent protection for ports 0 and 1 which may be used if the alternate functions of these two pins are not required. If overcurrent protection is desired on all four ports (or it is desired to use the alternate functions of these two pins), an external buffer may be used to drive the state of USBOC[3-0]# onto SD[3-0] during ISA bus refresh cycles (i.e., while ISA bus RFSH# is low, so that RFSH# may be used as the buffer enable). USCOC1# if Rx76[7] = 1 and Rx76[6] = 0.

USB Port 0 Over Current Detect USB Port 1 Over Current Detect USB Port 2 Over Current Detect USB Port 3 Over Current Detect

USB Interrupt Request A. Output of internal block. USB Interrupt Request B. Output of internal block.

System Management Bus (SMB) Interface (I2C Bus)

Signal Name Pin # I/O Signal Description

SMBCLK SMBDATA SMBALRT# / GPI6

Revision 2.37, November 10, 2004 -11- Pinouts

U9 IO

T9 IO

W10 I

SMB / I2C Clock. SMB / I2C Data. SMB Alert. (System Management Bus I/O space Rx08[3] = 1)

When the chip is enabled to allow it, assertion generates an IRQ or SMI interrupt or a power management resume event. The same pin is used as General Purpose Input 6 whose value is reflected in Rx48[6] of function 4 I/O space

VT82C686B "Super South" South Bridge

UltraDMA-33 / 66 / 100 Enhanced IDE Interface

Signal Name Pin # I/O Signal Description

PDRDY /

PDDMARDY / PDSTROBE

SDRDY / SDDMARDY / SDSTROBE

PDIOR# / PHDMARDY / PHSTROBE

SDIOR# / SHDMARDY / SHSTROBE

PDIOW# / PSTOP

SDIOW# / SSTOP

PDDRQ SDDRQ PDDACK# SDDACK# IRQ14 IRQ15

N16 I

V20 I

N17 O

W19 O

N18 O

W20 O

N19 I Y20 I

M20 O

V19 O

L1 I K5 I

EIDE Mode: Primary I/O Channel Ready. Device ready indicator UltraDMA Mode: Primary Device DMA Ready. Output flow control. The device

Primary Device Strobe. Input data strobe (both edges). The

EIDE Mode: Secondary I/O Channel Ready. D UltraDMA Mode: Secondary Device DMA Ready. O

Secondary Device Strobe. Input data strobe (both edges). The

EIDE Mode: Primary Device I/O Read. UltraDMA Mode: Primary Host DMA Ready. Primary

Primary Host Strobe. Output data strobe (both edges). The

EIDE Mode: Secondary Device I/O Read. UltraDMA Mode: Secondary Host DMA Ready. Input flow control. The host

Host Strobe B. Output strobe (both edges). The host may stop

EIDE Mode: Primary Device I/O Write. Device write strobe UltraDMA Mode: Primary Stop. Stop transfer: Asserted by the host prior to

EIDE Mode: Secondary Device I/O Write. Device write strobe UltraDMA Mode: Secondary Stop. Stop transfer: Asserted by the host prior to

Primary Device DMA Request. Primary channel DMA request Secondary Device DMA Request. Secondary channel DMA request Primary Device DMA Acknowledge. Primary channel DMA acknowledge Secondary Device DMA Acknowledge. Secondary channel DMA acknowledge Primary Channel Interrupt. Secondary Channel Interrupt.

may assert DDMARDY to pause output transfers

device may stop DSTROBE to pause input data transfers

evice ready indicator

utput flow control. The

device may assert DDMARDY to pause output transfers

device may stop DSTROBE to pause input data transfers

Device read strobe

channel input flow control. The host may assert HDMARDY to pause input transfers

host may stop HSTROBE to pause output data transfers

Device read strobe

may assert HDMARDY to pause input transfers

HSTROBE to pause output data transfers

initiation of an UltraDMA burst; negated by the host before data is transferred in an UltraDMA burst. Assertion of STOP by the host during or after data transfer in UltraDMA mode signals the termination of the burst.

Revision 2.37, November 10, 2004 -12- Pinouts

VT82C686B "Super South" South Bridge

UltraDMA-33 / 66 / 100 Enhanced IDE Interface (continued)

Signal Name Pin # I/O Signal Description

PDCS1#

PDCS3#

SDCS1#

SDCS3#

PDA[2-0]

SDA[2-0]

PDD[15-0]

SDD[15-0] / SA[15-0]

IDEIRQA / DACK0# IDEIRQB / DACK1#

L20 O

M16 O

U17 O

U18 O

M18, M19, M17 O

U20, V18, U19 O

N20, P17, P19, R16, R18, R20, T17, T19, T20, T18, T16, R19,

R17, P20, P18, P16

P5, R1-R5, T1-T4,

U1-U3, V1, V2, W1

L2 O E1 O

Primary Master Chip Select. This signal corresponds to CS1FX# on

the primary IDE connector. Primary Slave Chip Select. This signal corresponds to CS3FX# on the

primary IDE connector. Secondary Master Chip Select. This signal corresponds to CS17X# on

the secondary IDE connector. Secondary Slave Chip Select. This signal corresponds to CS37X# on

the secondary IDE connector. Primary Disk Address. PDA[2:0] are used to indicate which byte in

either the ATA command block or control block is being accessed. Secondary Disk Address. SDA[2:0] are used to indicate which byte in

either the ATA command block or control block is being accessed.

Primary Disk Data

Secondary Disk Data muxed with ISA Bus Address.

IDE Interrupt Request A. Output of internal block. IDE Interrupt Request B. Output of internal block.

Revision 2.37, November 10, 2004 -13- Pinouts

VT82C686B "Super South" South Bridge

MIDI Interface

Signal Name Pin # I/O Signal Description

MSI MSO

Y19 I Y18 O

MIDI Serial In

MIDI Serial Out

AC97 Audio / Modem Interface

Signal Name Pin # I/O Signal Description

ACRST ACSDOUT ACSYNC ACSDIN2 ACSDIN ACBTCK AC97IRQ / DACK3# MC97IRQ / DACK5#

/ SERIRQ / GPO19

U15 O Y16 O V16 O Y17 I V17 I

W18 I

D2 O

L4 O

AC97 Reset AC97 Serial Data Out AC97 Sync AC97 Serial Data In 2 AC97 Serial Data In AC97 Bit Clock AC97 Interrupt Request. Output of internal block. MC97 Interrupt Request. Output of internal block. Rx77[7] = 1, Rx77[3] = 1, Rx74[6] = 0.

Game Port Interface

Signal Name Pin # I/O Signal Description

JAB1 JAB2 JBB1 JBB2 JAX / GPO23 JAY / GPO22 JBX / GPI23 JBY / GPI22

See Function 0 Rx77[6]

W16 I

T15 I

W17 I

U16 I V15 I Y15 I U14 I

W15 I

Joystick A Button 1 Joystick A Button 2

Joystick B Button 1 Joystick B Button 2 Joystick A X-axis Joystick A Y-axis Joystick B X-axis Joystick B Y-axis

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VT82C686B "Super South" South Bridge

Floppy Disk Interface

Signal Name Pin # I/O Signal Description

DRVDEN0 DRVDEN1 MTR0# MTR1# DS0# DS1# DIR# STEP# INDEX# HDSEL# TRK00# RDATA# WDATA# WGATE# DSKCHG#

WRTPRT#

D9 O D6 O E9 O C8 O B8 O A8 O D8 O E8 O D7 I C7 O E7 I B6 I A7 O B7 O C6 I

A6 I

Drive Density Select 0. Drive Density Select 1. Motor Control 0. Select motor on drive 0. Motor Control 1. Select motor on drive 1 Drive Select 0. Select drive 0. Drive Select 1. Select drive 1 Direction. Direction of head movement (0 = inward motion, 1 = outward motion) Step. Low pulse for each track-to-track movement of the head. Index. Sense to detect that the head is positioned over the beginning of a track Head Select. Selects the side for R/W operations (0 = side 1, 1 = side 0) Track 0. Sense to detect that the head is positioned over track 0. Read Data. Raw serial bit stream from the drive for read operatrions. Write Data. Encoded data to the drive for write operations. Write Gate. Signal to the drive to enable current flow in the write head. Disk Change. Sense that the drive door is open or the diskette has been changed since the last drive selection. Write Protect. Sense for detection that the diskette is write protected (causes write

commands to be ignored)

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VT82C686B "Super South" South Bridge

Parallel Port Interface

Signal Name Pin # I/O Signal Description

PINIT# / DIR# STROBE# / nc AUTOFD# / DRVEN0

SLCTIN# / STEP# SLCT / WGATE# ACK# / DS1#

ERROR# / HDSEL#

BUSY / MTR1# PE / WDATA# PD7 / nc, PD6 / nc, PD5 / nc, PD4 / DSKCHG#, PD3 / RDATA#, PD2 / WRTPRT#, PD1 / TRK00#, PD0 / INDEX#

As shown by the alternate functions above, in mobile applications the parallel port pins can optionally be selected to function as a floppy disk interface for attachment of an external floppy drive using the parallel port connector (see Super I/O Configuration Index F6[5]).

C15 IO / O D16 IO / C16 IO / O

E15 IO / O E13 I / O B13 I / O

A15 I / O

C13 I / O D13 I / O

A13,

E14,

D14,

C14,

B14, A14, D15,

B15

IO / IO / IO / IO / I IO / I IO / I IO / I IO / I

Initialize. Initialize printer. Output in standard mode, I/O in ECP/EPP mode. Strobe. Output used to strobe data into the printer. I/O in ECP/EPP mode. Auto Feed. Output used to cause the printer to automatically feed one line after

each line is printed. I/O pin in ECP/EPP mode.

Select In. Output used to select the printer. I/O pin in ECP/EPP mode. Select. Status output from the printer. High indicates that it is powered on. Acknowledge. Status output from the printer. Low indicates that it has received

the data and is ready to accept new data Error. Status output from the printer. Low indicates an error condition in the

printer.

Busy. Status output from the printer. High indicates not ready to accept data. Paper End. Status output from the printer. High indicates that it is out of paper. Parallel Port Data.

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VT82C686B "Super South" South Bridge

Serial Ports and Infrared Interface

Signal Name Pin # I/O Signal Description

TXD1 TXD2 IRTX / GPO14

RXD1 RXD2 IRRX / GPO15

RTS1#

RTS2##

CTS1#

CTS2#

DTR1#

DTR2#

DSR1#

DSR2#

DCD1#

DCD2#

RI1#

RI2#

A11 O D10 O

E12 O

B12 I B10 I D12 IO

B11 O

E10 O

C11 I

A9 I

D11 O

B9 O

C12 I

C10 I

A12 I

A10 I

E11 I

C9 I

Transmit Data 1. Serial port 1 transmit data out. Transmit Data 2. Serial port 2 transmit data out. Infrared Transmit. IR transmit data out (Rx76[5] = 0) from serial port 2.

General Purpose Output 14 if Rx76[5] = 1 Receive Data 1. Serial port 1 receive data in. Receive Data 2. Serial port 2 receive data in. Infrared Receive. IR receive data in (Rx76[5] = 0) to serial port 2. General

Purpose Output 15 if Rx76[5] = 1

Request To Send 1. Indicator that serial output port 1 is ready to transmit data.

Typically used as hardware handshake with CTS1# for low level flow control. Designed for direct input to external RS-232C driver.

Request To Send 2. Indicator that serial output port 2 is ready to transmit data. Typically used as hardware handshake with CTS2# for low level flow control. Designed for direct input to external RS-232C driver.

Clear To Send 1. Indicator to serial port 1 that external communications device is ready to receive data. Typically used as hardware handshake with RTS1# for low level flow control. Designed for input from external RS-232C receiver.

Clear To Send 2. Indicator to serial port 2 that external communications device is ready to receive data. Typically used as hardware handshake with RTS2# for low level flow control. Designed for input from external RS-232C receiver.

Data Terminal Ready 1. Serial port 1 indicator that port is powered, initialized, and ready. Typically used as hardware handshake with DSR1# for overall readiness to communicate. Designed for direct input to external RS-232C driver.

Data Terminal Ready 2. Serial port 2 indicator that port is powered, initialized, and ready. Typically used as hardware handshake with DSR2# for overall readiness to communicate. Designed for direct input to external RS-232C driver.

Data Set Ready 1. Indicator to serial port 1 that external serial communications device is powered, initialized, and ready. Typically used as hardware handshake with DTR1# for overall readiness to communicate. Designed for direct input from external RS-232C receiver. Data Set Ready 2. Indicator to serial port 2 that external serial communications device is powered, initialized, and ready. Typically used as hardware handshake with DTR2# for overall readiness to communicate. Designed for direct input from external RS-232C receiver.

Data Carrier Detect 1. Indicator to serial port 1 that external modem is detecting a carrier signal (i.e., a communications channel is currently open). In direct connect environments, this input will typically be driven by DTR1# as part of the DTR/DSR handshake. Designed for direct input from external RS-232C receiver.

Data Carrier Detect 2. Indicator to serial port 2 that external modem is detecting a carrier signal (i.e., a communications channel is currently open). In direct connect environments, this input will typically be driven by DTR2# as part of the DTR/DSR handshake. Designed for direct input from external RS-232C receiver.

Ring Indicator 1. Indicator to serial port 1 that external modem is detecting a ring condition. Used by software to initiate operations to answer and open the communications channel. Designed for direct input from external RS-232C receiver (whose input is typically not connected in direct connect environments). Ring Indicator 2. Indicator to serial port 2 that external modem is detecting a ring condition. Used by software to initiate operations to answer and open the communications channel. Designed for direct input from external RS-232C receiver (whose input is typically not connected in direct connect environments).

Revision 2.37, November 10, 2004 -17- Pinouts

VT82C686B "Super South" South Bridge

ISA Bus Interface

Signal Name Pin # I/O Signal Description

SA[19:16], SA[15-0] / SDD[15-0]

LA[23:20]

SD[15:0]

SBHE#

IOR#

IOW#

MEMR#

MEMW#

SMEMR#

SMEMW#

BALE

IOCS16#

MCS16#

IOCHCK# /

GPI0

IOCHRDY

AEN

K1, K2, P3, P4, P5, R1, R2, R3, R4, R5, T1, T2,

T3, T4, U1, U2,

U3, V1, V2,

J2, J3, J4, J5 IO

P2, P1, N5, N3,

N1, M4, M2,

L5, W4, Y4,

V3, W3, Y3,

W2, Y2, Y1

F2 IO

D1 IO

C2 IO

U4 IO

V4 IO

A1 O

B1 O

H2 O

F3 I

F1 I

F4 I

A2 I

B2 O

System Address Bus. SA[19-16] are connected to ISA bus SA[19-16] directly.

SA[19-17] are also connected to LA[19-17] of the ISA bus. SA[15-0] are multiplexed with the IDE Secondary Data Bus. SA[15-0] may be connected to both SDD[15-0] and ISA bus SA[15-0], however if ISA address bus loading is a concern, 74F245 transceivers may be used to externally drive ISA address bus pins SA[15-0]. In this case, these pins would connect directly to the IDE secondary data bus and to the transceiver “A” pins and the ISA address bus would connect to the transceiver “B” pins. SOE# would be used to control the transceiver output enables and the ISA bus MASTER# signal would drive the transceiver direction controls.

System “Latched” Address Bus: The LA[23:20] address lines are bi-directional. These address lines allow accesses to physical memory on the ISA bus up to 16Mbytes. LA[19-17] on the ISA bus are connected to SA[19-17] (see notes above).

System Data. SD[15:0] provide the data path for devices residing on the ISA bus. X-Bus data signals XD[7:0] may be derived if needed from SD[7:0] using an external 74F245-type transceiver (see the XDIR pin description for transceiver connection details). SD7:4 are strap options for keyboard inputs 6:3 (see Function 0 Rx5A)

System Byte High Enable. SBHE# indicates, when asserted, that a byte is being transferred on the upper byte (SD[15:8]) of the data bus. SBHE# is negated during refresh cycles.

I/O Read. IOR# is the command to an ISA I/O slave device that the slave may drive data on to the ISA data bus.

I/O Write. IOW# is the command to an ISA I/O slave device that the slave may latch data from the ISA data bus.

Memory Read. MEMR# is the command to a memory slave that it may drive data onto the ISA data bus.

Memory Write. MEMW# is the command to a memory slave that it may latch data from the ISA data bus.

Standard Memory Read. SMEMR# is the command to a memory slave, under 1MB, which indicates that it may drive data onto the ISA data bus

Standard Memory Write. SMEMW# is the command to a memory slave, under 1MB, which indicates that it may latch data from the ISA data bus.

Bus Address Latch Enable. BALE is an active high signal asserted by the VT82C686B to indicate that the address (SA[19:0], LA[23:17] and the SBHE# signal) is valid

16-Bit I/O Chip Select. This signal is driven by I/O devices on the ISA Bus to indicate that they support 16-bit I/O bus cycles.

Memory Chip Select 16. ISA slaves that are 16-bit memory devices drive this line low to indicate they support 16-bit memory bus cycles.

I/O Channel Check (Rx74[0] = 1). When this signal is asserted, it indicates that a parity or an uncorrectable error has occurred for an I/O or memory device on the ISA Bus. The same pin may optionally be used as General Purpose Input 0. I/O Channel Ready (Rx74[0] = 1). This signal is normally high. Devices on the ISA Bus assert IOCHRDY low to indicate that additional time (wait states) is required to complete the cycle.

Address Enable. AEN is asserted during DMA cycles to prevent I/O slaves from misinterpreting DMA cycles as valid I/O cycles.

Revision 2.37, November 10, 2004 -18- Pinouts

VT82C686B "Super South" South Bridge

ISA Bus Interface (continued)

Signal Name Pin # I/O Signal Description

RFSH#

IRQ0 / GPI10 / GPO10 / GPIOC / CHAS

IRQ1 / MSCK IRQ3 IRQ4 IRQ5 IRQ6 / GPI4 / SLPBTN# IRQ7 IRQ8# / GPI1 IRQ9 IRQ10 IRQ11 IRQ12 / MSDT IRQ14 IRQ15 DRQ7 / GPI21, DRQ6 / GPI20, DRQ5 / GPI19, DRQ3 / GPI18, DRQ2 / SERIRQ / GPO24

/ USBOC1# DRQ1 / GPI17, DRQ0 / GPI16 DACK7# / USBIRQB / GPO21 / THRM#, DACK6# / USBIRQA / GPO20, DACK5# / MC97IRQ / GPO19 / SERIRQ, DACK3# / AC97IRQ / GPO18, DACK2# / USBOC0# / GPO25 DACK1# / IDEIRQB / GPO17, DACK0# / IDEIRQA / GPO16

TC SPKR SOE# (default pin function)

/ GPO13 / MCCS#

E3 IO

V14 I

D5 I G4 I G3 I G2 I G1 I

F5 I

W11 I

H4 I K3 I K4 I C5 I L1 I K5 I

N4, M5, M1,

D3,

H3,

E2,

N2,

M3,

L4,

D2,

G5,

E1,

L2 H1 O V5 O U5 O

I I I I I

I I

O O

Refresh. Indicates when a refresh cycle is in progress. Also driven by 16bit ISA Bus masters to indicate a refresh cycle.

Interrupt Request 0. (Rx77[3] = 1)

Interrupt Request 1. (Rx5A[1] = 0) (used for external KBC interrupt) Interrupt Request 3. (typically used for COM2 serial port interrupt) Interrupt Request 4. (typically used for COM1 serial port interrupt) Interrupt Request 5. Interrupt Request 6. (typically used for FDC floppy ctrlr interrupt) Interrupt Request 7. (typically used for LPT parallel port interrupt) Interrupt Request 8 from ext RTC if int RTC disabled (Rx5A[2] = 0) Interrupt Request 9. Interrupt Request 10. Interrupt Request 11. Interrupt Request 12. (Rx5A[1] = 0) Interrupt Request 14. (typically used for IDE primary chan interrupt) Interrupt Request 15. (typically used for IDE secondary ch interrupt) DMA Request. Used to request DMA services from the internal DMA

controller.

DRQ2: Rx68[3] = 0 & Rx75[3] = 0 & Rx75[1] = 0 See also Function 0 Rx77[7]

Acknowledge. Used by the internal DMA controller to indicate that a

request for DMA service has been granted.

DACK5#: Rx77[7] = 0

DACK2#: Rx68[3] = 0 & Rx75[3] = 0 & Rx75[2] = 0 See also Function 0 Rx77[7], Rx77[3], and Rx58

Terminal Count. Terminal count indicator asserted to DMA slaves. Speaker Drive. Output of internal timer/counter 2. ISA Address (SA) Output Enable. Asserted low when ISA address (SA)

is valid (deasserted when SDD is valid) when SA and SDD are multiplexed on SA pins 15-0 (i.e., when SPKR is strapped low to enable the audio interface pins). SOE# is tied directly to the output enable of 74F245 transceivers that buffer IDE Secondary Bus data and ISA-address (see SA pins for more information).

Revision 2.37, November 10, 2004 -19- Pinouts

VT82C686B "Super South" South Bridge

XD Interface

Signal Name Pin # I/O Signal Description

XDIR / PCS0# / GPO12

T5 O

X-Bus Data Direction. (Rx76[1]=0) Asserted low for all I/O read cycles and for

memory read cycles to the programmed BIOS address space. XDIR is tied directly to the direction control of a 74F245 transceiver that buffers the X-Bus data and ISA-Bus data. The transceiver output enable may be grounded. SD0-7 connect to the “A” side of the transceiver and XD0-7 connect to the “B” side. XDIR high indicates that SD0-7 drives XD0-7.

Serial IRQ

Signal Name Pin # I/O Signal Description

SERIRQ / DRQ2

/ GPO24 / USBOC1# SERIRQ / DACK5# / GPO19 / MC97IRQ

H3 I

L4 I

Serial IRQ (Rx68[3] = 1, Rx74[6] = 0 and Rx75[3] = 1)

Serial IRQ (Rx68[3] = 1 and Rx74[6] = 1)

Revision 2.37, November 10, 2004 -20- Pinouts

VT82C686B "Super South" South Bridge

Internal Keyboard Controller

Signal Name Pin # I/O Signal Description

MSCK / IRQ1

MSDT / IRQ12

KBCK / A20GATE

KBDT / KBRC

KBCS# / ROMCS# / strap

KBIN[6-3] / SD[7-4]

D5 IO / I

C5 IO / I

E5 IO / I

A5 IO / I

C1 O / O / I

W4,

Y4, V3, W3

I / IO

MultiFunction Pin (Internal mouse controller enabled by Rx5A[1]) Rx5A[1]=1 Mouse Clock. From internal mouse controller. Rx5A[1]=0 Interrupt Request 1. Interrupt input 1. MultiFunction Pin (Internal mouse controller enabled by Rx5A[1]) Rx5A[1]=1 Mouse Data. From internal mouse controller. Rx5A[1]=0 Interrupt Request 12. Interrupt input 12.

MultiFunction Pin (Internal keyboard controller enabled by Rx5A[0]) Rx5A[0]=1 Keyboard Clock. From internal keyboard controller Rx5A[0]=0 Gate A20. Input from external keyboard controller. MultiFunction Pin (Internal keyboard controller enabled by Rx5A[0]) Rx5A[0]=1 Keyboard Data. From internal keyboard controller. Rx5A[0]=0 Keyboard Reset. From external keyboard controller (KBC)

for CPURST# generation

Keyboard Chip Select (Rx5A[0]=0). To external keyboard controller chip.

Power-Up Configuration Strap (Sampled At Reset):

4.7K to GND = Socket-7, 4.7K to VCC3 = Socket-370 / Slot-1 Keyboard Inputs 6-3. Sampled at reset on SD[7-4] and latched into

Rx5A[7-4].

Chip Selects

Signal Name Pin # I/O Signal Description

ROMCS# / KBCS# / strap

PCS0# / GPO12 / XDIR

MCCS# / GPO13 / SOE#

MCCS# / GPI11 / GPO11

/ GPIOD

C1 O

T5 O

U5 O

U8 O

ROM Chip Select (Rx5A[0]=1). Chip Select to the BIOS ROM. Power-Up Configuration Strap (Sampled At Reset):

4.7K to GND = Socket-7, 4.7K to VCC3 = Socket-370 / Slot-1 Programmable Chip Select 0 (Rx76[1] = 1 and Rx8B[0] = 1). Asserted

during I/O cycles to programmable read or write ISA I/O port ranges. Addressed devices drive data to the SD pins (XDIR is disabled and the XBus is not implemented). See also Rx59[3] and Rx77[2].

Microcontroller Chip Select (Rx76[3] = 1, Rx76[4] = 0, Rx77[0] = 1).

Asserted during read or write accesses to I/O ports 62h or 66h.

Microcontroller Chip Select (Alternate Pin) (Rx76[4] = 0 selects MCCS#

on pin U8, Rx76[4] = 1 selects MCCS# on pin U5). Rx76[3] = 1 enables MCCS# output on the selected pin.

Revision 2.37, November 10, 2004 -21- Pinouts

VT82C686B "Super South" South Bridge

General Purpose Inputs

Signal Name Pin # I/O Signal Description

GPI0 / IOCHCK# GPI1 / IRQ8# GPI2 / BATLOW# GPI3 / LID / WSC# GPI4 / IRQ6 / SLPBTN# GPI5 / THRM / PME# GPI6 / SMBALRT# GPI7 / RING# GPI8 / GPO8 / GPIOA / GPOWE GPI9 / GPO9 / GPIOB / FAN2 GPI10 / GPO10 / GPIOC / CHAS / IRQ0 GPI11 / GPO11 / GPIOD / MCCS# GPI16 / DRQ0

GPI17 / DRQ1

GPI18 / DRQ3 GPI19 / DRQ5 GPI20 / DRQ6 GPI21 / DRQ7 GPI22 / JBY GPI23 / JBX GPI[23-16] (SD[7-0] & RFSH#)

Via VT82C686B User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual