VIA VT82C586B Datasheet
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EVISION HISTORY
Document Release Date Revision Initials
Revision 0.1 10/13/96 Initial release for 586A DH
Revision 0.5 12/23/96
reprinted
1/8/97
to fix
Acrobat
PDF file
size
problem
Incorrect
Change
Revision 1.0 5/13/97 • Overview Changes: Added System Block Diagram
Update to reflect 586B:
• Updated pin definitions:
Pins 18,31,33,58,60,131,133 (removed EXTSMI2-7 & DACEN)
Pins 77-78,80-83,85-86 (added GPI8-15 and GPO8-15)
Pins 94,87-88,92,136 (changed to GPIO0-4 and added alternate functions)
Pins 90,106,137 (added MIRQ0, MIRQ1, and MIRQ2 functions)
Pins 91,93,103,107 (changed to PWRBTN#, RI#, VDD-5VSB, PWRON)
Pins 113-114,116-119,121-122 (added GPI, GPO, and EXTSMI functions)
Fixed doc error DACK0-7 pin names changed to active low (DACK0-7#)
Removed options: IRQ12 (pin 137), strap (pin 48), RTCAS (pin 94)
• Updated register definitions
Removed VIA-specific port A8/A9 registers
Updated function 0 Rx5-4[3], Rx7-6[13], Rx41[0-4,6-7], Rx42[4-7], Rx44,
Rx46[2-4], Rx47[3], Rx48[3], Rx4A[4-6], Removed Rx50 (MDRQ)
Rx55[7-4] change PIRQD# to MIRQ1, Rx56 swap A/B, Rx57 swap C/D
Added 58-5B for PnP, XD, KBC/RTC config; added 60-6F for DDMA ctrl
Removed power mgmt regs 80-94 & added function 3 ACPI Power Mgmt
• Straps: moved 95-96 to 5A, allow RW after powerup, removed strap XD3
• Expanded CMOS RAM: added ports 72-75 & table 5 CMOS Reg Summary
• Added Power Management Subsystem Overview
• Incorporated App Note #53 APM-Compliant Pwr Mgmt Model of 82C586A
• Added AC Timing Section with IDE Interface Timing Diagrams & Specs
• Pin Function Changes:
Pin 90 added alternate function "POS" output
Pin 106 added alternate function "IRQ8#" input
Pin 137 added alternate function "SDDIR" output
• Register Definition Changes:
Fixed typos: Port 75 note, Fn0 Rx48[3], Rx55-57[7:0]; Fn1 Rx4[7]; Fn2
Rx3C-3D; Fn3 Rx26[9], Rx2F, Rx62-63, Table 7
Added missing register: Function 0 Rx59[3] MIRQ Pin Config Register
Function 0 PCI-to-ISA Bridge
Rx08[7:0] (changed) Revision Code Register
Rx2C[31:0] (new) Subsystem ID Register (read)
Rx41[0] (changed) ISA Test Mode Register
Rx46[7:5] and Rx48[5:4] (new) Misc Control Registers 1 and 3
Rx5C[0] (new) DMA Control Register
Rx70[31:0] (new) Subsystem ID Register (write)
Function 1 IDE Controller
Rx43[7] (new) FIFO Configuration Register
Rx44[1:0] (new) Misc Control Register 1
Function 3 Power Management
Rx04[0] (moved to Rx41[7]) Command Register
Rx08[7:0] (changed) Revision ID Register
Rx10[4:1], Rx14 (changed) Processor Control and Processor Level 2
Rx20[31:0] (moved to Rx48) I/O Base Address Register
Power Management I/O
Rx40[6:5] (new) GPIO Direction Control Register
• Electrical Spec Changes: Added PCI Cycle Timing
• Mechanical Spec Changes: Added marking specs for 3040E/F, 3041 silicon
(3041 only silicon)
(3041 only silicon)
(3040F and 3041 silicon)
(3040F and 3041 silicon)
(3040F and 3041 silicon)
(3040F and 3041 silicon)
(3041 only silicon)
VT82C586B
DH
DH
Revision 1.0 May 13, 1997 -i- Revision History
9,$7HFKQRORJLHV,QF
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ABLE OF CONTENTS
VT82C586B
REVISION HISTORY........................................................................................................................................................................I
TABLE OF CONTENTS..................................................................................................................................................................II
LIST OF FIGURES..........................................................................................................................................................................III
LIST OF TABLES ...........................................................................................................................................................................IV
OVERVIEW.......................................................................................................................................................................................3
PINOUTS............................................................................................................................................................................................4
REGISTERS.....................................................................................................................................................................................14
EGISTER OVERVIEW
R
ONFIGURATION SPACE
C
EGISTER DESCRIPTIONS
R
.................................................................................................................................................................14
I/O .......................................................................................................................................................20
............................................................................................................................................................21
Legacy I/O Ports...................................................................................................................................................................21
Keyboard Controller Registers..............................................................................................................................................................22
DMA Controller I/O Registers..............................................................................................................................................................24
Interrupt Controller Registers ............................................................................................................................................................... 25
Timer / Counter Registers .....................................................................................................................................................................25
CMOS / RTC Registers......................................................................................................................................................................... 26
PCI to ISA Bridge Registers (Function 0) ..........................................................................................................................27
PCI Configuration Space Header.......................................................................................................................................................... 27
ISA Bus Control.................................................................................................................................................................................... 27
Plug and Play Control........................................................................................................................................................................... 30
Distributed DMA Control..................................................................................................................................................................... 32
Miscellaneous ....................................................................................................................................................................................... 32
Enhanced IDE Controller Registers (Function 1)..............................................................................................................33
PCI Configuration Space Header.......................................................................................................................................................... 33
IDE-Controller-Specific Confiiguration Registers................................................................................................................................ 35
IDE I/O Registers..................................................................................................................................................................................37
Universal Serial Bus Controller Registers (Function 2)....................................................................................................38
PCI Configuration Space Header.......................................................................................................................................................... 38
USB-Specific Configuration Registers..................................................................................................................................................39
USB I/O Registers................................................................................................................................................................................. 39
Power Management Registers (Function 3)........................................................................................................................40
PCI Configuration Space Header.......................................................................................................................................................... 40
Power Management-Specific PCI Configuration Registers .................................................................................................................. 41
Power Management Subsystem Overview ............................................................................................................................................43
Power Management I/O-Space Registers..............................................................................................................................................46
ELECTRICAL SPECIFICATIONS...............................................................................................................................................55
BSOLUTE MAXIMUM RATINGS
A
HARACTERISTICS
DC C
IMING SPECIFICATIONS
AC T
................................................................................................................................................................55
.................................................................................................................................................55
......................................................................................................................................................56
PACKAGE MECHANICAL SPECIFICATIONS........................................................................................................................63
Revision 1.0 May 13, 1997 -ii- Table of Contents
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IST OF FIGURES
FIGURE 1. PC SYSTEM CONFIGURATION USING THE VT82C586B ................................................................................. 3
FIGURE 2. PIN DIAGRAM.............................................................................................................................................................4
FIGURE 3. STRAP OPTION CIRCUIT....................................................................................................................................... 31
FIGURE 4. POWER MANAGEMENT SUBSYSTEM BLOCK DIAGRAM........................................................................... 43
FIGURE 5. ULTRADMA-33 IDE TIMING - DRIVE INITIATING DMA BURST FOR READ COMMAND.................... 58
FIGURE 6. ULTRADMA-33 IDE TIMING - DRIVE INITIATING BURST FOR WRITE COMMAND............................58
FIGURE 7. ULTRADMA-33 IDE TIMING - PAUSING A DMA BURST ...............................................................................59
FIGURE 8. ULTRADMA-33 IDE TIMING - DRIVE TERMINATING DMA BURST DURING READ COMMAND......60
FIGURE 9. ULTRADMA-33 IDE TIMING - DRIVE TERMINATING DMA BURST DURING WRITE COMMAND ...60
FIGURE 10. ULTRADMA-33 IDE TIMING - HOST TERMINATING DMA BURST DURING READ COMMAND......61
FIGURE 11. ULTRADMA-33 IDE TIMING - HOST TERMINATING DMA BURST DURING WRITE COMMAND...61
FIGURE 12. ULTRADMA-33 IDE TIMING - PIO CYCLE......................................................................................................62
FIGURE 13. MECHANICAL SPECIFICATIONS - 208-PIN PLASTIC FLAT PACKAGE..................................................63
VT82C586B
Revision 1.0 May 13, 1997 -iii- List of Figures
9,$7HFKQRORJLHV,QF
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IST OF TABLES
TABLE 1. PIN DESCRIPTIONS.....................................................................................................................................................5
TABLE 2. SYSTEM I/O MAP....................................................................................................................................................... 14
TABLE 3. REGISTERS..................................................................................................................................................................14
TABLE 4. KEYBOARD CONTROLLER COMMAND CODES ..............................................................................................23
TABLE 5. CMOS REGISTER SUMMARY.................................................................................................................................26
TABLE 6. SCI/SMI/RESUME CONTROL FOR PM EVENTS.................................................................................................44
TABLE 7. SUSPEND RESUME EVENTS AND CONDITIONS ...............................................................................................44
TABLE 8. AC CHARACTERISTICS - PCI CYCLE TIMING..................................................................................................56
TABLE 9. AC CHARACTERISTICS - ULTRADMA-33 IDE BUS INTERFACE TIMING.................................................. 57
VT82C586B
Revision 1.0 May 13, 1997 -iv- List of Tables
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VT82C586B
VT82C586B PIPC
PCI I
WITH
M
ASTER MODE
USB C
• PC97 Compliant PCI to ISA Bridge
ONTROLLER
−
Integrated ISA Bus Controller with integrated DMA, timer, and interrupt controller
−
Integrated Keyboard Controller with PS2 mouse support
−
Integrated DS12885-style Real Time Clock with extended 256 byte CMOS RAM and Day/Month Alarm for ACPI
−
Integrated USB Controller with root hub and two function ports
−
Integrated master mode enhanced IDE controller with enhanced PCI bus commands and UltraDMA-33 extensions
−
PCI-2.1 compliant with delay transaction
−
Eight double-word line buffer between PCI and ISA bus
−
One level of PCI to ISA post-write buffer
−
Supports type F DMA transfers
−
Distributed DMA support for ISA legacy DMA across the PCI bus
−
Fast reset and Gate A20 operation
−
Edge trigger or level sensitive interrupt
−
Flash EPROM, 2MB EPROM and combined BIOS support
−
Programmable ISA bus clock
−
Supports external IOAPIC interface for symmetrical multiprocessor configurations
NTEGRATED PERIPHERAL CONTROLLER
PC97 C
ACPI, D
OMPLIANT
ISTRIBUTED
PCI IDE C
, K
EYBOARD CONTROLLER, AND REAL TIME CLOCK
PCI-TO-ISA B
DMA, P
RIDGE
LUG AND PLAY
ONTROLLER WITH ULTRA
,
DMA-33,
• Inter-operable with VIA and other Host-to-PCI Bridges
−
Combine with VT82C585VPX/587VP for a complete 75MHz 6x86 / PCI / ISA system (Apollo VPX)
−
Combine with VT82C595 for a complete Pentium / PCI / ISA system (Apollo VP2)
−
Combine with VT82C685/687 for a complete Pentium-Pro /PCI / ISA system (Apollo P6)
−
Combine with VIA Apollo-AGP and Apollo Pro chipsets for new high-performance / enhanced-functionality systems
−
Inter-operable with other Intel or non-Intel Host-to-PCI bridges for a complete PC97 compliant PCI/ISA system
• Enhanced Master Mode PCI IDE Controller with Extension to UltraDMA-33
−
Dual channel master mode PCI supporting four Enhanced IDE devices
−
Transfer rate up to 33MB/sec to cover PIO mode 4, multi-word DMA mode 2 drives, and UltraDMA-33 interface
−
Sixteen levels (doublewords) of prefetch and write buffers
−
Interlaced commands between two channels
−
Bus master programming interface for SFF-8038i rev.1.0 and Windows-95 compliant
−
Full scatter gather capability
−
Support ATAPI compliant devices including DVD devices
−
Support PCI native and ATA compatibility modes
−
Complete software driver support
Revision 1.0 May 13, 1997 -1- Features
9,$7HFKQRORJLHV,QF
Universal Serial Bus Controller
•
−
USB v.1.0 and Intel Universal HCI v.1.1 compatible
−
Eighteen level (doublewords) data FIFO with full scatter and gather capability
−
Root hub and two function ports
−
Integrated physical layer transceivers with over-current detection status on USB inputs
−
Legacy keyboard and PS/2 mouse support
Sophisticated PC97-Compatible Power Management
•
−
Supports both ACPI (Advanced Configuration and Power Interface) and legacy (APM) power management
−
ACPI v1.0 Compliant (all required features plus extensions for most efficient desktop power management)
−
APM v1.2 Compliant
−
Supports soft-off (suspend to disk) and power-on suspend with hardware automatic wake-up
−
One idle timer, one peripheral timer and one general purpose timer, plus 24/32-bit ACPI compliant timer
−
Dedicated input pin for external modem ring indicator for system wake-up
−
Enhanced integrated real time clock (RTC) with date alarm, month alarm, and century field
−
Normal, doze, sleep, suspend and conserve modes
−
System event monitoring with two event classes
−
Five multi-purpose I/O pins plus support for up to 16 general purpose input ports and 16 output ports
−
I2C serial bus support for JEDEC-compatible DIMM identification and on-board-device power control
−
Seven external event input ports with programmable SMI condition
−
Primary and secondary interrupt differentiation for individual channels
−
Clock throttling control
−
Multiple internal and external SMI sources for flexible power management models
VT82C586B
Plug and Play Controller
•
−
PCI interrupts steerable to any interrupt channel
−
Three steerable interrupt channels for on-board plug and play devices
−
Microsoft Windows 95
Pin-compatible upgrade from VT82C586 and VT82C586A for existing designs
•
Built-in Nand-tree pin scan test capability
•
0.5um mixed voltage, high speed and low power CMOS process
•
Single chip 208 pin PQFP
•
TM
and plug and play BIOS compliant
Revision 1.0 May 13, 1997 -2- Features
9,$7HFKQRORJLHV,QF
O
VERVIEW
VT82C586B
The VT82C586B PIPC (PCI Integrated Peripheral Controller) is a high integration, high performance and high compatibility
device that supports Intel and non-Intel based processor to PCI bus bridge functionality to make a complete Microsoft PC97compliant PCI/ISA system. In addition to complete ISA extension bus functionality, the VT82C586B includes standard intelligent
peripheral controllers:
a) Master mode enhanced IDE controller with dual channel DMA engine and interlaced dual channel commands. Dedicated
FIFO coupled with scatter and gather master mode operation allows high performance transfers between PCI and IDE
devices. In addition to standard PIO and DMA mode operation, the VT82C586B also supports the emerging UltraDMA-33
standard to allow reliable data transfer rates up to 33MB/sec throughput. The IDE controller is SFF-8038i v1.0 and
Microsoft Windows-95 compliant.
b) Universal Serial Bus controller that is USB v1.0 and Universal HCI v1.1 compliant. The VT82C586B includes the root hub
with two function ports with integrated physical layer transceivers. The USB controller allows hot plug and play and
isochronous peripherals to be inserted into the system with universal driver support. The controller also implements legacy
keyboard and mouse support so that legacy software can run transparently in a non-USB-aware operating system
environment.
c) Keyboard controller with PS2 mouse support.
d) Real Time Clock with 256 byte extended CMOS. In addition to the standard ISA RTC functionality, the integrated RTC also
includes the date alarm and other enhancements for compatibility with the ACPI standard.
e) Notebook-class power management functionality that is compliant with ACPI and legacy APM requirements. Two types of
sleep states (soft-off and power-on-suspend) are supported with hardware automatic wake-up. Additional functionality
includes event monitoring, CPU clock throttling (Intel processor pr otocol), modular power control, hardware- and software-
based event handling, general purpose IO, chip select and external SMI.
f) Distributed DMA capability for support of ISA legacy DMA over the PCI bus.
g) Plug and Play controller that allows complete steerability of all PCI interrupts to any interrupt channel. Three ad ditional
steerable interrupt channels are provided to allow plug and play and reconfigurability of on-board peripherals for W indows
95 compliance.
h) External IOAPIC support for Intel-compliant symmetrical multiprocessor systems.
The VT82C586B also enhances the functionality of the standard ISA peripherals. The integrated interrupt controller supports both
edge and level triggered interrupts channel by channel. The integrated DMA controller supports type F DMA in addition to
standard ISA DMA modes. Compliant with the PCI-2.1 specification, the VT82C586B supports delayed transactions so that
slower ISA peripherals do not block the traffic of the PCI bus. Special circuitry is built in to allow concurrent operation without
causing dead lock even in a PCI-to-PCI bridge environment The chip also includes eight levels (doublewords) of line buffers from
the PCI bus to the ISA bus to further enhance overall system performance.
CPU / Cache
Sideband Signals:
Init / CPUreset
IRQ / NMI
SMI / StopClk
FERR / IGNNE
Boot ROM
CA
CD
RTC
Crystal
North Bridge
VT82C586B
208PQFP
MA/RAS/CAS
MD
PCI
I2C (Module ID)
USB
KBC
IDE
GPIO, Power Control, Reset
ISA
System Memory
Expansion
Cards
Figure 1. PC System Configuration Using the VT82C586B
Revision 1.0 May 13, 1997 -3- Overview
9,$7HFKQRORJLHV,QF
GND
AD3
AD2
AD1
156
155
154
153
IOIOIO
VDD-PCI
AD4
AD5
AD6
AD7
CBE0#
AD8
AD9
AD10
GND
AD11
AD12
AD13
AD14
VDD-PCI
AD15
CBE1#
PAR
SERR#
STOP#
GND
DEVSEL#
TRDY#
IRDY#
FRAME#
CBE2#
AD16
VDD-PCI
AD17
AD18
AD19
GND
AD20
AD21
AD22
AD23
IDSEL
CBE3#
AD24
AD25
GND
VDD-PCI
AD26
AD27
AD28
AD29
AD30
AD31
PIRQD#
PIRQC#
PIRQB#
GND
157
IO
158
IO
159
IO
160
IO
161
IO
162
IO
163
IO
164
IO
165
166
IO
167
IO
168
IO
169
IO
170
171
IO
172
IO
173
IO
174
I
175
IO
176
177
IO
178
IO
179
IO
180
IO
181
IO
182
IO
183
184
IO
185
IO
186
IO
187
188
IO
189
IO
190
IO
191
IO
192
I
193
IO
194
IO
195
IO
196
197
198
IO
199
IO
200
IO
201
IO
202
IO
203
IO
204
I
205
I
206
I
207
208
I
I
O
O
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849
P
INOUTS
Figure 2. Pin Diagram
(EXTSMI3#)
(Strap)
(Strap)
(Strap)
(IRQ12)
VDD5
XD1
XD0
XDIR
MSDT
115
114
113
112
111
IOOIOIOIO
(GPI1) (GPO1)
(GPI0) (GPO0)
(EXTSMI0#)
‡ (POS) (MIRQ0)
(GPI15) (GPO15)
(GPI14) (GPO14)
(GPI13) (GPO13)
(GPI12) (GPO12)
(GPI11) (GPO11)
(GPI10) (GPO10)
(GPI9) (GPO9)
(GPI8) (GPO8)
AD0
PREQ#
PGNT#
SMI#
STPCLK#
A20M
NMI
INTR
VDD3
INIT
CPURST
152
151
150
149
148
147
146
145
144
143
OIOOOOOOOOO
IO
142
97&%
FERR#
GND
IGNNE#
PWRGD
141
140
139
138
I
(MIRQ2)
(EXTSMI4#)
(KBCS#)
(Strap)
MASTER#
GPIO4
ROMCS#
SPKR
DACK7#
DRQ7
137
136
135
134
133
132
OIO
IO
IOOIO
† (SDDIR)
(GPO_WE)
DACK6#
DRQ6
IRQ14
IRQ15
IRQ11
131
130
129
128
127
IIIII
(Strap) (EXTSMI7#)
(Strap) (EXTSMI6#)
(Strap) (EXTSMI5#)
(Strap) (EXTSMI4#)
IRQ10
IOCS16#
MEMW#
MEMR#
XD7
XD6
GND
XD5
XD4
126
125
124
123
122
121
120
119
I
IOIOIOIOIOIOIOIOIO
118
(GPI7) (GPO7)
(GPI6) (GPO6)
(GPI5) (GPO5)
(GPI4) (GPO4)
(GPI_RE#) (EXTSMI3#)
(Data) (I2CD2) (EXTSMI2#)
(Clock) (I2CD1) (EXTSMI1#)
XD3
XD2
117
116
(GPI3) (GPO3)
(GPI2) (GPO2)
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Note: Pin names in parentheses (...) indicate alternate function
‡ 3040 Rev F and Later Revisions
† 3041 Rev A and Later Revisions
III
I
O
O
O
OIO
IO
IO
IOIOIOIOIOIOIOIOIO
IO
I
OOO
O
IOIOIOIOIOIOIO
IO
I
I
(KA20G)
(KBRC#)
(IRQ1)
(MIRQ1) (IRQ8#) ‡
(RTCCS#)
KEYLOCK
KBDT
KBCK
PWRON
109
108
107
O
IO
OIO
50
RTCX2
106
105
I
O
I
104
103
I
102
101
100
I
99
IO
98
IO
97
IO
96
IO
95
O
94
I
93
IO
92
I
91
IO
90
I
89
IO
88
IO
87
IO
86
IO
85
84
IO
83
IO
82
IO
81
IO
80
79
IO
78
IO
77
I
76
I
75
I
74
I
73
I
72
I
71
IO
70
IO
69
68
IO
67
IO
66
IO
65
IO
64
IO
63
IO
62
I
61
O
60
I
59
O
58
I
57
O
56
O
55
O
54
53
O
51
52
MSCK
110
(IRQ8#)
O
VT82C586B
RTCX1
VDD-5VSB
VBAT
AGND
AVDD
USBCLK
USBDATA1USBDATA1+
USBDATA0USBDATA0+
GPIO0
RI#
GPIO3
PWRBTN#
APICCS#
DRDYB#
GPIO2
GPIO1
SD15
SD14
GND
SD13
SD12
SD11
SD10
VDD5
SD9
SD8
MEMCS16#
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
LA17/DA0
LA18/DA1
GND
LA19/DA2
LA20/DCS1A#
LA21/DCS3A#
LA22/DCS1B#
LA23/DCS3B#
SBHE#
IRQ9
DACK0#
DRQ0
DACK5#
DRQ5
SOE#
DIOWB#
DIORB#
VDD5
TC
DRQ3
DACK3#
DD8/SA8
REFRESH#
BALE
VDD5
DACK2#
DD7/SA7
DD6/SA6
GND
DD4/SA4
DD3/SA3
DD2/SA2
DD5/SA5
DDRQB
DDRQA
DD1/SA1
DD0/SA0
DDACKA#
GND
DIORA#
DIOWA#
DRDYA#
DDACKB#
PIRQA#
PCICLK
PCIRST#
RSTDRV
OSC
DRQ2
IOCHCK#
SMEMW#
IOCHRDY
IOR#
GND
IOW#
BCLK
SMEMR#
AEN
DRQ1
SA16
VDD5
DACK1#
DD15/SA15
GND
DD14/SA14
DD13/SA13
DD9/SA9
DD12/SA12
DD11/SA11
DD10/SA10
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Table 1. Pin Descriptions
CPU Interface
Signal Name Pin No. I/O Signal Description
CPURST 142 O
INTR 145 O
NMI 146 O
INIT 143 O
STPCLK# 148 O
SMI# 149 O
FERR# 141 O
IGNNE# 139 O
CPU Reset.
CPU Interrupt.
interrupt request is pending and needs service.
Non-Maskable Interrupt.
CPU. The VT82C586B generates an NMI when either SERR# or IOCHK# is
asserted.
Initialization.
on the PCI bus or if a soft reset is initiated by the register
Stop Clock.
different Power-Management events.
System Management Interrupt.
in response to different Power-Management events.
Numerical Coprocessor Error.
the CPU.
Ignore Numeric Error.
The VT82C586B asserts CPURST to reset the CPU during power-up.
INTR is driven by the VT82C586B to signal the CPU that an
The VT82C586B asserts INIT if it detects a shut-down special cycle
STPCLK# is asserted by the VT82C586B to the CPU in response to
VT82C586B
NMI is used to force a non-maskable interrupt to the
SMI# is asserted by the VT82C586B to the CPU
This signal is tied to the coprocessor error signal on
This pin is connected to the “ignore error” pin on the CPU.
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PCI Bus Interface
Signal Name Pin No. I/O Signal Description
PCLK 2 I
FRAME# 181 B
AD[31:0] 204-199, 196-
195, 192-189,
187-185, 183,
172, 170-167,
165-163, 161-
158, 155-152
C/BE[3:0]# 194, 182, 173,
162
IRDY# 180 B
TRDY# 179 B
STOP# 176 B
DEVSEL# 178 B
PAR 174 B
SERR# 175 I
IDSEL 193 I
PIRQA-D# 1, 207-205 I
PREQ# 151 O
PGNT# 150 I
PCI Clock.
Frame.
that one more data transfer is desired by the cycle initiator.
B
Address/Data Bus.
with FRAME# assertion and data is driven or received in following cycles.
B
Command/Byte Enable.
enables corresponding to supplied or requested data are driven on following clocks.
Initiator Ready.
Target Ready.
Stop.
Device Select.
positive or subtractive decoding.
Parity.
System Error.
error condition. Upon sampling SERR# active, the VT82C586B can be programmed
to generate an NMI to the CPU.
Initialization Device Select.
read and write cycles.
PCI Interrupt Request
INTD# pins as follows:
PCI Slot 1 INTA# INTB# INTC# INTD#
PCI Slot 2 INTB# INTC# INTD# INTA#
PCI Slot 3 INTC# INTD# INTA# INTB#
PCI Slot 4 INTD# INTA# INTB# INTC#
PCI Request.
PCI Grant.
VT82C586B.
PCLK provides timing for all transactions on the PCI Bus.
Assertion indicates the address phase of a PCI transfer. Negation indicates
Asserted when the initiator is ready for data transfer.
Asserted when the target is ready for data transfer.
Asserted by the target to request the master to stop the current transaction.
The VT82C586B asserts this signal to claim PCI transactions through
A single parity bit is provided over AD[31:0] and C/BE[3:0]#.
SERR# can be pulsed active by any PCI device that detects a system
This signal goes to the North Bridge to request the PCI bus.
This signal is driven by the North Bridge to grant PCI access to the
VT82C586B
The standard PCI address and data lines. The address is driven
The command is driven with FRAME# assertion. Byte
IDSEL is used as a chip select during configuration
. These pins are typically connected to the PCI bus INTA#-
PIRQA# PIRQB#
PIRQC# PIRQD#
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ISA Bus Control
Signal Name Pin No. I/O Signal Description
SA[15:0] /
DD[15:0]
SA16 19 B
LA23/DCS3B#,
LA22/DCS1B#,
LA21/DCS3A#,
LA20/DCS1A#,
LA[19:17] /
DA[2:0]
SD[15:8] /
GPI[15:8] /
GPO[15:8]
SBHE# 62 B
IOR# 12 B
IOW# 11 B
MEMR# 123 B
MEMW# 124 B
SMEMR# 10 O
SMEMW# 9 O
BALE 35 O
IOCS16# 125 I
MEMCS16# 76 I
IOCHCK# 5 I
IOCHRDY 8 I
20-25, 27-28,
36-38, 40-44
63-67, 69-70 B
86-85, 83-80,
78-77
B
System Address Bus / IDE Data Bus
System Address Bus
Multifunction Pins
ISA Bus Cycles:
Address: The LA[23:17] address lines are bi-directional. These address lines allow
accesses to physical memory on the ISA bus up to 16MBytes.
PCI IDE Cycles:
Chip Select: DCS1A# is for the ATA command register block and corresponds to
CS1FX# on the primary IDE connector. DCS3A# is for the ATA command register
block and corresponds to CS3FX# on the primary IDE connector. DCS1B# is for the
ATA command register block and corresponds to CS17X# on the primary IDE
connector. DCS3B# is for the ATA command register block and corresponds to
CS37X# on the primary IDE connector.
Disk Address: DA[2:0] are used to indicate which byte in either the ATA command
block or control block is being accessed.
B
System Data.
the ISA bus. These pins also function as
GPIO3_CFG bit is low (pin 92 becomes GPI_RE# for enabling external inputs onto
the SD pins using an external buffer). These pins also function as
Outputs
of an external latch).
System Byte High Enable.
transferred on the upper byte (SD[15:8]) of the data bus. SBHE# is negated during
refresh cycles.
I/O Read.
data on to the ISA data bus.
I/O Write.
latch data from the ISA data bus.
Memory Read.
onto the ISA data bus.
Memory Write.
from the ISA data bus.
Standard Memory Read.
1MB, which indicates that it may drive data onto the ISA data bus
Standard Memory Write.
1MB, which indicates that it may latch data from the ISA data bus.
Bus Address Latch Enable.
VT82C586B to indicate that the address (SA[19:0], LA[23:17] and the SBHE#
signal) is valid
16-Bit I/O Chip Select.
indicate that they support 16-bit I/O bus cycles.
Memory Chip Select 16.
low to indicate they support 16-bit memory bus cycles.
I/O Channel Check.
uncorrectable error has occurred for a device or memory on the ISA Bus.
I/O Channel Ready.
additional time (wait states) is required to complete the cycle.
SD[15:8] provide the high order byte data path for devices residing on
15-8 if the GPIO4_CFG bit is low (pin 136 becomes GPO_WE for control
IOR# is the command to an ISA I/O slave device that the slave may drive
IOW# is the command to an ISA I/O slave device that the slave may
MEMR# is the command to a memory slave that it may drive data
MEMW# is the command to a memory slave that it may latch data
VT82C586B
General Purpose Inputs
SBHE# indicates, when asserted, that a byte is being
SMEMR# is the command to a memory slave, under
SMEMW# is the command to a memory slave, under
BALE is an active high signal asserted by the
This signal is driven by I/O devices on the ISA Bus to
ISA slaves that are 16-bit memory devices drive this line
When this signal is asserted, it indicates that a parity or an
Devices on the ISA Bus negate IOCHRDY to indicate that
15-8 if the
General Purpose
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ISA Bus Control (continued)
Signal Name Pin No. I/O Signal Description
REFRESH# 29 B
AEN 15 O
IRQ15, 14, 119, 7-3
DRQ7-5, 3-0 132, 130, 57,
DACK7:5, 3-0# 133, 131, 58,
TC 32 O
MASTER# (see below) I
SPKR /
Power-up Strap
128-129, 127-
126, 61, 71-75
30, 7, 16, 59
31, 33, 18, 60
134 B
Refresh.
an input REFRESH# is driven by 16-bit ISA Bus masters to indicate refresh cycle.
Address Enable.
misinterpreting DMA cycles as valid I/O cycles.
I
Interrupt Request.
ISA Bus I/O devices with a mechanism for asynchronously interrupting the CPU.
I
DMA Request.
VT82C586B’s DMA controller.
O
Acknowledge.
been granted.
Terminal Count.
indicator.
ISA Master Request.
Multifunction Pin
As an output REFRESH# indicates when a refresh cycle is in progress. As
AEN is asserted during DMA cycles to prevent I/O slaves from
The DRQ lines are used to request DMA services from the
The DACK# output lines indicate a request for DMA service has
Normal Operation:
Power-up Strapping:
VT82C586B
The IRQ signals provide both system board components and
The VT82C586B asserts TC to DMA slaves as a terminal count
(see below pin 137)
Speaker Drive.
0/1 = Fixed/flexible IDE I/O base
The SPKR signal is the output of counter 2.
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On Board Plug and Play
Signal Name Pin No. I/O Signal Description
MIRQ0 /
APICCS# /
POS (3040F)
MIRQ1 /
KEYLOCK /
IRQ8# (3040F)
MIRQ2 /
MASTER# /
SDDIR (3041A)
90 I
106 I
137 I
Multifunction Pin
O
O
O
MIRQ0.
APICCS#
implementations.
POS.
was introduced in rev F of the 3040 silicon and is not available in earlier chips.
Rx59[3] Rx59[0]
Multifunction Pin
I
MIRQ1.
I
KEYLOCK.
IRQ8#.
revision F of the 3040 silicon and is not available in earlier chips.
Rx48[4] Rx59[1]
Rx5A[2] Rx48[4]
Multifunction Pin
I
MIRQ2.
MASTER#.
control for the IDE interface DD / SA transceivers (see SOE#).
SDDIR.
interface DD / SA transceivers (see SOE#) separate from MASTER#. This
function was introduced in revision A of the 3041 silicon and not available in
earlier chips.
Rx48[5] Rx59[2]
Steerable interrupt request input for on-board devices.
. Chip select for external IOAPIC chip for symmetric multiprocessor
Power-On Suspend Status Output (see Function 0 Rx59 bit-3). This function
0 0 MIRQ0 (input)
0 1 APICCS# (output)
1 0 -illegal1 1 POS (output)
Steerable interrupt request input for on-board devices.
Keyboard lock input.
Interrupt input for external RTC. This function was introduced in
0 0 MIRQ1 (input)
0 1 KEYLOCK (input)
1 0 -illegal1 1 IRQ8# (input) (see also Rx5A[2] and table below). With
0 0 External RTC - IRQ8# input on pin 104
0 1 External RTC - IRQ8# input on pin 106
1 x Internal RTC - IRQ8# input not required
Steerable interrupt request input for on-board devices.
ISA Master Request indicator. This pin also serves as the direction
This pin may be programmed to serve as a direction control for the IDE
0 0 MASTER# (input)
0 1 MIRQ2 (input)
1 0 -illegal1 1 SDDIR (output)
VT82C586B
(see PCI Configuration Register Function 0 Rx59[3,0])
Pin Function
(see PCI Configuration Register Function 0 Rx59[1] & Rx48[4])
Pin Function
this setting, Rx57[3:0] must be set to 0 (MIRQ1 routing)
Pin Function
(see PCI Configuration Register Function 0 Rx59[2] & Rx48[5])
Pin Function
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UltraDMA-33 Enhanced IDE Interface
Signal Name Pin No. I/O Signal Description
DRDYA# /
DDMARDYA#
/ DSTROBEA
DRDYB# /
DDMARDYB#
/ DSTROBEB
DIORA# /
HDMARDYA#
/ HSTROBEA
DIORB# /
HDMARDYB#
/ HSTROBEB
DIOWA# /
STOPA
DIOWB# /
STOPB
SOE# 56 O
DDRQA 45 I
DDRQB 46 I
DDACKA# 47 O
DDACKB# 48 O
49 I
89 I
50 O
54 O
51 O
55 O
EIDE Mode:
UltraDMA Mode:
EIDE Mode:
UltraDMA Mode:
EIDE Mode:
UltraDMA Mode:
EIDE Mode:
UltraDMA Mode:
EIDE Mode:
UltraDMA Mode:
EIDE Mode:
UltraDMA Mode:
System Address Transceiver Output Enable.
enables of the 245 transceivers that interface the DD[15:0] signals to SA[15:0]. The
transceiver direction controls are driven by MASTER# with DD[15-0] connected to
the “A” side of the transceivers and SA[15-0] connected to the “B” side.
Device DMA Request A.
Device DMA Request B.
Device DMA Acknowledge A.
Device DMA Acknowledge B.
VT82C586B
I/O Channel Ready A.
Device DMA Ready A
The device may assert DDMARDY# to pause output transfers
Device Strobe A
The device may stop DSTROBE to pause input data transfers
I/O Channel Ready B.
Device DMA Ready B
The device may assert DDMARDY# to pause output transfers
Device Strobe B
The device may stop DSTROBE to pause input data transfers
Device I/O Read A.
Host DMA Ready A
The host may assert HDMARDY# to pause input transfers
Host Strobe A
The host may stop HSTROBE to pause output data transfers
Device I/O Read B.
Host DMA Ready B
The host may assert HDMARDY# to pause input transfers
Host Strobe B
The host may stop HSTROBE to pause output data transfers
Device I/O Write A.
. Primary channel stop transfer: asserted by the host prior
Stop A
to initiation of an UltraDMA burst; negated by the host before
data is transferred in an UltraDMA burst. Assertion of STOP by
the host during or after data transfer in UltraDMA mode signals
the termination of the burst.
Device I/O Write B.
. Secondary channel stop transfer: asserted by the host
Stop B
prior to initiation of an UltraDMA burst; negated by the host
before data is transferred in an UltraDMA burst. Assertion of
STOP by the host during or after data transfer in UltraDMA mode
signals the termination of the burst.
Primary channel DMA request
Secondary channel DMA request
. Primary channel output data strobe (both edges)
. Secondary channel output strobe (both edges)
Primary channel DMA acknowledge
Secondary channel DMA acknowledge
Primary channel device ready indicator
. Primary channel output flow control
. Primary channel input data strobe (both edges)
Secondary channel device ready
. Secondary channel output flow control
. Secondary channel input strobe (both edges)
Primary channel device read strobe
. Primary channel input flow control
Secondary channel device read strobe
. Secondary channel input flow control
Primary channel device write strobe
Secondary channel device write strobe
This signal controls the output
Note: Refer to the ISA bus interface pin descriptions for remaining IDE interface pin descriptions (the IDE address, data, and
drive select pins are multiplexed with the ISA bus LA and SA pins). Also, the MASTER# pin description may be found
in the "On Board Plug and Play" pin group (DD / SA transceiver direction control).
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XD Interface
Signal Name Pin No. I/O Signal Description
XD7-0,
EXTSMI7-3#,
GPI7-0,
GPO7-0,
Power-up Straps
XDIR 112 O
ROMCS# /
KBCS#
122
121
119
118
117
116
114
113
135 O
B
Multifunction Pins
X-bus Data Bus.
External SMI Inputs.
General Purpose Inputs.
General Purpose Outputs.
Power-up Strap Option Inputs.
XD0: 0/1 - Disable/enable internal KBC
XD1: 0/1 - Disable/enable internal PS/2 Mouse
XD2: 0/1 - Disable/enable internal RTC
XD4~XD7: RP13~RP16 for internal KBC
X-Bus Data Direction.
transceiver that buffers the X-Bus data and ISA-Bus data (the output enable of the
transceiver should be grounded). SD0-7 connect to the “A” side of the transceiver
and XD0-7 connect to the “B” side. XDIR high indicates that SD0-7 drives XD0-7.
Multifunction Pin. ROM Chip Select / Keyboard Controller Chip Select.
ISA memory cycle:
ISA I/O cycle:
VT82C586B
For connection to external X-Bus devices (e.g. BIOS ROM)
External SCI/SMI ports.
GPIO3_CFG bit low (pin 92 = GPI_RE#)
GPIO4_CFG bit low (pin 136 = GPO_WE)
(see Configuration Register Offset 5Ah)
XDIR is tied directly to the direction control of a 74F245
ROMCS#.
KBCS#.
Chip Select to the BIOS ROM.
Chip Select to the external keyboard controller.
General Purpose I/O
Signal Name Pin No. I/O Signal Description
GPIO0 /
EXTSMI0#
GPIO1 /
EXTSMI1# /
I2CD1 (Clock)
GPIO2 /
EXTSMI2# /
I2CD2 (Data)
GPIO3 /
EXTSMI3# /
GPI_RE#
GPIO4 /
EXTSMI4# /
GPO_WE
94 B
87 B
88 B
92 B
136 B
General Purpose I/O 0
This pin sits on the VDD-5VSB power plane and is available even under soft-off
state.
General Purpose I/O 1
Can be used along with pin 88 as an I
defined as clock).
General Purpose I/O 2
Can be used along with pin 87 as an I
defined as data).
Multifunction Pin
GPIO3 Configuration bit high:
external SCI/SMI capability.
GPIO3 Configuration bit low:
Connects to the output enable (OE# pin) of the external 244 buffers whose data pins
connect to SD15-8 and XD7-0 for GPI15-0.
Multifunction Pin
GPIO4 Configuration bit high:
external SCI/SMI capability.
GPIO4 Configuration bit low:
Connects to the latch enable (LE pin) of the external 373 latches whose data pins
connect to SD15-8 and XD7-0 for GPO15-0.
: General Purpose I/O with external SCI/SMI capability.
: General Purpose I/O with external SCI/SMI capability.
: General Purpose I/O with external SCI/SMI capability.
(per GPIO3 Configuration Bit: Function 3 Rx40 bit-6)
(per GPIO4 Configuration Bit: Function 3 Rx40 bit-7)
2
C pair (by software convention this pin is
2
C pair (by software convention this pin is
General Purpose I/O 3
Read Enable for General Purpose Inputs
General Purpose I/O 4
Write Enable for General Purpose Outputs
: General Purpose I/O with
: General Purpose I/O with
:
:
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Universal Serial Bus Interface
Signal Name Pin No. I/O Signal Description
USBDATA0+ 95 B
USBDATA0- 96 B
USBDATA1+ 97 B
USBDATA1- 98 B
USBCLK 99 I
USB Port 0 Data +
USB Port 0 Data USB Port 1 Data +
USB Port 1 Data USB Clock.
Clock input for Universal Serial Bus interface
Keyboard Interface
Signal Name Pin No. I/O Signal Description
KBCK /
KA20G
KBDT /
KBRC#
MSCK / IRQ1 110 B
MSDT / IRQ12 111 B
A20M 147 O
KEYLOCK /
MIRQ1 /
IRQ8#
108 B
109 B
106 I
Multifunction Pin.
Internal KBC enabled:
Internal KBC disabled:
Multifunction Pin.
Internal KBC enabled:
Internal KBC disabled:
Multifunction Pin.
PS/2 mouse enabled:
PS/2 mouse disabled and internal KBC disabled:
IRQ 1 input from external KBC.
Multifunction Pin.
PS/2 mouse enabled:
PS/2 mouse disabled:
A20 Mask.
Keyboard Lock.
(For reference only - see pin 106 description in "Onboard Plug and Play" section)
Direct connect A20 mask on CPU.
Keyboard lock signal for internal keyboard controller.
VT82C586B
Function depends on enable/disable of internal KBC.
Keyboard Clock.
Gate A20:
Function depends on enable/disable of internal KBC.
Keyboard Data.
Keyboard Reset:
Function depends on enable/disable of internal KBC.
Mouse Clock.
Function depends on enable/disable of internal KBC.
Mouse Data.
Interrupt Request 12.
Clock to keyboard interface.
Gate A20 output from external KBC
Data to keyboard interface.
Reset input from external KBC.
Clock to PS/2 mouse interface.
Interrupt Request 1.
Data to PS/2 mouse interface.
IRQ 12 input from external KBC
Internal Real Time Clock
Signal Name Pin No. I/O Signal Description
RTCX1 /
IRQ8#
RTCX2 /
RTCCS#
VBAT 102 I
Revision 1.0 May 13, 1997 -12- Pinouts
104 I
105 O
Multifunction Pin
Internal RTC enabled:
Internal RTC disabled:
Rx5A[2] Rx48[4]
0 0 External RTC - IRQ8# input on pin 104
0 1 External RTC - IRQ8# input on pin 106
1 x Internal RTC - IRQ8# input not required
Multifunction Pin
Internal RTC enabled:
Internal RTC disabled:
RTC Battery.
Battery input for internal RTC
RTC Crystal Input
Interrupt Request 8
Pin Function
RTC Crystal Output
External RTC Chip Select
: 32.768Khz crystal or oscillator input.
: IRQ8 input from external RTC
: 32.768Khz crystal output
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Resets and Clocks
Signal Name Pin No. I/O Signal Description
PWRGD 138 I
PCIRST# 3 O
RSTDRV 4 O
BCLK 14 O
OSC 6 I
Power Good.
PCI Reset.
generate PCIRST# during power-up or from the control register.
Reset Drive.
Bus Clock.
Oscillator.
Connected to the POWERGOOD signal on the Power Supply.
An active low reset signal for the PCI bus. The VT82C586B will
RSTDRV is the reset signal to the ISA bus.
ISA bus clock.
OSC is the 14.31818 MHz clock signal. It is used by the internal Timer.
Power Management
Signal Name Pin No. I/O Signal Description
PWRBTN# 91 I
PWRON 107 O
RI# 93 I
Power Button.
Power Supply Control.
Ring Indicator.
to be re-activated by a received phone call. Input referenced to VDD-5VSB.
Referenced to VDD-5VSB.
May be connected to external modem circuitry to allow the system
Power and Ground
VT82C586B
Powered by VDD-5VSB.
Signal Name Pin No. I/O Signal Description
VDD5 17, 34, 53, 79,
115
VDD-5VSB 103 P
VDD3 144 P
VDD_PCI 157, 171, 184,
198
AVDD 100 P
AGND 101 P
GND 13, 26, 39, 52,
68, 84, 120,
140, 156, 166,
177, 188, 197,
208
P
Power Supply.
switch on the power supply is turned on and the PWRON signal is conditioned high.
Power Supply.
is turned off. If the "soft-off" state is not implemented, then this pin can be
connected to VDD5.
Power Supply.
circuitry.
P
PCI Voltage.
USB Differential Output Power Source
USB Differential Output Ground
P
Ground
4.75 to 5.25V. This supply is turned on only when the mechanical
Always available unless the mechanical switch of the power supply
This pin should be connected to the same voltage as the CPU I/O
3.3 or 5V.
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VT82C586B
R
EGISTERS
Register Overview
The following tables summarize the configuration and I/O
registers of the VT82C586B. These tables also document the
power-on default value (“Default”) and access type (“Acc”) for
each register. Access type definitions used are RW
(Read/Write), RO (Read/Only), “—” for reserved / used
(essentially the same as RO), and RWC (or just WC) (Read /
Write 1’s to Clear individual bits). Registers indicated as RW
may have some read/only bits that always read back a fixed
value (usually 0 if unused); registers designated as RWC or
WC may have some read-only or read write bits (see individual
register descriptions for details).
Detailed register descriptions are provided in the following
section of this document. All offset and default values are
shown in hexadecimal unless otherwise indicated
Table 2. System I/O Map
Port Function Actual Port Decoding
00-1F Master DMA Controller 0000 0000 000x nnnn
20-3F Master Interrupt Controller 0000 0000 001x xxxn
40-5F Timer / Counter 0000 0000 010x xxnn
60-6F Keyboard Controller 0000 0000 0110 xnxn
(60h) KBC Data 0000 0000 0110 x0x0
(61h) Misc Functions & Spkr Ctrl 0000 0000 0110 xxx1
(64h) KBC Command / Status 0000 0000 0110 x1x0
70-77 RTC/CMOS/NMI-Disable 0000 0000 0111 0nnn
78-7F -available for system use- 0000 0000 0111 1xxx
80 -reserved- (debug port) 0000 0000 1000 0000
81-8F DMA Page Registers 0000 0000 1000 nnnn
90-91 -available for system use- 0000 0000 1001 000x
92 System Control 0000 0000 1001 0010
93-9F -available for system use- 0000 0000 1001 nnnn
A0-BF Slave Interrupt Controller 0000 0000 101x xxxn
C0-DF Slave DMA Controller 0000 0000 110n nnnx
E0-FF -available for system use- 0000 0000 111x xxxx
100-CF7 -available for system useCF8-CFB PCI Configuration Address 0000 1100 1111 10xx
CFC-CFF PCI Configuration Data 0000 1100 1111 11xx
D00-FFFF -available for system use-
Table 3. Registers
Legacy I/O Registers
Port Master DMA Controller Registers Default Acc
00 Channel 0 Base & Current Address RW
01 Channel 0 Base & Current Count RW
02 Channel 1 Base & Current Address RW
03 Channel 1 Base & Current Count RW
04 Channel 2 Base & Current Address RW
05 Channel 2 Base & Current Count RW
06 Channel 3 Base & Current Address RW
07 Channel 3 Base & Current Count RW
08 Status / Command RW
09 Write Request
0A Write Single Mask
0B Write Mode
0C Clear Byte Pointer FF
0D Master Clear
0E Clear Mask
0F Read / Write Mask RW
Port Master Interrupt Controller Regs Default Acc
20 Master Interrupt Control — *
21 Master Interrupt Mask — *
20 Master Interrupt Control Shadow —
21 Master Interrupt Mask Shadow —
* RW if shadow registers are disabled
Timer/Counter Registers Default Acc
Port
40 Timer / Counter 0 Count RW
41 Timer / Counter 1 Count RW
42 Timer / Counter 2 Count RW
43 Timer / Counter Control
Port Keyboard Controller Registers Default Acc
60 Keyboard Controller Data RW
61 Misc Functions & Speaker Control RW
64 Keyboard Ctrlr Command / Status RW
Port CMOS / RTC / NMI Registers Default Acc
70 CMOS Memory Address & NMI Disa
71 CMOS Memory Data (128 bytes) RW
72 CMOS Memory Address RW
73 CMOS Memory Data (256 bytes) RW
74 CMOS Memory Address RW
75 CMOS Memory Data (256 bytes) RW
NMI Disable is port 70h (CMOS Memory Address) bit-7.
RTC control occurs via specific CMOS data locations (0-0Dh).
Ports 72-73 may be used to access all 256 locations of CMOS.
Ports 74-75 may be used to access CMOS if the internal RTC is
disabled.
WO
WO
WO
WO
WO
WO
RW
RW
WO
WO
Revision 1.0 May 13, 1997 -14- Register Overview
9,$7HFKQRORJLHV,QF
VT82C586B
Port DMA Page Registers Default Acc
87 DMA Page - DMA Channel 0 RW
83 DMA Page - DMA Channel 1 RW
81 DMA Page - DMA Channel 2 RW
82 DMA Page - DMA Channel 3 RW
8F DMA Page - DMA Channel 4 RW
8B DMA Page - DMA Channel 5 RW
89 DMA Page - DMA Channel 6 RW
8A DMA Page - DMA Channel 7 RW
Port System Control Registers Default Acc
92 System Control RW
Port Slave Interrupt Controller Regs Default Acc
A0 Slave Interrupt Control — *
A1 Slave Interrupt Mask — *
A0 Slave Interrupt Control Shadow —
A1 Slave Interrupt Mask Shadow —
* RW accessible if shadow registers are disabled
RW
RW
Slave DMA Controller Registers Default Acc
Port
C0 Channel 0 Base & Current Address RW
C2 Channel 0 Base & Current Count RW
C4 Channel 1 Base & Current Address RW
C6 Channel 1 Base & Current Count RW
C8 Channel 2 Base & Current Address RW
CA Channel 2 Base & Current Count RW
CC Channel 3 Base & Current Address RW
CE Channel 3 Base & Current Count RW
D0 Status / Command RW
D2 Write Request
D4 Write Single Mask
D6 Write Mode
D8 Clear Byte Pointer FF
DA Master Clear
DC Clear Mask
DE Read / Write Mask RW
WO
WO
WO
WO
WO
WO
Revision 1.0 May 13, 1997 -15- Register Overview
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