Via VT8235M User Manual

Data Sheet

VT8235M Version CD

South Bridge

Revision 2.03 March 16, 2005

VIA TECHNOLOGIES, INC.

Copyright © 2002-2005 VIA Technologies Incorporated. All Rights Reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system or translated into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise without the prior written permission of VIA Technologies Incorporated. The material in this document is for information only and is subject to change without notice. VIA Technologies Incorporated reserves the right to make changes in the product design without reservation and without notice to its users.

Trademark Notices:

VT8235M may only be used to identify products of VIA Technologies.

is a registered trademark of VIA Technologies.

AMD-K7™ and Athlon™ are registered trademarks of Advanced Micro Devices. Celeron™, Pentium™, Pentium II™, Pentium III™, Pentium 4™, MMX™ and Intel™ are registered trademarks of Intel Corporation. Windows XP™, Windows 2000™, Windows ME™, Windows 98™ and Plug and Play™ are registered trademarks of Microsoft Corporation. PCI™ is a registered trademark of the PCI Special Interest Group. PS/2™ is a registered trademark of International Business Machines Corporation. All trademarks are the properties of their respective owners.

Disclaimer Notice:

No license is granted, implied or otherwise, under any patent or patent rights of VIA Technologies. VIA Technologies makes no warranties, implied or otherwise, in regard to this document and to the products described in this document. The information provided by this document is believed to be accurate and reliable as of the publication date of this document. However, VIA Technologies assumes no responsibility for any errors in this document. Furthermore, VIA Technologies assumes no responsibility for the use or misuse of the information in this document and for any patent infringements that may arise from the use of this document. The information and product specifications within this document are subject to change at any time, without notice and without obligation to notify any person of such change.

Offices:

USA Office: Taipei Office:

940 Mission Court 1 Fremont, CA 94539 Chung-Cheng Road, Hsin-Tien USA Taipei, Taiwan ROC Tel: (510) 683-3300 Tel: (886-2) 2218-5452 Fax: (510) 683-3301 or (510) 687-4654 Fax: (886-2) 2218-5453 Web: http://www.viatech.com

Web: http://www.via.com.tw

Floor, No. 531

VT8235M Version CD V-Link South Bridge

REVISION HISTORY

Document Release Date Revision Initials

1.21 9/27/02 Fixed pin names of PCREQA/B and PCGNTA/B in pin descriptions DH

1.22 10/24/02 Fixed register references in MSCK and MSDT pin descriptions Fixed VLVREF voltage for V-Link 8x mode Removed references to nonexistent ports 72-73

1.3 11/20/02 Updated LAN I/O Rx23-20[10], 27-24[15-11], 6F[2-0], 70[6-0], 74[4-0], 83, 84, 86 DH

1.31 12/11/02 Fixed IORDY signal name polarity in pin diagram; fixed minor typos in pin lists Added strap description in VAD7 pin description; Fixed Func 0 Rx7C[3-0], 98[7,3] Fixed VIA logo in page heading starting on page 6

1.4 12/17/02 Fixed first two feature bullets to indicate current north bridge products Improved DPSLP# pin description; Fixed GPO22-23, 28-29 pin descriptions Fixed note in VCC pin description; Improved bit description for D17 F0 RxE5[3]

1.41 1/3/03 Updated Port 61 (bits 7-6 and 3-2) and Port 92 (bits 7-6 and 3) Device 16 Function 0-3 USB – added Rx83-80; renamed F3 Rx48-49 Device 17 Function 1 IDE – fixed Rx4E register name; removed RxFD Fixed Rx3C[3-0] of Device 17 Function 1, 5, 6 and Device 18 Function 0 Fixed Rx2C-2F of Device 17 Function 5-6 and RxB of Function 6

1.42 1/3/03 Fixed Device Ids in table 5 function summary for USB 2.0 and LAN DH

1.43 2/5/03 Changed Device 17 Function 0 Rx50[0] to reserved DH

1.44 2/5/03 Updated feature bullets to indicated compatibility with ACPI 2.0 DH

1.5 2/25/03 Updated figure 1 block diagram; Updated defaults in GPI pin description table Added strap on SDCS1# in ballout & pin lists and added to strap pin description table Updated Device 16 Function 0-3 Rx83 default; Removed PMIO Rx5C[1] Device 17 Function 0 – fixed Rx50[1] bit name, 95[2] bit description

1.51 3/3/03 Fixed EEDI and EEDO pin directions; added register cross references to GPIOC-E DH

1.52 3/18/03 Updated GPI/GPO pin default states Fixed PMIO Rx30[1] cross-reference to Device 17 Function 0 Rx84

1.6 4/15/03 Fixed IDE Rx3D default, fixed D17 F0 Rx8C[7-4],8D[4]; updated PMIO Rx10[3-0] Fixed incorrect JEDEC-spec reference in mechanical specification diagram

1.7 4/29/03 Added “Version CD” to product name to differentiate from “Version CE” Fixed VT8233A Version CE / VT8235ML South Bridge part # references

1.71 6/9/03 Updated Dev 17 Func 0 Rx59[3-2], PMIO RxB-8[31-24], Dev 17 Func 1 Rx4C DH

1.72 6/30/03 Changed pins W22 and AD17 to NC DH

1.73 9/17/03 Removed power requirements table; Updated PMIO Rx5-4[12:10] AL

1.74 3/3/04 Moved straps to separate table; Updated IO Trap registers Rx5C[0] Updated Dev18 Func 0 Rx06[7:5], 07[7:3], 08[0], 09[0], 0C[4], 0D[1:0], 23-20[7], 4340[11], 6E[5:3], 6F[5:3]

1.75 4/20/04 Updated top marking on Mechanical Specification section; Fixed Pin AD7, AE7 IO Prosperity

1.76 5/10/04 Updated Device18 Function 0 Rx7B VL

1.77 7/9/04 Added lead-free package diagram to mechanical specification section VL

1.78 8/11/04 Updated lead-free diagram in mechanical specification VL

1.79 8/26/04 Updated APIC Fixed IRQ Routing Table in register descriptions Fixed incorrect reference in Device17 Function 0 Rx81

2.0 9/3/04 Changed part to VT8235M Version CD VL

2.01 11/4/04 Updated Rx48 and Rx49 in Device 17 Function 5 and 6 Updated bit definition for D17F0 Rx80[5]; Added D17F0 RxEC-EF

2.02 11/23/04 Updated top marking on mechanical specification VL

2.03 3/16/05 Added USBREXT signal description and updated copyright notice DA

Revision 2.03, March 16, 2005 -iii- Revision History

VT8235M Version CD V-Link South Bridge

TABLE OF CONTENTS

REVISION HISTORY ....................................................................................................................................................................III

TABLE OF CONTENTS.................................................................................................................................................................IV

LIST OF FIGURES ....................................................................................................................................................................... VII

LIST OF TABLES ......................................................................................................................................................................... VII

PRODUCT FEATURES.................................................................................................................................................................... 1

OVERVIEW....................................................................................................................................................................................... 4

PINOUTS............................................................................................................................................................................................ 6

PIN DESCRIPTIONS........................................................................................................................................................................ 9

V-LINK PIN DESCRIPTIONS ........................................................................................................................................................... 9

CPU, APIC AND CPU CONTROL PIN DESCRIPTIONS ............................................................................................................... 10

MII, SERIAL EEPROM, LPC AND DMA PIN DESCRIPTIONS .................................................................................................. 12

USB, SMB AND PROGRAMMABLE CHIP SELECT PIN DESCRIPTIONS ....................................................................................... 13

EIDE INTERFACE PIN DESCRIPTIONS ........................................................................................................................................ 14

SERIAL IRQ AND AC97 PIN DESCRIPTIONS............................................................................................................................... 15

INTERNAL KEYBOARD CONTROLLER AND SPEAKER PIN DESCRIPTIONS ................................................................................. 16

GENERAL PURPOSE INPUT PIN DESCRIPTIONS .......................................................................................................................... 17

GENERAL PURPOSE OUTPUT AND GPIO PIN DESCRIPTIONS .................................................................................................... 18

POWER MANAGEMENT AND EVENT DETECTION PIN DESCRIPTIONS ....................................................................................... 19

CLOCK, RESETS, POWER STATUS, POWER AND GROUND PIN DESCRIPTIONS ......................................................................... 20

STRAP PIN DESCRIPTIONS ........................................................................................................................................................... 21

REGISTERS..................................................................................................................................................................................... 22

REGISTER OVERVIEW ................................................................................................................................................................. 22

REGISTER DESCRIPTIONS ........................................................................................................................................................... 37

Legacy I/O Ports................................................................................................................................................................... 37

Keyboard Controller I/O Registers........................................................................................................................................................ 38

DMA Controller I/O Registers .............................................................................................................................................................. 40

Interrupt Controller I/O Registers.......................................................................................................................................................... 41

Timer / Counter Registers......................................................................................................................................................................41

CMOS / RTC I/O Registers................................................................................................................................................................... 42

Keyboard / Mouse Wakeup Index / Data Registers........................................................................................................... 43

Keyboard / Mouse Wakeup Registers................................................................................................................................. 43

Memory Mapped I/O APIC Registers ................................................................................................................................ 44

Indexed I/O APIC Registers ................................................................................................................................................ 44

Configuration Space I/O ...................................................................................................................................................... 46

Device 16 Function 0 Registers - USB 1.1 UHCI Ports 0-1 ............................................................................................... 47

PCI Configuration Space Header...........................................................................................................................................................47

USB-Specific Configuration Registers.................................................................................................................................................. 48

USB I/O Registers................................................................................................................................................................................. 50

Device 16 Function 1 Registers - USB 1.1 UHCI Ports 2-3 ............................................................................................... 51

PCI Configuration Space Header...........................................................................................................................................................51

USB-Specific Configuration Registers.................................................................................................................................................. 52

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USB I/O Registers................................................................................................................................................................................. 54

Device 16 Function 2 Registers - USB 1.1 UHCI Ports 4-5 ............................................................................................... 55

PCI Configuration Space Header...........................................................................................................................................................55

USB-Specific Configuration Registers.................................................................................................................................................. 56

USB I/O Registers................................................................................................................................................................................. 58

Device 16 Function 3 Registers - USB 2.0 EHCI................................................................................................................ 59

PCI Configuration Space Header...........................................................................................................................................................59

USB-Specific Configuration Registers.................................................................................................................................................. 60

EHCI USB 2.0 I/O Registers................................................................................................................................................................. 61

Device 17 Function 0 Registers – Bus Control and Power Management......................................................................... 62

PCI Configuration Space Header...........................................................................................................................................................62

ISA Bus Control .................................................................................................................................................................................... 63

Miscellaneous Control........................................................................................................................................................................... 65

Function Control.................................................................................................................................................................................... 66

Serial IRQ, LPC, and PC/PCI DMA Control ........................................................................................................................................ 67

Plug and Play Control - PCI .................................................................................................................................................................. 67

GPIO and Miscellaneous Control.......................................................................................................................................................... 68

Programmable Chip Select Control....................................................................................................................................................... 70

ISA Decoding Control........................................................................................................................................................................... 71

Power Management-Specific Configuration Registers.......................................................................................................................... 73

System Management Bus-Specific Configuration Registers ................................................................................................................. 80

SMB GPIO Slave Command Codes...................................................................................................................................................... 80

General Purpose I/O Control Registers ................................................................................................................................................. 81

Watchdog Timer Registers .................................................................................................................................................................... 82

Power Management I/O-Space Registers .............................................................................................................................................. 83

System Management Bus I/O-Space Registers...................................................................................................................................... 92

Device 17 Function 1 Registers - Enhanced IDE Controller............................................................................................. 95

PCI Configuration Space Header...........................................................................................................................................................95

IDE-Controller-Specific Configuration Registers ................................................................................................................................. 97

IDE Power Management Registers...................................................................................................................................................... 101

IDE Back Door Registers .................................................................................................................................................................... 101

IDE I/O Registers................................................................................................................................................................................ 101

Device 17 Function 5 Registers - AC97 Audio Controller............................................................................................... 102

PCI Configuration Space Header.........................................................................................................................................................102

Audio-Specific PCI Configuration Registers....................................................................................................................................... 103

I/O Base 0 Regs – Audio Scatter / Gather DMA ................................................................................................................................. 105

Device 17 Function 6 Registers - AC97 Modem Controller............................................................................................ 114

PCI Configuration Space Header.........................................................................................................................................................114

Modem-Specific PCI Configuration Registers.................................................................................................................................... 115

I/O Base 0 Regs – Modem Scatter / Gather DMA............................................................................................................................... 117

Device 18 Function 0 Registers - LAN .............................................................................................................................. 120

PCI Configuration Space Header.........................................................................................................................................................120

LAN-Specific PCI Configuration Registers ........................................................................................................................................ 120

LAN I/O Registers............................................................................................................................................................................... 122

FUNCTIONAL DESCRIPTIONS................................................................................................................................................ 133

POWER MANAGEMENT.............................................................................................................................................................. 133

Power Management Subsystem Overview .......................................................................................................................................... 133

Processor Bus States............................................................................................................................................................................ 133

System Suspend States and Power Plane Control................................................................................................................................ 134

General Purpose I/O Ports................................................................................................................................................................... 134

Power Management Events ................................................................................................................................................................. 135

System and Processor Resume Events................................................................................................................................................. 135

Legacy Power Management Timers .................................................................................................................................................... 136

System Primary and Secondary Events ............................................................................................................................................... 136

Peripheral Events................................................................................................................................................................................. 136

ELECTRICAL SPECIFICATIONS ............................................................................................................................................ 137

ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................... 137

DC CHARACTERISTICS.............................................................................................................................................................. 137

REGISTER BITS POWERED BY VBAT ....................................................................................................................................... 138

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VT8235M Version CD V-Link South Bridge

REGISTER BITS POWERED BY VSUS25 .................................................................................................................................... 138

PACKAGE MECHANICAL SPECIFICATIONS...................................................................................................................... 139

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VT8235M Version CD V-Link South Bridge

LIST OF FIGURES

FIGURE 1. PC SYSTEM CONFIGURATION USING THE VT8235M VERSION CD........................................................... 5

FIGURE 2. BALL DIAGRAM (TOP VIEW)................................................................................................................................. 6

FIGURE 3. POWER MANAGEMENT SUBSYSTEM BLOCK DIAGRAM......................................................................... 133

FIGURE 4. SYSTEM BLOCK DIAGRAM USING THE P4X400 NORTH BRIDGE .......................................................... 135

FIGURE 5. MECHANICAL SPECIFICATIONS – 487 PIN BALL GRID ARRAY PACKAGE ........................................ 139

FIGURE 6. LEAD-FREE MECHANICAL SPECIFICATIONS – 487 PIN BALL GRID ARRAY PACKAGE ................ 140

LIST OF TABLES

TABLE 1. PIN LIST (NUMERICAL ORDER) ............................................................................................................................. 7

TABLE 2. PIN LIST (ALPHABETICAL ORDER) ...................................................................................................................... 8

TABLE 3. MEMORY MAPPED REGISTERS ........................................................................................................................... 22

TABLE 4. FUNCTION SUMMARY............................................................................................................................................. 22

TABLE 5. SYSTEM I/O MAP....................................................................................................................................................... 22

TABLE 6. REGISTERS ................................................................................................................................................................. 23

TABLE 7. KEYBOARD CONTROLLER COMMAND CODES .............................................................................................. 39

TABLE 8. CMOS REGISTER SUMMARY ................................................................................................................................ 42

TABLE 9. APIC FIXED IRQ ROUTING .................................................................................................................................... 65

TABLE 10. PNP IRQ ROUTING TABLE ................................................................................................................................... 67

Revision 2.03, March 16, 2005 -vii- Table of Content

VT8235M Version CD V-Link South Bridge

VT8235M VERSION CD

LOW COST V-LINK CLIENT

IGHLY INTEGRATED SOUTH BRIDGE

HIGH BANDWIDTH V-LINK CLIENT CONTROLLER

NTEGRATED FAST ETHERNET,

NTEGRATED DIRECT SOUND AC97 AUDIO,

LTRADMA-133/100/66/33 MASTER MODE EIDE CONTROLLER,

IX PORT USB 2.0 CONTROLLER, KEYBOARD / MOUSE CONTROLLER,

RTC, LPC, SMB

US, SERIAL IRQ, PLUG AND PLAY, ACPI,

AND PC2001 COMPLIANT ENHANCED POWER MANAGEMENT

PRODUCT FEATURES

• Inter-operable with VIA Host-to-V-Link Host Controller

− Combine with KT400A North Bridge for a complete Athlon system

− Combine with CLE266 North Bridge for a complete VIA C3 / Pentium 3 system

− Combine with P4X400 North Bridge for a complete Pentium 4 system

• High Bandwidth 533 MB/s 8-bit V-Link Client Controller

− Supports 66 MHz V-Link Client interface with total bandwidth of 533 MB/sec

− V-Link operates in 2x, 4x, and 8x modes

− Full duplex commands with separate Strobe / Command

− Request / Data split transaction

− Configurable outstanding transaction queue for V-Link Client accesses

− Auto Client Retry to eliminate V-Link Host-Client Retry cycles

− Intelligent V-Link transaction protocol to eliminate data wait-state / throttle transfer latency; all V-Link transactions

for both Host and Client have a consistent view of transaction data depth and buffer size to avoid data overflow.

− Highly efficient V-Link arbitration with minimum overhead; all V-Link transactions have predictable cycle length

with known Command / Data duration

− Auto connect / reconnect capability and dynamic stop for minimum power consumption

− Parity checking to insure correct data transfers

• Integrated Peripheral Controllers

−

Integrated Fast Ethernet Controller with 1 / 10 / 100 Mbit capability

− Integrated USB 2.0 Controller with three root hubs and six function ports

− Dual channel UltraDMA-133 / 100 / 66 / 33 master mode EIDE controller

− AC-link interface for AC-97 audio codec and modem codec

− HSP modem support

− Integrated DirectSound compatible digital audio controller

− LPC interface for Low Pin Count interface to Super-I/O or ROM

• Integrated Legacy Functions

− Integrated Keyboard Controller with PS2 mouse support

− Integrated DS12885-style Real Time Clock with extended 256 byte CMOS RAM and Day/Month Alarm for ACPI

− Integrated DMA, timer, and interrupt controller

− Serial IRQ for docking and non-docking applications

− Fast reset and Gate A20 operation

Revision 2.03, March 16, 2005 -1- Product Feature

VT8235M Version CD V-Link South Bridge

• Concurrent PCI Bus Controller

− 33 MHz operation

− Supports up to six PCI masters

− Peer concurrency

− Concurrent multiple PCI master transactions; i.e., allow PCI masters from both PCI buses active at the same time

− Zero wait state PCI master and slave burst transfer rate

− PCI to system memory data streaming up to 132Mbyte/sec (data sent to north bridge via high speed V-Link

Interface)

− PCI master snoop ahead and snoop filtering

− Eight DW of CPU to PCI posted write buffers

− Byte merging in the write buffers to reduce the number of PCI cycles and to create further PCI bursting possibilities

− Enhanced PCI command optimization (MRL, MRM, MWI, etc.)

− Four lines of post write buffers from PCI masters to DRAM

− Sixteen levels (double-words) of prefetch buffers from DRAM for access by PCI masters

− Delay transaction from PCI master accessing DRAM

− Transaction timer for fair arbitration between PCI masters (granularity of two PCI clocks)

− Symmetric arbitration between Host/PCI bus for optimized system performance

− Complete steerable PCI interrupts

− PCI-2.2 compliant, 32 bit 3.3V PCI interface with 5V tolerant inputs

• Fast Ethernet Controller

− High performance PCI master interface with scatter / gather and bursting capability

− Standard MII interface to external PHYceiver

− 1 / 10 / 100 MHz full and half duplex operation

− Independent 2K byte FIFOs for receive and transmit

− Flexible dynamically loadable EEPROM algorithm

− Physical, Broadcast, and Multicast address filtering using hashing function

− Magic packet and wake-on-address filtering

− Software controllable power down

• UltraDMA-133 / 100 / 66 / 33 Master Mode EIDE Controller

− Dual channel master mode hard disk controller supporting four Enhanced IDE devices

− Transfer rate up to 133MB/sec to cover PIO mode 4, multi-word DMA mode 2 drives, and UltraDMA-133 interface

− Increased reliability using UltraDMA-133/100/66 transfer protocols

− Thirty-two levels (doublewords) of prefetch and write buffers

− Dual DMA engine for concurrent dual channel operation

− Bus master programming interface for SFF-8038i rev.1.0 and Windows-95 compliant

− Full scatter gather capability

− Support ATAPI compliant devices including DVD devices

− Support PCI native and ATA compatibility modes

− Complete software driver support

• Direct Sound Ready AC97 Digital Audio Controller

− AC-Link access to 4 CODECs (AC97 + AMC97 + MC97)

− Multichannel Audio

− Bus Master Scatter / Gather DMA

− Dedicated read and write channels supporting simultaneous stereo playback and record

− Dedicated read and write channels supporting simultaneous modem receive and transmit

− 1 stereo DirectSound channel with source / volume control / mixer

− 1 shared FM / SPDIF PCM read channel

− 1 dedicated channel supporting multi-channel audio

− 32-byte line-bufers for each SGD channel

− Programmable 8bit / 16bit mono / stereo PCM data format support

− AC97 2.1 compliant

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VT8235M Version CD V-Link South Bridge

• System Management Bus Interface

− Host interface for processor communications

− Slave interface for external SMBus masters

• Universal Serial Bus Controller

USB v2.0 and Enhanced Host Controller Interface (EHCI) v1.0 compatible

−

− USB v1.1 and Universal Host Controller Interface (UHCI) v1.1 compatible

− Eighteen level (doublewords) data FIFO with full scatter and gather capability

− Three root hubs and six function ports

− Integrated physical layer transceivers with optional over-current detection status on USB inputs

− Legacy keyboard and PS/2 mouse support

• Sophisticated PC2001-Compatible Mobile Power Management

− Supports both ACPI (Advanced Configuration and Power Interface) and legacy (APM) power management

− ACPI v2.0 Compliant

− APM v1.2 Compliant

− CPU clock throttling and clock stop control for complete ACPI C0 to C3 state support

− PCI bus clock run, Power Management Enable (PME) control, and PCI/CPU clock generator stop control

− Supports multiple system suspend types: power-on suspends with flexible CPU/PCI bus reset options,

suspend to DRAM, and suspend to disk (soft-off), all with hardware automatic wake-up

− Multiple suspend power plane controls and suspend status indicators

− One idle timer, one peripheral timer and one general purpose timer, plus 24/32-bit ACPI compliant timer

− Normal, doze, sleep, suspend and conserve modes

− Global and local device power control

− System event monitoring with two event classes

− Primary and secondary interrupt differentiation for individual channels

− Dedicated input pins for power and sleep buttons, external modem ring indicator, and notebook lid open/close for

system wake-up

− 32 general purpose input ports and 32 output ports

− Multiple internal and external SMI sources for flexible power management models

− Enhanced integrated real time clock (RTC) with date alarm, month alarm, and century field

− Thermal alarm on external temperature sensing circuit

− I/O pad leakage control

• Plug and Play Controller

− PCI interrupts steerable to any interrupt channel

− Steerable interrupts for integrated peripheral controllers: USB, floppy, serial, parallel, and audio

− Microsoft Windows XP

, Windows NTTM, Windows 2000TM, Windows 98

and plug and play BIOS compliant

• Built-in NAND-tree pin scan test capability

• 0.22um, 2.5V, low power CMOS process

• Single chip 27 x 27 mm, 1.0 mm ball pitch, 487 pin BGA

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VT8235M Version CD V-Link South Bridge

OVERVIEW

The VT8235M Version CD South Bridge is a high integration, high performance, power-efficient, and high compatibility device that supports Intel and non-Intel based processor to V-Link bus bridge functionality to make a complete Microsoft PC2001compliant PCI/LPC system. The VT8235M Version CD includes standard intelligent peripheral controllers:

a) IEEE 802.3 compliant 10 / 100 Mbps PCI bus master Ethernet MAC with standard MII interface to external PHYceiver.

b) Master mode enhanced IDE controller with dual channel DMA engine and interlaced dual channel commands. Dedicated

FIFO coupled with scatter and gather master mode operation allows high performance transfers between PCI and IDE devices. In addition to standard PIO and DMA mode operation, the VT8235M Version CD also supports the UltraDMA133, 100, 66, and 33 standards to allow reliable data transfer at rates up to 133 MB/sec. The IDE controller is SFF-8038i v1.0 and Microsoft Windows-family compliant.

c) Universal Serial Bus controller that is USB v2.0 / 1.1 and Universal HCI v2.0 / 1.1 compliant. The VT8235M Version CD

includes three root hubs with six function ports with integrated physical layer transceivers. The USB controller allows hot plug and play and isochronous peripherals to be inserted into the system with universal driver support. The controller also implements legacy keyboard and mouse support so that legacy software can run transparently in a non-USB-aware operating system environment.

d) Keyboard controller with PS2 mouse support.

e) Real Time Clock with 256 byte extended CMOS. In addition to the standard ISA RTC functionality, the integrated RTC also

includes the date alarm, century field, and other enhancements for compatibility with the ACPI standard.

f) Notebook-class power management functionality compliant with ACPI and legacy APM requirements. Multiple sleep states

(power-on suspend, suspend-to-DRAM, and suspend-to-Disk) are supported with hardware automatic wake-up. Additional functionality includes event monitoring, CPU clock throttling and stop (Intel processor protocol), PCI bus clock stop control, modular power, clock and leakage control, hardware-based and software-based event handling, general purpose I/O, chip select and external SMI.

g) Full System Management Bus (SMBus) interface.

h) Integrated bus-mastering dual full-duplex direct-sound AC97-link-compatible sound system.

i) Plug and Play controller that allows complete steerability of all PCI interrupts and internal interrupts / DMA channels to any

interrupt channel. One additional steerable interrupt channel is provided to allow plug and play and reconfigurability of onboard peripherals for Windows family compliance.

The VT8235M Version CD also enhances the functionality of the standard ISA peripherals. The integrated interrupt controller supports both edge and level triggered interrupts channel by channel. The integrated DMA controller supports type F DMA in addition to standard ISA DMA modes. Compliant with the PCI-2.2 specification, the VT8235M Version CD supports delayed transactions and remote power management so that slower ISA peripherals do not block the traffic of the PCI bus. Special circuitry is built in to allow concurrent operation without causing dead lock even in a PCI-to-PCI bridge environment. The chip also includes eight levels (doublewords) of line buffers from the PCI bus to the ISA bus to further enhance overall system performance.

Revision 2.03, March 16, 2005 -4- Overview

VT8235M Version CD V-Link South Bridge

CPU / Cac h e

North Bridge

M A / Co mma n d

Sys tem Memory

Sideband Signals

Init / A20M#

INTR / NMI

SMI / StopClk

Vl i n k Interface

SMB

DIMM Module ID

Expansion

Ca rd s

FERR / IGNNE

Slee

Boo t ROM

LPC

VT8235M

487 BGA

IDE Primary and Secondary

PCI

USB 2.0 Ports 0-5

Onboard

LPC I/ O

Keyboard / Mouse AC97 Link APIC

RTC Cry s t a l

Figure 1. PC System Configuration Using the VT8235M Version CD

GPIO, Power Control, Reset MII Fast Ethernet Interface

Revision 2.03, March 16, 2005 -5- Overview

VT8235M Version CD V-Link South Bridge

PINOUTS Figure 2. Ball Diagram (Top View)

Key 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

GPIO

AGP

MRX

MTX

GND GND

SERR# PERR# STOP#

CBE

AD15 PAR

AD11 AD13 AD14

AD10 AD9 AD12

AD7 AD6 AD4 AD8 GND

AD5 AD2 AD0

AD3 AD1 AD21

AD20 AD22 AD23 GND VCC

CBE

AD24 AD25

AD27 AD26 AD28

AD29 AD31 AD30

INT

PCI

RST#

SDO

SDI3

MS DT

CPU

MISS

EXT

SMI#

SUS CLK

LID#

SMB

DT2

SMB

CK2

SUS

SDI0

SDI2

KB DT

MS CK

RING#

SUS

SMB

ALRT#

SMB

DT1

PWR

BTN#

PWR OK#

SUS

TRUD#

SYNC

CBE

RDY#

DEV

SEL#

RST#

BTCK

SDI1

PME#

SUS

GPO 0 VSUS

SMB

CK1

RTC

FRM# AD16 AD19

RDY#

REQ

GNT

CBE

REQ

GNT

REQ

GNT

REQ5#

GPI7

INT

GNT5#

GPO7

GND

VSUS

GND VCC

BAT

LOW#

THRM#

ST#

VSUS

GPI 1 VSUS

RTC

GPI 0 V

BAT

PWR

AD17

REQ

GNT

VCC

GND

VCC

GND

VSUS

RSM

RST#

GPIO A GPIO C L

PCK

RUN#

AD18

REQ

GNT

GND

BZ#

GPIO 9 GPIO

GPIO

RAM

VCC

VGATE

GPIO8

GPIO

RAM GND

VCC

ERR

MRX

CLK

MRX

GND

VCC VCC GND

MTX

MII

VCC

MII

VCC

MTX

CLK

MTX ENA M CRS

MTX

VCC

G6 7 8 9 10 11 12 13 14 15 16 17 18 19 G20

H GPIO Pins LAN Pins USB Pins H

J J

K K11 12 13 14 15 K16 V-Link K

L PCI Pins L10 GND GND GND GND GND GND L17 Pins L

M M GND GND GND GND GND GND M M

N N GND GND GND GND GND GND N N

P P GND GND GND GND GND GND P P

R R GND GND GND GND GND GND R CPU R

AC97 Pins

U11 12 13 14 15 U16 U

T10 GND GND GND GND GND GND T17 Pins T

V KB/MS Pins Pri V

W PM Pins IDE W

Y LPC Pins X-Bus Pins Sec IDE Pins Pins Y

AA6 7 8 9 10 11 12 13 14 15 16 17 18 19 AA20

VCC

GPIO E CPU

GPIO D L

PCI

STP# L AD3 L AD0

VCC VCC

GND GND IOR#

STP#

REQ# L AD2

FRM# L AD1

IOW#

SPKR

strap

TEST

RDY

SER IRQ

MEM

VCC

SA19

strap

SA18

strap

SA17

strap

SA16

strap

GND GND

OSC

SOE#

strap

MEM

ROMCS

#/strap

CS#

D0 M COL

MII

VCC25

MII

VCC25

VCC

XD 1 XD 0 SD

XD 7 XD 4 SD

XD 6 XD 3 SD

XD 5 XD 2 SDD0

USB

OC0#

USB

OC1#

USB

OC2#

USB

VSUS

OC4#

USB

OC5#

OC3#

VCC VCC

VCC

COMP

RDY

DRQ

SA00

USB

GND

P4+

USB

GND

P4–

USB

GND

USB

GND

P5–

USB

GND

P5+

VCC

VCC VCC GND GND

GND GND

SDD1

SA01

GND

SDD2

SA02

VREF

SDD4

SA04

SDD3 SA03

GND

USB

GND

USB

GND

USB

GND

USB

GND

USB

GND

VCC

SDD5

SA05

SDD7 SA07

SDD6 SA06

USB

P2+

USB

P2–

USB

GND

USB

P3–

USB

P3+

USB

GND

VCC

SDD9

SA09

GND

SDD8

SA08

USB

GND

USB

GND

USB

GND

USB

GND

USB

GND

USB

GND

VCC

GND

SDD10

SA10

SDD12

SA12

SDD11

SA11

USB

P0+

GND

USB

P0–

GND

USB

GND

USB

VCC

P1–

UPLL

USB

GND

P1+

UPLL

USB

VCC

GND

VCC

IOW#

SDD13

SA13

SDD15

SA15

SDD14

SA14

VCC

VAD

VCC

VAD

VCC

VCC VCC

GND GND

VAD

VCC

PLL

VCC

PCI

CLK

APIC

VREF

DRQ

D15

GND

SDA1

strap

DAK#

GND

IOR#

VCC

USB

UPLL

GND

UPLL

USB

REXT

USB CLK

GND

VAD 9 VBE

VAD

GND

VREF

COMP

GND

VCC

PLL

GND

NMI GHI# INIT#

INTR SMI# A20M#

APIC

CLK

APIC

COMP

PD A0

GND

D12

SDCS1#

strap

SDCS3#

strap

SDA0

strap

SDA2

strap

USB

VCC

USB

VCC

USB

VCC

USB

VAD 8 V

VCC

VAD

GND

VAD 0 VAD

VAD

STB

GND

STB

VAD 3 VAD

CMD

VAD 6 UP

CMD

GND

CLK

VCC

VRD

VID

SLP

SEL

TPO SLP# FERR#

CS1#

CS3#

IOR#

PD D0

IRQ

GND

IOW#

GND

D11

GND

PD D7

USB

VCC

USB

VCC

USB

VCC

PAR

VAD

STB#

VAD

VBE

VCC

SLP#

STP

CLK#

IGN NE#

DAK#

RDY

D14

D13

D10

PD D6

Revision 2.03, March 16, 2005 -6- Pin Diagram

VT8235M Version CD V-Link South Bridge

–

Table 1. Pin List (Numerical Order)

Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin # Pin Name

A01 P GND A02 P GND

A03 IO TRDY# A04 IO CBE2# D01 IO CBE1# A05 IO AD17 D02 IO AD15 A06 IO GPIO11 D03 IO PAR A07 IO GPIO12 / INTE# / PCGNTA D04 I REQ2# H24 O UPSTB A08 I AGPBZ# / GPI6 D05 O GNT1# A09 I MRXD3 D06 I REQ0# H26 O UPSTB# A10 I MRXERR D07 IO GPIO10 A11 O MTXD1 D08 IO GPIO14 / INTG# A12 I MTXCLK D09 I MRXD2 A13 O EECS# A14 I EEDO A15 I USBOC0#

A16 P USBGND

A17 IO USBP4+ D14 I USBOC4# J25 IO VAD03 W22–NC AD20 IO SDD10 / SA10

A18 P USBGND D15 P VSUSUSB

A19 IO USBP2+

A20 P USBGND

A21 IO USBP0+

A22 P USBGND A23 P VCCUPLL D20 P USBGND A24 P USBVCC A25 P USBVCC D22 P VCCUPLL A26 P USBVCC B01 P GND B02 P GND

B03 IO DEVSEL# B04 IO FRAME# E01 IO AD11 L03 IO AD25 B05 IO AD16 E02 IO AD13 B06 IO AD19 E03 IO AD14 B07 IO GPIO9 / PCREQB E04 O GNT2# L24 I VCL B08 IO GPIO13 / INTF# / PCGNTB E06 O GNT0# B09 IO MDIO B10 I MRXCLK B11 O MTXD2 B12 O MTXENA E10 I MRXD0 B13 I MCRS B14 O EEDI B15 I USBOC1# E13

B16 P USBGND

B17 IO USBP4– E15 I USBOC3# N04 I REQ5# / GPI7

B18 P USBGND

B19 IO USBP2– E17 IO USBP5+ P02 I INTB# AB23 IO PDD12

B20 P USBGND E18 P USBGND

B21 IO USBP0– E19 IO USBP3+ P04 O GNT5# / GPO7

B22 P USBGND E20 P USBGND P22 P PLLVCC B23 P GNDUPLL B24 P USBVCC E22 P GNDUPLL B25 P USBVCC B26 P USBVCC

C01 I SERR# C02 IO PERR# E26 IO VAD04 R02 O PCIRST# AC06 IO GPIOE / GPIO31 AF05 IO PCKRUN# C03 IO STOP# C04 IO IRDY# C05 I REQ1# C06 IO AD18 F04 IO CBE0# C07 IO GPIO15 / INTH# C08 I VGATE / GPIO8 / PCREQA C09 O MDCK C10 I MRXDV C11 O MTXD3 F23 IO VAD09 C12 O MTXD0 F24 IO VBE0# C13 I MCOL F25 IO VAD00 C14 O EECK

C15 I USBOC2#

C16 P USBGND C17 P USBGND C18 P USBGND C19 P USBGND C20 P USBGND C21 P USBGND C22 P USBGND

C23 AI USBREXT

GND pins (28 pins): F6,11, G5, L11-16, M11-16, N5,11-16, P11-16, R11-16, T11-16, V21, W21, AA5, AB5,12-13,18-19 VCC pins (19 pins): F9-10,14-15, H5, J5,21, K5,21, T5,21, U5,21-22, V5, AB8-9,16-17 VCC33 pins (25 pins): F5,7-8,12-13,16-17, L5, M5, P5,21, R5,21, W5, Y5,21, AA21, AB6-7,10-11,14-15,20-21 VCCVK pins (17 pins): F22, G21, H21, L21-22, M21-26, N21-26

C24 P USBVCC C25 P USBVCC C26 P USBVCC

D10 I MRXD1 J04 O GNT3# W01 IO MSDT / IR

D11 P MIIVCC D12 P MIIVCC J23 P VLVREF

D13

P MIIVCC25

D16 P USBGND

D17 IO USBP5

D18 P USBGND

D19 IO USBP3

D21 IO USBP1

D23 I USBCL

D24 P USBVCC

D25 IO VAD08 D26 IO VPAR

E07 P RAMVCC E08 P RAMGND E09 P GND

E11 P MIIVCC E12 P MIIVCC

P MIIVCC25

E14 I USBOC5#

E16 P GND

E21 IO USBP1+

E23 P GND

E24 IO VAD05

E25 P GND

F01 IO AD10 R03 O ACRST# AC07 O CPUSTP# / GPO5 F02 IO AD09 F03 IO AD12

F18 P USBGND F19 P USBGND F20 P USBGND F21 P USBGND

F26 IO VAD01 G01 IO AD07 G02 IO AD06 G03 IO AD04 T25 OD A20M# G04 IO AD08 G22 IO VAD11 G23 IO VAD10 G24 IO VAD13 G25 I DNSTB G26 I DNSTB# U23 I APICCL

K25 O UPCMD Y22 I PDDR

H01 IO AD05 H02 IO AD02 H03 IO AD00 U26 I FERR# H04 I RE

H22 IO VAD12 V02 IO KBDT / KBRC AD08 IO LAD2

H23 P GND

H25 P GND V22 P GND

J01 IO AD03 J02 IO AD01 J03 IO AD21

J22 IO VAD14 W02 IO MSCK / IR

J24 I DNCMD W04 I BATLOW# / GPI5

J26 IO VAD02 K01 IO AD20 K02 IO AD22 K03 IO AD23

K04 P GND

K22 IO VAD15 Y02 I RING# / GPI3 AD26 IO PDD10

K23 I VLCOMP

K24 IO VAD06 Y04 I THRM# / GPI18 AE02 O PWROK#

K26 IO VAD07 Y23 O PDA0 L01 IO CBE3# L02 IO AD24

L04 I RE

L23 P GND

L25 P GND

L26 IO VBE1# AA22 IO PDD15 AE12 IO MEMR# M01 IO AD27 M02 IO AD26 M03 IO AD28 M04 O GNT4# AA26 IO PDD14 N01 IO AD29 N02 IO AD31 N03 IO AD30

P01 I INTA#

P03 I INTC# AB24 IO PDD02 AE23 O SDA0 / stra

P23 P PLLGND

P24 OD VRDPSLP / GPIO29 AC02 IO SMBDT1 AF01 O SUSC# P25 OD VIDSEL / GPIO28 AC03 I GPI1 AF02 O SUSB# / GPO2 P26 OD DPSLP# / GPIO23 R01 I INTD#

R04 P GND

R22 I PCICL R23 OD NMI AC10 IO IOR# AF09 I TEST R24 OD GHI# / GPIO22 R25 OD INIT# AC12 I OSC AF11 IO SA16 / O16 / stra R26 OD STPCLK# AC13 IO XD1 AF12 O ROMCS#/KBCS#/ T01 O ACSYNC T02 I ACSDIN0 T03 I ACBITCL

T04 P VSUS25 AC17 P GND

T22 O APICD0 T23 OD INTR AC21 O SDIOW# AF18 IO SDD06 / SA06

T24 OD SMI# AC22 O SDA1 / stra

T26 OD IGNNE# AC24 IO PDD04 AF21 IO SDD14 / SA14 U01 O ACSDOUT U02 I ACSDI2 /IO20/PCS0# U03 I ACSDIN1

U04 P VSUS25

U24 O TPO AD04 I RTCX1 U25 OD SLP# AD05 I RSMRST#

V01 I ACSDI3 /IO21/PCS1# /SB#

V03 IO KBCK / A20G AD09 IO IOW#

V04 P GND

V23 O APICD1 V24 O PDCS1# AD13 IO XD7 V25 O PDA1 AD14 IO XD4 V26 O PDA2 AD15 I SDRDY

W03 I PME# AD18 IO SDD05 / SA05

W23 I PDCOMP

W24 O PDCS3# AD22 O SDDACK#

W25 P GND

W26 O PDDACK# AD24 IO PDD09

Y01 I CPUMISS / GPI17 AD25 IO PDD05

Y03 O SUSST1# / GPO3 AE01 IO SMBCK2 /

Y24 O PDIOR# AE05 IO GPIOA / GPIO24 Y25 O PDIOW# AE06 IO GPIOC / GPIO25

Y26 I PDRDY AE07 O LFRM# AA01 IO EXTSMI# / GPI2 AA02 O SUSA# / GPO1 AE09 O SPKR / stra AA03 OD GPO0 AE10 I SERIR

AA04 P VSUS33

AA23 P GND

AA24 IO PDD00 AE14 IO XD3 AA25 IO PDD01 AE15 I SDDR

AB01 O SUSCLK / GPO4 AE17 IO SDD04 / SA04 AB02 I SMBALRT# AE18 IO SDD07 / SA07 AB03 IO SMBCK1

AB04 P VSUS33 AB22 P GND

AB25 P GND

AB26 IO PDD13 AC01 I LID# / GPI4 AE26 IO PDD06

AC04 P VSUS33 AC05 P VSUS33

AC08 P GND AC09 P GND

AC11 IO SA19 / O19 / strap AF10 IO MEMW#

AC14 IO XD0 AF13 IO XD5

AC15 I SDCOMP AC16 P GND

AC20 P GND

AC23 O SDCS1# / stra

AC25 IO PDD11 AF22 O SDIOR#

AC26 IO PDD03 AF23 O SDA2 / stra AD01 IO SMBDT2 / GPIO26 AF24 I IR AD02 I PWRBTN# AF25 IO PDD07 AD03 I INTRUD# / GPI16 AF26 IO PDD08

12 AD16 IO SDD01 / SA01 1 AD17–NC

AF19 IO SDD08 / SA08

AF20 IO SDD11 / SA11

AD06 IO GPIOD / GPIO30 AD07 I LREQ#

AD10 I IORDY / GPI19 AD11 IO SA18 / O18 / stra AD12 O SOE# / stra

AD19 IO SDD09 / SA09

AD21 IO SDD13 / SA13

AD23 O SDCS3# / stra

AE03 I GPI0

AE04 P VBAT

AE08 IO LAD1

AE11 IO SA17 / O17 / stra

AE13 IO XD6

AE16 P GND

AE19 P GND

AE20 IO SDD12 / SA12 AE21 IO SDD15 / SA15

AE22 P GND

AE24 I IRQ14

AE25 P GND

AF03 O RTCX2 AF04 I PWRGD

AF06 O PCISTP# / GPO6 AF07 IO LAD3 AF08 IO LAD0

AF14 IO XD2 AF15 IO SDD00 / SA00 AF16 IO SDD02 / SA02 AF17 IO SDD03 / SA03

Revision 2.03, March 16, 2005 -7- Pin Lists

VT8235M Version CD V-Link South Bridge

–

Table 2. Pin List (Alphabetical Order)

Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin # Pin Name

T25 OD A20M# T03 I ACBITCLK

R03 O ACRST# T02 I ACSDIN0 U03 I ACSDIN1 U02 I ACSDI2 /IO20/PCS0# V01 I ACSDI3 /IO21/PCS1# /SLPB# U01 O ACSDOUT T01 O ACSYNC H03 IO AD00

J02 IO AD01

H02 IO AD02

J01 IO AD03 G03 IO AD04 H01 IO AD05 G02 IO AD06 G01 IO AD07 G04 IO AD08 F02 IO AD09 F01 IO AD10 E01 IO AD11 F03 IO AD12 E02 IO AD13 E03 IO AD14 D02 IO AD15 B05 IO AD16 A05 IO AD17 C06 IO AD18 B06 IO AD19 K01 IO AD20

J03 IO AD21 K02 IO AD22 K03 IO AD23 L02 IO AD24 L03 IO AD25

M02 IO AD26 M01 IO AD27 M03 IO AD28 N01 IO AD29 N03 IO AD30 N02 IO AD31 A08 I AGPBZ# / GPI6 T26 OD IGNNE# AD26 IO PDD10 AA02 O SUSA# / GPO1 F23 IO VAD09 U23 I APICCLK

T22 O APICD0

V23 O APICD1

W04 I BATLOW# / GPI5

F04 IO CBE0#

D01 IO CBE1# A04 IO CBE2#

L01 IO CBE3#

Y01 I CPUMISS / GPI17 AD10 I IORDY / GPI19 Y25 O PDIOW# K25 O UPCMD L26 IO VBE1#

AC07 O CPUSTP# / GPO5

B03 IO DEVSEL#

J24 I DNCMD

G25 I DNSTB G26 I DNSTB#

P26 OD DPSLP# / GPIO23 C14 O EECK

A13 O EECS#

B14 O EEDI

A14 I EEDO

AA01 IO EXTSMI# / GPI2

U26 I FERR#

B04 IO FRAME# R24 OD GHI# / GPIO22

A01 P GND A02 P GND

B01 P GND B02 P GND E09 P GND E16 P GND E23 P GND E25 P GND

H23 P GND H25 P GND

K04 P GND L23 P GND

L25 P GND R04 P GND V04 P GND V22 P GND

W25 P GND AA23 P GND AB22 P GND AB25 P GND AC08 P GND AC09 P GND AC16 P GND AC17 P GND AC20 P GND AE16 P GND AE19 P GND AE22 P GND AE25 P GND

B23 P GNDUPLL E22 P GNDUPLL

E06 O GNT0# AF05 IO PCKRUN# AF21 IO SDD14 / SA14 C23 AI USBREXT D05 O GNT1# R22 I PCICL E04 O GNT2# R02 O PCIRST# AD22 O SDDACK#

J04 O GNT3# AF06 O PCISTP# / GPO6 AE15 I SDDR

M04 O GNT4# Y23 O PDA0 AF22 O SDIOR#

P04 O GNT5# / GPO7 V25 O PDA1 AC21 O SDIOW#

AE03 I GPI0 V26 O PDA2 AD15 I SDRDY

AC03 I GPI1

B07 IO GPIO9 / PCRE D07 IO GPIO10 W24 O PDCS3# U25 OD SLP# A06 IO GPIO11 AA24 IO PDD00 AB02 I SMBALRT# A07 IO GPIO12/INTE#/PCGA AA25 IO PDD01 AB03 IO SMBCK1 F25 IO VAD00 B08 IO GPIO13/INTF#/PCGB AB24 IO PDD02 AE01 IO SMBCK2 / GPIO27 F26 IO VAD01 D08 IO GPIO14 / INTG# AC26 IO PDD03 AC02 IO SMBDT1 J26 IO VAD02

C07 IO GPIO15 / INTH# AC24 IO PDD04 AD01 IO SMBDT2 / GPIO26 J25 IO VAD03 AE05 IO GPIOA / GPIO24 AD25 IO PDD05 T24 OD SMI# E26 IO VAD04 AE06 IO GPIOC / GPIO25 AE26 IO PDD06 AD12 O SOE# / stra

AD06 IO GPIOD / GPIO30 AF25 IO PDD07 AE09 O SPKR / stra AC06 IO GPIOE / GPIO31 AF26 IO PDD08 C03 IO STOP# K26 IO VAD07 AA03 OD GPO0 AD24 IO PDD09 R26 OD STPCLK# D25 IO VAD08

R25 OD INIT# AC25 IO PDD11 AF02 O SUSB# / GPO2 G23 IO VAD10

P01 I INTA# AB23 IO PDD12 AF01 O SUSC# G22 IO VAD11 P02 I INTB# AB26 IO PDD13 AB01 O SUSCLK / GPO4 H22 IO VAD12

P03 I INTC# AA26 IO PDD14 Y03 O SUSST1# / GPO3 G24 IO VAD13 R01 I INTD# AA22 IO PDD15 AF09 I TEST J22 IO VAD14 T23 OD INTR W26 O PDDACK# Y04 I THRM# / GPI18 K22 IO VAD15

AD03 I INTRUD# / GPI16 Y22 I PDDR AC10 IO IOR# Y24 O PDIOR# A03 IO TRDY# F24 IO VBE0#

AD09 IO IOW# Y26 I PDRDY H24 O UPSTB

C04 IO IRDY# C02 IO PERR# H26 O UPSTB#

AE24 I IR AF24 I IR

V03 IO KBCK / A20G W03 I PME# V02 IO KBDT / KBRC AD02 I PWRBTN#

AF08 IO LAD0 AF04 I PWRGD AE08 IO LAD1 AE02 O PWROK#

AD08 IO LAD2

AF07 IO LAD3

AE07 O LFRM# D06 I RE AC01 I LID# / GPI4 C05 I RE AD07 I LRE

C13 I MCOL H04 I RE B13 I MCRS L04 I RE C09 O MDC

B09 IO MDIO Y02 I RING# / GPI3 AE12 IO MEMR# AF12 O ROMCS#/KBCS#/st AF10 IO MEMW# AD05 I RSMRST#

D11 P MIIVCC

D12 P MIIVCC

E11 P MIIVCC

E12 P MIIVCC

D13

14 15

# D04 I REQ2#

N04 I REQ5# / GPI7

P MIIVCC25

E13

P MIIVCC25

B10 I MRXCL E10 I MRXD0 AC22 O SDA1 / stra D10 I MRXD1 AF23 O SDA2 / stra D09 I MRXD2 A09 I MRXD3 AC23 O SDCS1# / stra C10 I MRXDV AD23 O SDCS3# / stra

A10 I MRXERR AF15 IO SDD00 / SA00 D14 I USBOC4# W02 IO MSCK / IR W01 IO MSDT / IR

A12 I MTXCL

C12 O MTXD0 AE17 IO SDD04 / SA04 D21 IO USBP1

A11 O MTXD1 AD18 IO SDD05 / SA05 E21 IO USBP1+

B11 O MTXD2 AF18 IO SDD06 / SA06 B19 IO USBP2

C11 O MTXD3 AE18 IO SDD07 / SA07 A19 IO USBP2+

B12 O MTXENA AF19 IO SDD08 / SA08 D19 IO USBP3 W22

AD17

R23 OD NMI AF20 IO SDD11 / SA11 A17 IO USBP4+

AC12 I OSC AE20 IO SDD12 / SA12 D17 IO USBP5

D03 IO PAR AD21 IO SDD13 / SA13 E17 IO USBP5+

W23 I PDCOMP

B V24 O PDCS1# C01 I SERR#

P23 P PLLGND

P22 P PLLVCC A16 P USBGND

E08 P RAMGND B18 P USBGND

E07 P RAMVCC B20 P USBGND T04 P VSUS25

AD04 I RTCX1

AF03 O RTCX2 AF11 IO SA16 / O16 / stra AE11 IO SA17 / O17 / stra

AD11 IO SA18 / O18 / stra

NC AD19 IO SDD09 / SA09 E19 IO USBP3+ NC AD20 IO SDD10 / SA10 B17 IO USBP4

0# 1#

3# 4#

AC11 IO SA19 / O19 / strap AE23 O SDA0 / strap

AC15 I SDCOMP

1 AD16 IO SDD01 / SA01 E14 I USBOC5# 12 AF16 IO SDD02 / SA02 B21 IO USBP0

AF17 IO SDD03 / SA03 A21 IO USBP0+

AE21 IO SDD15 / SA15

AE10 I SERIR

U24 O TPO

D23 I USBCLK L24 I VCL

A18 P USBGND A20 P USBGND K23 I VLCOMP A22 P USBGND J23 P VLVREF B16 P USBGND

B22 P USBGND U04 P VSUS25 C16 P USBGND AA04 P VSUS33 C17 P USBGND AB04 P VSUS33 C18 P USBGND AC04 P VSUS33 C19 P USBGND AC05 P VSUS33 C20 P USBGND D15 P VSUSUSB C21 P USBGND C22 P USBGND D16 P USBGND D18 P USBGND D20 P USBGND E18 P USBGND E20 P USBGND F18 P USBGND

F19 P USBGND F20 P USBGND

F21 P USBGND

A15 I USBOC0#

B15 I USBOC1# C15 I USBOC2# E15 I USBOC3#

A24 P USBVCC

A25 P USBVCC

A26 P USBVCC

B24 P USBVCC

B25 P USBVCC

B26 P USBVCC

C24 P USBVCC

C25 P USBVCC

C26 P USBVCC

D24 P USBVCC

E24 IO VAD05

K24 IO VAD06

AE04 P VBAT

A23 P VCCUPLL

D22 P VCCUPLL

C08 I VGATE/GPIO8/PCRA

P25 OD VIDSEL / GIO28

D26 IO VPAR

P24 OD VRDPSLP/GPIO29

AC14 IO XD0 AC13 IO XD1 AF14 IO XD2 AE14 IO XD3 AD14 IO XD4 AF13 IO XD5 AE13 IO XD6 AD13 IO XD7

Revision 2.03, March 16, 2005 -8- Pin Lists

VT8235M Version CD V-Link South Bridge

PIN DESCRIPTIONS

V-Link Pin Descriptions

V-Link Interface

Signal Name Pin # I/O Signal Description

VAD[15:0]

VPAR

VBE[1:0]#

VCLK UPCMD

DNCMD UPSTB

UPSTB# DNSTB

DNSTB# VLCOMP

K22, J22, G24, H22, G22, G23, F23, D25, K26, K24, E24, E26,

J25, J26, F26, F25

D26 IO Parity. If the VPAR function is implemented in a compatible manner on the

L26, F24 IO Byte Enables. VBE0# is used with VAD[7-0] and VBE1# is used with

L24 I

K25 O

J24 I

H24 O H26 O

G25 I G26 I

K23 AI

IO Address / Data Bus. Bits 0-7 are implemented and bits 8-15 are reserved for

future use. VAD[7:0] are used to send strap information to the chipset north bridge. At power up VAD7 reflects the state of a strap on SDCS3#, VAD[6:4] reflect the state of straps on pins SDA[2:0] and VAD[3:0] reflect the state of straps on pins SA[19:16]. The specific interpretation of these straps is north bridge chip design dependent.

north bridge, this pin should be connected to the north bridge VPAR pin (P4X333, P4X400, P4X800, KT400). If VPAR is not implemented in the north bridge chip or is incompatible with the 8235 (4x V-Link north bridges) connect this pin to an 8.2K pullup to 2.5V (Pro266, Pro266T, KT266, KT266A, KT333, P4X266, PN266, KN266, KM266, P4M266, P4N266). See app note AN222 for details.

VAD[15-8] (VBE1# and VAD[15-8] are reserved for future use).

V-Link Clock. Command from Client-to-Host.

Command from Host-to-Client. Strobe from Client-to-Host.

Complement Strobe from Client-to-Host. Strobe from Host-to-Client.

Complement Strobe from Host-to-Client. V-Link Compensation.

Revision 2.03, March 16, 2005 -9- Pin Descriptions

VT8235M Version CD V-Link South Bridge

CPU, APIC and CPU Control Pin Descriptions

CPU Interface

Signal Name Pin # I/O Signal Description

A20M#

FERR#

IGNNE# INIT#

INTR

NMI

SLP# SMI#

STPCLK#

Note: Connect each of the above signals to 150 Ω pullup resistors to VCC_CMOS (see Design Guide).

T25 OD A20 Mask. Connect to A20 mask input of the CPU to control address bit-20 generation.

Logical combination of the A20GATE input (from internal or external keyboard controller) and Port 92 bit-1 (Fast_A20).

U26 I Numerical Coprocessor Error. This signal is tied to the coprocessor error signal on the

CPU. Internally generates interrupt 13 if active. Output voltage swing is programmable tot

1.5V or 2.5V by Device 17 Function 0 Rx67[2]. T26 OD Ignore Numeric Error. This pin is connected to the CPU “ignore error” pin. R25 OD Initialization. The VT8235M Version CD asserts INIT# if it detects a shut-down special

cycle on the PCI bus or if a soft reset is initiated by the register

T23 OD CPU Interrupt. INTR is driven by the VT8235M Version CD to signal the CPU that an

interrupt request is pending and needs service.

R23 OD Non-Maskable Interrupt. NMI is used to force a non-maskable interrupt to the CPU. The

VT8235M Version CD generates an NMI when PCI bus SERR# is asserted.

U25 OD Sleep. Used to put the CPU to sleep.

T24 OD System Management Interrupt. SMI# is asserted by the VT8235M Version CD to the

CPU in response to different Power-Management events.

R26 OD Stop Clock. STPCLK# is asserted by the VT8235M Version CD to the CPU to throttle the

processor clock.

Advanced Programmable Interrupt Controller (APIC) Interface

Signal Name Pin # I/O Signal Description

APICD1 APICD0 APICCLK

V23 O Internal APIC Data 1. Function 0 Rx58[6] = 1

T22 O Internal APIC Data 0. Function 0 Rx58[6] = 1

U23 I

APIC Clock.

CPU Speed Control Interface

Signal Name Pin # I/O Signal Description

VGATE / GPI8

/ GPO8 / PCREQA

VIDSEL / GPI2 / GPO2

VRDSLP / GPI29 / GPO29

GHI# / GPI22 / GPO22 DPSLP# / GPI23 / GPO23

CPUMISS / GPI17 Y1 I CPU Missing. Used to detect the physical presence of the CPU chip in its socket. High

AGPBZ# / GPI6 A8 I AGP Busy. Low indicates that an AGP master cycle is in progress (CPU speed transitions

C8 I Voltage Gate. Signal from the CPU voltage regulator. High indicates the voltage regulator

output is stable. This pin performs the VGATE function if Device 17 Function 0 Rx53[7] = 0, E5[4] = 1 and E4[3] = 0.

P25 OD Voltage Regulator ID Select. Connected to the CPU voltage regulator. Low selects the

voltage ID from the CPU; high selects a different fixed voltage ID (the lower voltage used for CPU deep sleep mode). This pin performs the VIDSEL function if Func 0 RxE5[3] = 0.

P24 OD Voltage Regulator Deep Sleep. Connected to the CPU voltage regulator. High selects

the proper voltage for deep sleep mode. This pin performs the VRDPSLP function if Function 0 RxE5[3] = 0.

R24 OD CPU Speed Select. Connected to the CPU voltage regulator, used to select high speed (L)

or low speed (H). This pin performs the GHI# function if Function 0 RxE5[3] = 0.

P26 OD CPU Deep Sleep. This pin performs the DPSLP# function if Device 17 Function 0

RxE5[3]=0.

indicates no CPU present. Connect to the CPUMISS pin of the CPU socket. The state of this pin may be read in the SMBus 2 registers. This pin may be used as CPUMISS and GPI17 at the same time.

will be postponed if this input is asserted low). Connected to the AGP Bus AGPBZ# pin.

Revision 2.03, March 16, 2005 -10- Pin Descriptions

VT8235M Version CD V-Link South Bridge

PCI Bus Interface

Signal Name Pin # I/O Signal Description

AD[31:0]

CBE[3:0]#

DEVSEL#

FRAME#

IRDY# TRDY# STOP# SERR#

PAR INTA#

INTB# INTC# INTD# INTE# / GPI12,

/ GPO12, / PCGNTA, INTF# / GPI13, / GPO13,

/ PCGNTB, INTG# / GPI14

/ GPO14, INTH# / GPI15 / GPO15

REQ5# / GPI7, REQ4#, REQ3#, REQ2#, REQ1#, REQ0# GNT5# / GPO7, GNT4#, GNT3#, GNT2#, GNT1#, GNT0#

PCIRST# PCICLK

PCKRUN#

(see pin

L1, A4,

D1, F4

list)

B3 IO Device Select. The VT8235M Version CD asserts this signal to claim PCI transactions

B4 IO Frame. Assertion indicates the address phase of a PCI transfer. Negation indicates that

C4 IO Initiator Ready. Asserted when the initiator is ready for data transfer. A3 IO Target Ready. Asserted when the target is ready for data transfer. C3 IO Stop. Asserted by the target to request the master to stop the current transaction. C1 I System Error. SERR# can be pulsed active by any PCI device that detects a system error

D3 IO Parity. A single parity bit is provided over AD[31:0] and C/BE[3:0]#.

P1, P2, P3,

A7,

B8,

D8,

L4 H4 D4

C5 D6

E4 D5

R2 O PCI Reset. This signal is used to reset devices attached to the PCI bus.

R22 I PCI Clock. This signal provides timing for all transactions on the PCI Bus.

AF5 IO PCI Bus Clock Run. This signal indicates whether the PCI clock is or will be stopped

IO Address / Data Bus. Multiplexed address and data. The address is driven with FRAME#

assertion and data is driven or received in following cycles.

IO Command / Byte Enable. The command is driven with FRAME# assertion. Byte

enables corresponding to supplied or requested data are driven on following clocks.

through positive or subtractive decoding. As an input, DEVSEL# indicates the response to a VT8235M Version CD-initiated transaction and is also sampled when decoding whether to subtractively decode the cycle.

one more data transfer is desired by the cycle initiator.

condition. Upon sampling SERR# active, the VT8235M Version CD can be programmed to generate an NMI to the CPU.

I PCI Interrupt Request. The INTA# through INTD# pins are typically connected to the

PCI bus INTA#-INTD# pins per the table below. INTE-H# are enabled by setting Device 17, Function 0 Rx5B[1] = 1. BIOS settings must match the physical connection method. INTA# PCI Slot 1 INTA# INTB# INTC# INTD# PCI Slot 2 INTB# INTC# INTD# INTE# PCI Slot 3 INTC# INTD# INTE# INTF# PCI Slot 4 INTD# INTE# INTF# INTG# PCI Slot 5 INTE# INTF# INTG# INTH# PCI Slot 6 INTF# INTG# INTH# INTA#

I PCI Request. These signals connect to the VT8235M Version CD from each PCI slot (or

each PCI master) to request the PCI bus. To use pin N4 as REQ5#, Function 0 RxE4 must be set to 1 otherwise this pin will function as General Purpose Input 7.

O PCI Grant. These signals are driven by the VT8235M Version CD to grant PCI access to

a specific PCI master. To use pin P4 as GNT5#, Function 0 RxE4 must be set to 1 otherwise this pin will function as General Purpose Output 7.

(high) or running (low). The VT8235M Version CD drives this signal low when the PCI clock is running (default on reset) and releases it when it stops the PCI clock. External devices may assert this signal low to request that the PCI clock be restarted or prevent it from stopping. Connect this pin to ground using a 100 Ω resistor if the function is not used. Refer to the “PCI Mobile Design Guide” and an applicable VIA North Bridge Design Guide (e.g., KT400, CLE266, or P4X400) for more details.

INTB# INTC# INTD#

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VT8235M Version CD V-Link South Bridge

MII, Serial EEPROM, LPC and DMA Pin Descriptions

LAN Controller - Media Independent Interface (MII)

Signal Name Pin # I/O PU Signal Description

MCOL MCRS

MDCK

MDIO

MRXCLK MRXD[3-0]

MRXDV MRXERR

MTXCLK

MTXD[3-0]

MTXENA

MIIVCC MIIVCC25

RAMVCC RAMGND

C13 I B13 I

C9 O

B9 IO

B10 I

A9, D9, D10, E10 I

C10 I A10 I

A12 I

C11, B11, A11, C12 O

B12 O

D11, D12, E11, E12

D13, E13

E7 E8

Power Power

Power Power Ground For Internal LAN RAM.

MII Collision Detect. From the external PHY.

MII Carrier Sense. Asserted by the external PHY when the media is

active. MII Management Data Clock. Sent to the external PHY as a timing

reference for MDIO MII Management Data I/O. Read from the MDI bit or written to the

MDO bit. MII Receive Clock. 2.5 or 25 MHz clock recovered by the PHY.

MII Receive Data. Parallel receive data lines driven by the external

PHY synchronous with MRXCLK.

PD MII Receive Data Valid.

MII Receive Error. Asserted by the PHY when it detects a data

decoding error. MII Transmit Clock. Always active 2.5 or 25 MHz clock supplied by

the PHY. MII Transmit Data. Parallel transmit data lines synchronized to

MTXCLK. MII Transmit Enable. Signals that transmit is active from the MII

port to the PHY. MII Interface Power. 3.3V ±5%.

MII Suspend Power. 2.5V ±5%. Power For Internal LAN RAM. 2.5V ±5%.

Serial EEPROM Interface

Signal Name Pin # I/O PU Signal Description

EECS# EECK EEDO EEDI

These pins are disabled if the SDCS1# pin is strapped low to enable serial EEPROM connection via the MII interface.

A13 O C14 O

Serial EEPROM Chip Select. Serial EEPROM Clock.

A14 I Serial EEPROM Data Output. Connect to EEPROM Data Out pin. B14 O Serial EEPROM Data Input. Connect to EEPROM Data In pin.

Low Pin Count (LPC) Interface

Signal Name Pin # I/O PU Signal Description

LFRM# LREQ# LAD[3-0]

Note: Connect the LPC interface LPCRST# (LPC Reset) signal to PCIRST#

AF7, AD8, AE8, AF8 IO PU

AE7 O AD7 I

LPC Frame. LPC DMA / Bus Master Request. LPC Address / Data.

PC / PCI DMA

Signal Name Pin # I/O PU Signal Description

PCREQA / GPI8 / GPO8 / VGATE PCREQB / GPI9 / GPO9 B7 I PC / PCI Request B. Device 17 Function 0 Rx53[7] = 1 PCGNTA / GPI12 / GPO12 A7 O PC / PCI Grant A. Device 17 Function 0 Rx53[7] = 1 PCGNTB / GPI13 / GPO13 B8 O PC / PCI Grant B. Device 17 Function 0 Rx53[7] = 1

C8 I PC / PCI Request A. Device 17 Function 0 Rx53[7] = 1

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VT8235M Version CD V-Link South Bridge

USB, SMB and Programmable Chip Select Pin Descriptions

Universal Serial Bus 2.0 Interface

Signal Name Pin # I/O Signal Description

USBP0+ USBP0–

USBP1+ USBP1–

USBP2+ USBP2–

USBP3+ USBP3–

USBP4+ USBP4–

USBP5+ USBP5–

USBCLK USBREXT

USBOC0# USBOC1# USBOC2# USBOC3# USBOC4# USBOC5#

USBVCC USBGND

VSUSUSB VCCUPLL

GNDUPLL

A21 IO B21 IO

E21 IO

D21 IO A19 IO

B19 IO

E19 IO

D19 IO A17 IO

B17 IO

E17 IO

D17 IO D23 I USB 2.0 Clock. 48MHz clock input for the USB interface

C23 AI A15 I USB 2.0 Port 0 Over Current Detect. Port 0 is disabled if low.

B15 I USB 2.0 Port 1 Over Current Detect. Port 1 is disabled if low. C15 I USB 2.0 Port 2 Over Current Detect. Port 2 is disabled if low.

E15 I USB 2.0 Port 3 Over Current Detect. Port 3 is disabled if low.

D14 I USB 2.0 Port 4 Over Current Detect. Port 4 is disabled if low.

E14 I USB 2.0 Port 5 Over Current Detect. Port 5 is disabled if low.

(see pin list) (see pin list)

D15

A23, D22

B23, E22

Power Power USB 2.0 Port Differential Output Interface Logic Ground.

Power Power

Power USB 2.0 PLL Analog Ground.

USB 2.0 Port 0 Data + USB 2.0 Port 0 Data –

USB 2.0 Port 1 Data + USB 2.0 Port 1 Data –

USB 2.0 Port 2 Data + USB 2.0 Port 2 Data –

USB 2.0 Port 3 Data + USB 2.0 Port 3 Data –

USB 2.0 Port 4 Data + USB 2.0 Port 4 Data –

USB 2.0 Port 5 Data + USB 2.0 Port 5 Data –

USB External Resistor.

USB 2.0 Port Differential Output Interface Logic Voltage. 3.3V

USB 2.0 Suspend Power. 2.5V ±5%. USB 2.0 PLL Analog Voltage. 2.5V ±5%.

System Management Bus (SMB) Interface (I2C Bus)

Signal Name Pin # I/O Signal Description

SMBCK1 SMBCK2 / GPI27 / GPO27 AE1 IO SMB / I2C Channel 2 Clock. Rx95[2] = 0

SMBDT1 SMBDT2 / GPI26 / GPO26 AD1 IO SMB / I2C Channel 2 Data. Rx95[2] = 0

SMBALRT#

AB3 IO

AC2 IO

AB2 I SMB Alert. (enabled by System Management Bus I/O space Rx08[3] =

SMB / I2C Channel 1 Clock.

SMB / I2C Channel 1 Data.

1) When the chip is enabled to allow it, assertion generates an IRQ or SMI interrupt or a power management resume event. Connect to a 10K ohm pullup to VSUS33 if not used.

Programmable Chip Selects

Signal Name Pin # I/O Signal Description

PCS0# / GPIO20 / ACSDIN2 U2 O Programmable Chip Select 0. RxE4[6]=1, E5[1]=1 PCS1# / GPIO21 / ACSDIN3 / SLPBTN# V1 O Programmable Chip Select 1. RxE4[6]=1, E5[2]=1

Revision 2.03, March 16, 2005 -13- Pin Descriptions

VT8235M Version CD V-Link South Bridge

EIDE Interface Pin Descriptions

UltraDMA-133 / 100 / 66 / 33 Enhanced IDE Interface

Signal Name Pin # I/O Signal Description

PDRDY /

PDDMARDY / PDSTROBE

SDRDY / SDDMARDY / SDSTROBE

PDIOR# / PHDMARDY / PHSTROBE

SDIOR# / SHDMARDY / SHSTROBE

PDIOW# / PSTOP

SDIOW# / SSTOP

PDDRQ SDDRQ

PDDACK# SDDACK#

IRQ14 IRQ15

Y26 I EIDE Mode: Primary I/O Channel Ready. Device ready indicator

UltraDMA Mode: Primary Device DMA Ready. Output flow control. The device may

assert DDMARDY to pause output transfers

Primary Device Strobe. Input data strobe (both edges). The device

may stop DSTROBE to pause input data transfers

AD15 I EIDE Mode: Secondary I/O Channel Ready. Device ready indicator

UltraDMA Mode: Secondary Device DMA Ready. O

may assert DDMARDY to pause output transfers

Secondary Device Strobe. Input data strobe (both edges). The device

may stop DSTROBE to pause input data transfers

Y24 O EIDE Mode: Primary Device I/O Read. Device read strobe

UltraDMA Mode: Primary Host DMA Ready. Primary

host may assert HDMARDY to pause input transfers

Primary Host Strobe. Output data strobe (both edges). The host may

stop HSTROBE to pause output data transfers

AF22 O EIDE Mode: Secondary Device I/O Read. Device read strobe

UltraDMA Mode: Secondary Host DMA Ready. Input flow control. The host may

assert HDMARDY to pause input transfers

Host Strobe B. Output strobe (both edges). The host may stop

HSTROBE to pause output data transfers

Y25 O EIDE Mode: Primary Device I/O Write. Device write strobe

UltraDMA Mode: Primary Stop. Stop transfer: Asserted by the host prior to initiation of

an UltraDMA burst; negated by the host before data is transferred in an UltraDMA burst. Assertion of STOP by the host during or after data transfer in UltraDMA mode signals the termination of the burst.

AC21 O EIDE Mode: Secondary Device I/O Write. Device write strobe

UltraDMA Mode: Secondary Stop. Stop transfer: Asserted by the host prior to initiation

of an UltraDMA burst; negated by the host before data is transferred in an UltraDMA burst. Assertion of STOP by the host during or after data transfer in UltraDMA mode signals the termination of the burst.

Y22 I Primary Device DMA Request. Primary

AE15 I Secondary Device DMA Request. Secondary

W26 O Primary Device DMA Acknowledge. Primary

AD22 O Secondary Device DMA Acknowledge. Secondary

AE24 I AF24 I

Primary Channel Interrupt Request. Secondary Channel Interrupt Request.

channel DMA request

channel DMA acknowledge

utput flow control. The device

channel input flow control. The

channel DMA acknowledge

Revision 2.03, March 16, 2005 -14- Pin Descriptions

VT8235M Version CD V-Link South Bridge

UltraDMA-133 / 100 / 66 / 33 Enhanced IDE Interface (continued)

Signal Name Pin # I/O Signal Description

PDCS1#

PDCS3#

SDCS1# / strap AC23 O Secondary Master Chip Select. This signal corresponds to CS17X#

SDCS3# / strap AD23 O Secondary Slave Chip Select. This signal corresponds to CS37X# on

PDA[2-0]

SDA[2-0] / strap AF23, AC22, AE23 O Secondary Disk Address. SDA[2:0] are used to indicate which byte in

PDD[15-0] SDD[15-0] / SA[15-0] (see pin list) IO / IO

PDCOMP SDCOMP

V24 O Primary Master Chip Select. This signal corresponds to CS1FX# on

the primary IDE connector.

W24 O Primary Slave Chip Select. This signal corresponds to CS3FX# on

the primary IDE connector.

on the secondary IDE connector. Strap low (resistor to ground) to enable serial EEPROM interface via the MII bus (this disables the EExx pins). This pin has an internal pullup to default to serial EEPROM interface via the EExx pins.

the secondary IDE connector. Strap information is communicated to the north bridge via VAD[7].

V26, V25, Y23 O Primary Disk Address. PDA[2:0] are used to indicate which byte in

either the ATA command block or control block is being accessed.

either the ATA command block or control block is being accessed. Strap information is communicated to the north bridge via VAD[6:4].

(see pin list) IO

W23 I

AC15 I

Primary Disk Data. Secondary Disk Data.

Primary Disk Compensation. Secondary Disk Compensation.

Serial IRQ and AC97 Pin Descriptions

Serial IRQ

Signal Name Pin # I/O Signal Description

SERIRQ

AE10 I Serial IRQ. This pin has an internal pull-up resistor.

AC97 Audio / Modem Interface

Signal Name Pin # I/O Signal Description

ACRST# ACBTCK ACSYNC ACSDO

ACSDIN0 (VSUS33)† T2 I ACSDIN1 (VSUS33)† U3 I ACSDIN2 / GPIO20 / PCS0# U2 I AC97 Serial Data In 2. RxE4[6]=0,E5[1]=0, PMIO Rx4C[20]=1 ACSDIN3 / GPIO21 / PCS1# / SLPBTN# V1 I AC97 Serial Data In 3. RxE4[6]=0,E5[2]=0, PMIO Rx4C[21]=1

†The supply voltage for ACSDIN0-1 is VSUS33 so these inputs can support wake-up on modem ring.

R3 O T3 I T1 O

U1 O

AC97 Reset. AC97 Bit Clock. AC97 Sync. AC97 Serial Data Out.

AC97 Serial Data In 0. AC97 Serial Data In 1.

Revision 2.03, March 16, 2005 -15- Pin Descriptions

VT8235M Version CD V-Link South Bridge

Internal Keyboard Controller and Speaker Pin Descriptions

Internal Keyboard Controller

Signal Name Pin # I/O PU Signal Description

MSCK / IRQ1 W2 IO / I PU MultiFunction Pin (Internal mouse controller enabled by Rx51[1])

Rx51[2]=1 Mouse Clock. From internal mouse controller. Rx51[2]=0 Interrupt Request 1. Interrupt input 1.

MSDT / IRQ12 W1 IO / I PU MultiFunction Pin (Internal mouse controller enabled by Rx51[1])

Rx51[2]=1 Mouse Data. From internal mouse controller. Rx51[2]=0 Interrupt Request 12. Interrupt input 12.

KBCK / KA20G V3 IO / I PU MultiFunction Pin (Internal keyboard controller enabled by

Rx51[0]) Rx51[0]=1 Keyboard Clock. From internal keyboard controller Rx51[0]=0 Gate A20. Input from external keyboard controller.

KBDT / KBRC V2 IO / I PU MultiFunction Pin (Internal keyboard controller enabled by

Rx51[0]) Rx51[0]=1 Keyboard Data. From internal keyboard controller. Rx51[0]=0 Keyboard Reset. From external keyboard controller

(KBC) for CPURST# generation

KBCS# / ROMCS# / strap AF12 O / O Keyboard Chip Select (Rx51[0]=0). To external keyboard

controller chip. Strap high to enable LPC ROM:

Note: KBCK, KBDT, MSCK, and MSDT are powered by the VSUS33 suspend voltage plane.

ISA Subset / Parallel BIOS ROM Interface

Signal Name Pin # I/O PU Signal Description

ROMCS# / KBCS# /

strap

SPKR / strap AE9 O Speaker. Strap low to enable (high to disable) CPU frequency

MEMR# MEMW#

IOR# IOW#

IORDY / GPI19 AD10 I I/O Ready. Used to insert wait states in I/O or memory cycles.

SOE# / strap AD12 O XD Bus Tranceiver Output Enable. Strap low to enable auto

XD[7-0]

SA[19-16] / GPO[19-16] / straps SA[15-0] / SDD[15-0] (see pin list) O

AF12 O ROM Chip Select (Rx51[0]=1). Chip Select to the BIOS ROM.

Strap high to enable LPC ROM.

strapping.

AE12 O AF10 O

AC10 O

AD9 O

AD13, AE13, AF13, AD14,

AE14, AF14,

AC13, AC14

AC11, AD11,

AE11, AF11

IO XD Bus. For input of BIOS ROM data or data from other on-board

Memory Read. Memory Write.

I/O Read. I/O Write.

RxE5[0] = 0

reboot.

I/O or memory devices.

System Address 19-16. Strap states are passed to North Bridge via

VAD[3-0]. Functions as SA[19-16] if RxE4[5] = 0. System Address 15-0.

Revision 2.03, March 16, 2005 -16- Pin Descriptions

VT8235M Version CD V-Link South Bridge

General Purpose Input Pin Descriptions

General Purpose Inputs

Signal Name Pin # I/O Signal Description

GPI0 (VBAT) GPI1 (VSUS33)

GPI2 / EXTSMI# (VSUS33) AA1 I General Purpose Input 2. Status on PMIO Rx20[4] GPI3 / RING# (VSUS33) Y2 I General Purpose Input 3. Status on PMIO Rx20[8] GPI4 / LID# (VSUS33) AC1 I General Purpose Input 4. Status on PMIO Rx20[11] GPI5 / BATLOW# (VSUS33) W4 I General Purpose Input 5. Status on PMIO Rx20[12] GPI6 / AGPBZ# A8 I General Purpose Input 6. Status on PMIO Rx20[5] GPI7 / REQ5# N4 I General Purpose Input 7. RxE4[2] = 0

GPI8 / GPO8 / PCREQA / VGATE C8 I General Purpose Input 8. RxE4[3] = 0, E5[4]=0, 53[7] = 0 GPI9 / GPO9 / PCREQB B7 I General Purpose Input 9. RxE4[3] = 0, 53[7] = 0 GPI10 / GPO10 D7 I General Purpose Input 10. RxE4[3] = 0 GPI11 / GPO11 A6 I General Purpose Input 11. RxE4[3] = 0

GPI12 / GPO12 / INTE# / PCGNTA A7 I General Purpose Input 12. RxE4[4] = 0, 5B[1]=0, 53[7]=0 GPI13 / GPO13 / INTF# / PCGNTB B8 I General Purpose Input 13. RxE4[4] = 0, 5B[1]=0, 53[7]=0 GPI14 / GPO14 / INTG# D8 I General Purpose Input 14. RxE4[4] = 0, 5B[1]=0 GPI15 / GPO15 / INTH# C7 I General Purpose Input 15. RxE4[4] = 0, 5B[1]=0

GPI16 / INTRUDER# (VBAT) AD3 I General Purpose Input 16. Status on PMIO Rx20[6] GPI17 / CPUMISS Y1 I General Purpose Input 17. Status on PMIO Rx20[5]

GPI18 / THRM# / AOLGPI Y4 I General Purpose Input 18. Rx8C[3] = 0 GPI19 / IORDY AD10 I General Purpose Input 19. RxE5[0] = 1

GPI20 / GPO20 / ACSDIN2 / PCS0# U2 I General Purpose Input 20. RxE4[6]=1, E5[1]=0,

GPI21 / GPO21 / ACSDIN3 / PCS1# / SLPBTN# V1 I General Purpose Input 21. RxE4[6]=1, E5[2]=0

GPI22 / GPO22 / GHI# R24 I General Purpose Input 22. RxE5[3] = 1, PMIO 4C[22] = 1 GPI23 / GPO23 / DPSLP# P26 I General Purpose Input 23. RxE5[3] = 1, PMIO 4C[23] = 1

GPI24 / GPO24 / GPIOA AE5 I General Purpose Input 24. RxE6[0] = 0 GPI25 / GPO25 / GPIOC AE6 I General Purpose Input 25. RxE6[1] = 0

GPI26 / GPO26 / SMBDT2 (VSUS33) AD1 I General Purpose Input 26. Rx95[2] = 1, 95[3] = 0 GPI27 / GPO27 / SMBCK2 (VSUS33) AE1 I General Purpose Input 27. Rx95[2] = 1, 95[3] = 0

GPI28 / GPO28 / VIDSEL P25 I General Purpose Input 28. RxE5[3] = 1, PMIO 4C[28] = 1 GPI29 / GPO29 / VRDSLP P24 I General Purpose Input 29. RxE5[3] = 1, PMIO 4C[29] = 1

GPI30 / GPO30 / GPIOD AD6 I General Purpose Input 30. RxE6[6] = 0 GPI31 / GPO31 / GPIOE AC6 I General Purpose Input 31. RxE6[7] = 0

Note: Default pin function is underlined in the signal name column above. Note: Input pin status for the above GPI pins 31-0 is also available on PMIO Rx4B-48[31-0] Note: See also Power Management I/O register Rx50 for input pin change status for GPI16-19 and 24-27 Note: See also Power Management I/O register Rx52 for SCI/SMI select for GPI16-19 and 24-27 Note: See also Power Management I/O register Rx4C. General purpose input pins 20-31 are shared with OD (open drain) general purpose output functions, so to use one of these pins as an input pin, a one must be written to the corresponding bit of PMIO Rx4C.

AE3 I General Purpose Input 0. Status on PMIO Rx20[0] AC3 I General Purpose Input 1. Status on PMIO Rx20[1]

PMIO 4C[20] = 1

PMIO 4C[21] = 1

Revision 2.03, March 16, 2005 -17- Pin Descriptions

VT8235M Version CD V-Link South Bridge

General Purpose Output and GPIO Pin Descriptions

General Purpose Outputs

Signal Name Pin # I/O Signal Description

GPO0 (VSUS33) GPO1 / SUSA# (VSUS33) AA2 O General Purpose Output 1. Rx94[2] = 1 GPO2 / SUSB# (VSUS33) AF2 O General Purpose Output 2. Rx94[3] = 1 GPO3 / SUSST1# (VSUS33) Y3 O General Purpose Output 3. Rx94[4] = 1 GPO4 / SUSCLK (VSUS33) AB1 O General Purpose Output 4. Rx95[1] = 1

GPO5 / CPUSTP# AC7 O General Purpose Output 5. RxE4[0] = 1 GPO6 / PCISTP# AF6 O General Purpose Output 6. RxE4[1] = 1 GPO7 / GNT5# P4 O General Purpose Output 7. RxE4[2] = 0

GPO8 / GPI8 / PCREQA / VGATE C8 O General Purpose Output 8. RxE4[3]=1, E5[4]=0, 53[7]=0 GPO9 / GPI9 / PCREQB B7 O General Purpose Output 9. RxE4[3]=1, 53[7]=0 GPO10 / GPI10 D7 O General Purpose Output 10. RxE4[3]=1 GPO11 / GPI11 A6 O General Purpose Output 11. RxE4[3]=1

GPO12 / GPI12 / INTE# / PCGNTA A7 O General Purpose Output 12. RxE4[4]=1, 5B[1]=0, 53[7]=0 GPO13 / GPI13 / INTF# / PCGNTB B8 O General Purpose Output 13. RxE4[4]=1, 5B[1]=0, 53[7]=0 GPO14 / GPI14 / INTG# D8 O General Purpose Output 14. RxE4[4]=1, 5B[1]=0 GPO15 / GPI15 / INTH# C7 O General Purpose Output 15. RxE4[4]=1, 5B[1]=0

GPO16 / SA16 / strap AF11 O General Purpose Output 16. RxE4[5] = 1 GPO17 / SA17 / strap AE11 O General Purpose Output 17. RxE4[5] = 1 GPO18 / SA18 / strap AD11 O General Purpose Output 18. RxE4[5] = 1 GPO19 / SA19 / strap AC11 O General Purpose Output 19. RxE4[5] = 1

GPO20 / GPI20 / ACSDIN2 / PCS0# U2 OD General Purpose Output 20. RxE4[6]=1, E5[1]=0 GPO21 / GPI21 / ACSDIN3 / PCS1# /SLPBTN# V1 OD General Purpose Output 21. RxE4[6]=1, E5[2]=0

GPO22 / GPI22 / GHI# R24 OD General Purpose Output 22. RxE5[3]=1 GPO23 / GPI23 / DPSLP# P26 OD General Purpose Output 23. RxE5[3]=1 GPO24 / GPI24 / GPIOA AE5 O/OD General Purpose Output 24. RxE6[0] = 1 GPO25 / GPI25 / GPIOC AE6 O/OD General Purpose Output 25. RxE6[1] = 1

GPO26 / GPI26 / SMBDT2 (VSUS33†) AD1 OD General Purpose Output 26. Rx95[2] = 1, 95[3] = 1 GPO27 / GPI27 / SMBCK2 (VSUS33†) AE1 OD General Purpose Output 27. Rx95[2] = 1, 95[3] = 1 GPO28 / GPI28 / VIDSEL P25 OD General Purpose Output 28. RxE5[3] = 1 GPO29 / GPI29 / VRDSLP P24 OD General Purpose Output 29. RxE5[3] = 1 GPO30 / GPI30 / GPIOD AD6 O/OD General Purpose Output 30. RxE6[6] = 1 GPO31 / GPI31 / GPIOE AC6 O/OD General Purpose Output 31. RxE6[7] = 1

Note: The output state for each of the above general purpose outputs is selectable via Power Management I/O registers Rx4C-48 Note: The output types of GPO24-25 and 30-31 are selectable OD vs TTL (see Function 0 RxE7) Note: Default pin functions are underlined in the table above. † The suspend voltage is only used for maintaining the operation of the SMB function on thses pins (Device 17 Function 0 Rx95[3] = 0). If VCC power is lost, the GPIO function of these pins and the state of PMIO Rx4C[27:26} (which determines the GPO output level) will be lost also.

AA3 O

General Purpose Output 0.

General Purpose I/O

Signal Name Pin # I/O Signal Description

GPIOA / GPI24 / GPO24 AE5 IO General Purpose I/O A / 24. RxE6[0] = 1 GPIOC / GPI25 / GPO25 AE6 IO General Purpose I/O C / 25. RxE6[1] = 1 GPIOD / GPI30 / GPO30 AD6 IO General Purpose I/O D / 30. RxE6[6] = 1 GPIOE / GPI31 / GPO31 AC6 IO General Purpose I/O E / 31. RxE6[7] = 1

The output type of the above pins may be selected as either OD or TTL (see Device 17 Function 0 RxE7)

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Power Management and Event Detection Pin Descriptions

Power Management and Event Detection

Signal Name Pin # I/O Signal Description

PWRBTN#

SLPBTN# / GPIO21 / ACSDIN3 / PCS1# RSMRST#

EXTSMI# / GPI2 AA1 IOD External System Management Interrupt. When enabled to allow it, a falling edge on

PME# SMBALRT#

LID# / GPI4 AC1 I Notebook Computer Display Lid Open / Closed Monitor. Used by the Power

INTRUDER# / GPI16 AD3 I Intrusion Indicator. The value of this bit may be read at PMIO Rx20[6] THRM# / GPI18

/ AOLGPI

RING# / GPI3 Y2 I Ring Indicator. May be connected to external modem circuitry to allow the system to

BATLOW# / GPI5 W4 I Battery Low Indicator. (10K PU to VSUS33 if not used) (3.3V only) CPUSTP# / GPO5 AC7 O CPU Clock Stop (RxE4[0] = 0). Signals the system clock generator to disable the

PCISTP# / GPO6 AF6 O PCI Clock Stop (RxE4[1] = 0). Signals the system clock generator to disable the PCI

SUSA# / GPO1 AA2 O Suspend Plane A Control (Rx94[2]=0). Asserted during power management POS,

SUSB# / GPO2 AF2 O Suspend Plane B Control (Rx94[3]=0). Asserted during power management STR and

SUSC#

SUSST1# / GPO3 Y3 O Suspend Status 1 (Rx94[4] = 0). Typically connected to the North Bridge to provide

SUSCLK

CPUMISS / GPI17 Y1 I CPU Missing. Used to detect the physical presence of the CPU chip in its socket.

AOLGPI / GPI18

/ THRM#

AD2 I Power Button. Used by the Power Management subsystem to monitor an external

system on/off button or switch. Internal logic powered by VSUS33.

V1 I Sleep Button. Used by the Power Management subsystem to monitor an external sleep

button or switch. RxE4[6] = 1, 80[6] = 1, E5[2] = 0 and PMIO Rx4C[21] = 1

AD5 I Resume Reset. Resets the internal logic connected to the VSUS33 power plane and

also resets portions of the internal RTC logic. Internal logic powered by VBAT.

this input causes an SMI# to be generated to the CPU to enter SMI mode. (10K PU to VSUS33 if not used) (3.3V only)

W3 I Power Management Event. (10K PU to VSUS33 if not used)

AB2 I SMB Alert. When programmed to allow it (SMB I/O Rx8[3]=1), assertion generates

an IRQ, SMI, or power management event. (10K PU to VSUS33 if not used)

Management subsystem to monitor the opening and closing of the display lid of notebook computers. Can be used to detect either low-to-high or high-to-low transitions to generate an SMI#. (10K PU to VSUS33 if not used)

Y4 I Thermal Alarm Monitor. Rx8C[3] = 1. Rising or falling edges (selectable by PMIO

Rx2C[6]) may be detected to set status at PMIO Rx20[10]. Setting of this status bit may then be used to generate an SCI or SMI. THRM# may also be used to enable duty cycle control of stop-clock (STPCLK#) to automatically limit maximum temperature (see Device 17 Function 0 Rx8C[7-3]).

be re-activated by a received phone call. (10K PU to VSUS33 if not used)

CPU clock outputs. Not connected if not used.

clock outputs. Not connected if not used.

STR, and STD suspend states. Used to control the primary power plane. (10K PU to VSUS33 if not used)

STD suspend states. Used to control the secondary power plane. (10K PU to VSUS33 if not used)

AF1 O Suspend Plane C Control. Asserted during power management STD suspend state.

Used to control the tertiary power plane. Also connected to ATX power-on circuitry. (10K PU to VSUS33 if not used)

information on host clock status. Asserted when the system may stop the host clock, such as Stop Clock or during POS, STR, or STD suspend states. Connect 10K PU to VSUS33.

AB1 O Suspend Clock. 32.768 KHz output clock for use by the North Bridge (e.g., KT400A,

CLE266 or P4X400) for DRAM refresh purposes. Stopped during Suspend-to-Disk and Soft-Off modes. Connect 10K PU to VSUS33.

High indicates no CPU present. Connect to the CPUMISS pin of the CPU socket. The state of this pin may be read in the SMBus 2 registers. This pin may be used as CPUMISS and GPI17 at the same time.

Y4 I Alert On LAN. The state of this pin may be read in the SMBus 2 registers. This pin

may be used as AOLGPI, GPI18 and THRM# all at the same time.

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VT8235M Version CD V-Link South Bridge

Clock, Resets, Power Status, Power and Ground Pin Descriptions

Resets, Clocks, and Power Status

Signal Name Pin # I/O Signal Description

PWRGD

PWROK# PCIRST#

OSC RTCX1

RTCX2 TEST

TPO NC

AF4 I Power Good. Connected to the Power Good signal on the Power Supply. Internal logic

AE2 O Power OK. Internal logic powered by VSUS33.

R2 O PCI Reset. Active low reset signal for the PCI bus. The VT8235M Version CD will

assert this pin during power-up or from the control register.

AC12 I Oscillator. 14.31818 MHz clock signal used by the internal Timer.

AD4 I RTC Crystal Input: 32.768 KHz crystal or oscillator input. This input is used for the

internal RTC and power-well power management logic and is powered by VBAT.

AF3 O RTC Crystal Output: 32.768 KHz crystal output. Internal logic powered by VBAT. AF9 I

U24 O Test Pin Output. Output pin for test mode.

W22, AD17 – No Connect. Reserved. Do not connect.

Test.

Power and Ground

Signal Name Pin # I/O Signal Description

VCC33 VCC

GND VSUS33

VSUS25 VSUSUSB VBAT

VLVREF VCCVK

MIIVCC

MIIVCC25 RAMVCC

RAMGND USBVCC

USBGND VCCUPLL

GNDUPLL PLLVCC

PLLGND

†Created by a resistive voltage divider of 1KΩ 1% to 3.3V and 383Ω 1% to ground (see Design Guide)

(see pin list) P (see pin list) P

(see pin list) P Ground. Connect to primary motherboard ground plane.

AA4, AB4,

AC4, AC5

T4, U4 P Suspend Power. 2.5V ±5%.

D15 P USB Suspend Power. 2.5V ±5%.

AE4 P RTC Battery. Battery input for internal RTC (RTCX1, RTCX2)

J23 P V-Link Voltage Reference. 0.9V ±5% for 4x transfers and 0.625V ±5% for 8x transfers.

(see pin list) P

D11, D12,

E11, E12

D13, E13 P LAN MII Suspend Power. 2.5V ±5%.

E7 P LAN RAM Power. 2.5V ±5%. Power for LAN internal RAM. Connect to VCC

E8 P LAN RAM Ground. Connect to GND through a ferrite bead.

(see pin list) P USB 2.0 Differential Output Power. 3.3V ±5%. Power for USB differential outputs

(see pin list) P USB 2.0 Differential Output Ground. Connect to GND through a ferrite bead.

A23, D22 P USB 2.0 PLL Analog Voltage. 2.5V ±5%. Connect to VCC through a ferrite bead. B23, E22 P USB 2.0 PLL Analog Ground. Connect to GND through a ferrite bead.

P22 P PLL Analog Power. 2.5V ±5%. Connect to VCC through a ferrite bead. P23 P PLL Analog Ground. Connect to GND through a ferrite bead.

I/O Power. 3.3V ±5% Core Power. 2.5V ±5%. This supply is turned on only when the mechanical switch on

the power supply is turned on and the PWRON signal is conditioned high. Note: The VT8233A Version CE (VT8235ML) core voltage is 3.3V so board designs that are intended to allow use of either VT8235M Version CD or VT8233A Version CE (VT8235ML) should take this difference into account and allow the core voltage to be selected as either 2.5V (for the VT8235M Version CD) or 3.3V (for the VT8233A Version CE / VT8235ML).

P Suspend Power. 3.3V ±5%. Always available unless the mechanical switch of the

power supply is turned off. If the “soft-off” state is not implemented, then this pin can be connected to VCC33. Signals powered by or referenced to this plane are: PWRGD, RSMRST#, PWRBTN#, SMBCK1/2, SMBDT1/2, GPO0, SUSA# / GPO1, SUSB# / GPO2, SUSC#, SUSST1# / GPO3, SUSCLK / GPO4, GPI1, GPI2 / EXTSMI#, GPI3 / RING#, GPI4 / LID, GPI5 / BATLOW#, GPI6 / PME#, SMBALRT#

V-Link Compensation Circuit Voltage. 2.5V ±5%

P LAN MII Power. 3.3V ±5%.Power for LAN Media Independent Interface (interface to

external PHY). Connect to VCC33 through a ferrite bead.

through a ferrite bead.

(USBP0+, P0–, P1+, P1–, P2+, P2–, P3+, P3–, P4+, P4–, P5+, P5–). Connect to VSUS33 through a ferrite bead.

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VT8235M Version CD V-Link South Bridge

Strap Pin Descriptions

Strap Pins

Strap Pins for VT8235M Version CD Configuration

Signal Name Pin # Function Description Note

Strap_SOE# AD12 Auto Reboot L: Enable Auto Reboot

H: Disable Auto Reboot (Default)

SPKR AE9 CPU Frequency Strapping L: Enable CPU Frequency Strapping

H: Disable CPU Frequency Strapping (Default)

ROMCS# / KBCS# AF12 Internal Keyboard Controller L: Disable internal KBC

H: Enable internal KBC (Default)

SDCS1# AC23 Eliminate External LAN

EEPROM

Strap Pins for North Bridge Configuration

SDCS3# AD23 NB Configuration SDCS3# signal state is reflected on signal pin

SDA2 AF23 NB Configuration SDA2 signal state is reflected on signal pin

SDA1 AC22 NB Configuration SDA1 signal state is reflected on signal pin

SDA0 AE23 NB Configuration SDA0 signal states is reflected on signal pins

SA19 AC11 NB Configuration SA19 signal state is reflected on signal pin VD[3]

SA18 AD11 NB Configuration SA18 signal state is reflected on signal pin VD[2]

SA17 AE11 NB Configuration SA17 signal state is reflected on signal pin,

SA16 AF11 NB Configuration SA16 signal state is reflected on signal pin,

L: Enable. Use external EEPROM (Default) H: Disable. Do not use external EEPROM

VD[7] during power up for North Bridge configuration.

VD[6] during power up for North Bridge configuration.

VD[5] during power up for North Bridge configuration.

VD[4] during power up for North Bridge configuration.

during power up for North Bridge configuration.

VD[1] during power up for North Bridge configuration.

VD[0] during power up for North Bridge configuration.

Check the North Bridge DS for details Check the North Bridge DS for details Check the North Bridge DS for details Check the North Bridge DS for details Check the North Bridge DS for details Check the North Bridge DS for details Check the North Bridge DS for details Check the North Bridge DS for details

Summary of Internal Pull-Up / Pull-Down Resistor Implementation Internal Pullups are present on pins KBCK, KBDT, MSCK, MSDT, SERIRQ, LAD[3:0], SDCS1# Internal Pulldowns are present on pins SA[19-16] and all LAN pins

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VT8235M Version CD V-Link South Bridge

REGISTERS

The following tables summarize the configuration and I/O registers of the VT8235M Version CD. These tables also document the power-on default value (“Default”) and access type (“Acc”) for each register. Access type definitions used are RW (Read/Write), RO (Read/Only), “—” for reserved / used (essentially the same as RO), and RWC (or just WC) (Read / Write 1’s to Clear individual bits). Registers indicated as RW may have some read/only bits that always read back a fixed value (usually 0 if unused); registers designated as RWC or WC may have some read-only or read write bits (see individual register descriptions for details).

Detailed register descriptions are provided in the following section of this document. All offset and default values are shown in hexadecimal unless otherwise indicated

Table 3. Memory Mapped Registers

FEC00000 APIC Index (8-bit) FEC00010 APIC Data (32-bit) FEC00020 APIC IRQ Pin Assertion (8-bit) FEC00040 APIC EOI (8-bit)

“APIC” = “Advanced Programmable Interrupt Controller”

Table 5. System I/O Map

Port Function Actual Port Decoding

00-1F Master DMA Controller 0000 0000 000x nnnn 20-3F Master Interrupt Controller 0000 0000 001x xxxn 40-5F Timer / Counter 0000 0000 010x xxnn 60-6F Keyboard Controller 0000 0000 0110 xnxn (60h) KBC Data 0000 0000 0110 x0x0 (61h) Misc Functions & Spkr Ctrl 0000 0000 0110 xxx1 (64h) KBC Command / Status 0000 0000 0110 x1x0 70-77 RTC/CMOS/NMI-Disable 0000 0000 0111 0nnn 78-7F -available for system use- 0000 0000 0111 1xxx 80 -reserved- (debug port) 0000 0000 1000 0000 81-8F DMA Page Registers 0000 0000 1000 nnnn 90-91 -available for system use- 0000 0000 1001 000x 92 System Control 0000 0000 1001 0010 93-9F -available for system use- 0000 0000 1001 nnnn A0-BF Slave Interrupt Controller 0000 0000 101x xxxn C0-DF Slave DMA Controller 0000 0000 110n nnnx E0-FF -available for system use- 0000 0000 111x xxxx

100-CF7 -available for system use*

CF8-CFB PCI Configuration Address 0000 1100 1111 10xx CFC-CFF PCI Configuration Data 0000 1100 1111 11xx

D00-FFFF -available for system use-

Table 4. Function Summary

Bus Device Func Device ID Function

0 16 (10h) 0 3038h USB 1.1 UHCI Ports 0-1 0 16 (10h) 1 3038h USB 1.1 UHCI Ports 2-3 0 16 (10h) 2 3038h USB 1.1 UHCI Ports 4-5 0 16 (10h) 3 3104h USB 2.0 EHCI Ports 0-5

0 17 (11h) 0 3074h Bus Control & Power Mgmt 0 17 (11h) 1 0571h IDE Controller 0 17 (11h) 5 3059h AC97 Audio Codec Controller 0 17 (11h) 6 3068h MC97 Modem Codec Ctrlr

0 18 (12h) 0 3065h VIA LAN Controller

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VT8235M Version CD V-Link South Bridge

Table 6. Registers

Legacy I/O Registers

Master DMA Controller Registers Default Acc

Port

00 Channel 0 Base & Current Address RW 01 Channel 0 Base & Current Count RW 02 Channel 1 Base & Current Address RW 03 Channel 1 Base & Current Count RW 04 Channel 2 Base & Current Address RW 05 Channel 2 Base & Current Count RW 06 Channel 3 Base & Current Address RW 07 Channel 3 Base & Current Count RW 08 Status / Command RW

09 Write Request 0A Write Single Mask 0B Write Mode 0C Clear Byte Pointer FF 0D Master Clear

0E Clear Mask

0F Read / Write Mask RW

Port

Master Interrupt Controller Regs Default Acc

20 Master Interrupt Control — *

21 Master Interrupt Mask — *

20 Master Interrupt Control Shadow —

21 Master Interrupt Mask Shadow —

* RW if shadow registers are disabled

Port

Timer/Counter Registers Default Acc

40 Timer / Counter 0 Count RW

41 Timer / Counter 1 Count RW

42 Timer / Counter 2 Count RW

43 Timer / Counter Control

Port

Keyboard Controller Registers Default Acc

60 Keyboard Controller Data RW

61 Misc Functions & Speaker Control RW

64 Keyboard Ctrlr Command / Status RW

Port

CMOS / RTC / NMI Registers Default Acc

70 CMOS Memory Address & NMI Disa

71 CMOS Memory Data (128 bytes) RW

74 CMOS Memory Address

75 CMOS Memory Data (256 bytes) RW

NMI Disable is port 70h (CMOS Memory Address) bit-7. RTC control occurs via specific CMOS data locations (0-Dh). Ports 74-75 may be used to access CMOS if the internal RTC is disabled.

WO WO WO WO WO WO

RW RW

Legacy I/O Registers (continued)

DMA Page Registers Default Acc

Port

87 DMA Page – DMA Channel 0 RW 83 DMA Page – DMA Channel 1 RW 81 DMA Page – DMA Channel 2 RW

82 DMA Page – DMA Channel 3 RW 8F DMA Page – DMA Channel 4 RW 8B DMA Page – DMA Channel 5 RW

89 DMA Page – DMA Channel 6 RW 8A DMA Page – DMA Channel 7 RW

Port

System Control Registers Default Acc

92 System Control RW

Port

Slave Interrupt Controller Regs Default Acc

A0 Slave Interrupt Control — * A1 Slave Interrupt Mask — * A0 Slave Interrupt Control Shadow — A1 Slave Interrupt Mask Shadow —

* RW accessible if shadow registers are disabled

Port

Slave DMA Controller Registers Default Acc

C0 Channel 0 Base & Current Address RW C2 Channel 0 Base & Current Count RW C4 Channel 1 Base & Current Address RW C6 Channel 1 Base & Current Count RW C8 Channel 2 Base & Current Address RW

CA Channel 2 Base & Current Count RW CC Channel 3 Base & Current Address RW CE Channel 3 Base & Current Count RW

D0 Status / Command RW D2 Write Request D4 Write Single Mask D6 Write Mode D8 Clear Byte Pointer FF

DA Master Clear DC Clear Mask DE Read / Write Mask RW

WO WO WO WO WO WO

RW RW

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