VIA VT8231 Datasheet

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EVISION HISTORY

Document Release Date Revision Initials

Revision 0.4 9/17/99 Initial release based on 82C686A “Super South” Data Sheet revision 1.42

Updated feature bullets, document title, and block diagram Replaced pinout diagram with blank BGA352 template Added LAN, LPC, and EEPROM pin descriptions, removed signals as req’d

Updated Functions 5 and 6 per engineering input Revision 0.5 9/27/99 Added Preliminary Ballout & Mechanical Spec DH Revision 0.6 10/1/99 Updated pin descriptions and pin lists DH Revision 0.7 10/15/99 Updated pinouts to conform to engineering pinout revision 0.4 dated 10/6/99 DH Revision 0.8 10/29/99 Updated feature bullets and performed partial edit of Overview text

Updated pinouts per engineering pinout rev 0.6 / pinlist rev 0.2 dated 10/20/99

Updated Electrical Specs and added “output drive” and “input voltage” tables

VT8231

Preliminary Revision 0.8 October 29, 1999 -i- Revision History

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ABLE OF CONTENTS

VT8231

REVISION HISTORY........................................................................................................................................................................I

TABLE OF CONTENTS..................................................................................................................................................................II

LIST OF FIGURES..........................................................................................................................................................................IV

LIST OF TABLES...........................................................................................................................................................................IV

OVERVIEW.......................................................................................................................................................................................5

PINOUTS............................................................................................................................................................................................7

IN DIAGRAM

.................................................................................................................................................................................7

IN LISTS

IN DESCRIPTIONS

........................................................................................................................................................................................8

.......................................................................................................................................................................10

REGISTERS.....................................................................................................................................................................................29

EGISTER OVERVIEW

EGISTER DESCRIPTIONS

.................................................................................................................................................................29

............................................................................................................................................................41

Legacy I/O Ports...................................................................................................................................................................41

Keyboard Controller Registers.............................................................................................................................................................. 42

DMA Controller I/O Registers.............................................................................................................................................................. 44

Interrupt Controller Registers ............................................................................................................................................................... 45

Timer / Counter Registers..................................................................................................................................................................... 45

CMOS / RTC Registers......................................................................................................................................................................... 46

Super-I/O Configuration Index / Data Registers...............................................................................................................47

Super-I/O Configuration Registers.....................................................................................................................................47

Super-I/O I/O Ports..............................................................................................................................................................50

Floppy Disk Controller Registers.......................................................................................................................................................... 50

Parallel Port Registers........................................................................................................ ................................................................... 51

Serial Port 1 Registers........................................................................................................................................................................... 52

Serial Port 2 Registers........................................................................................................................................................................... 53

SoundBlaster Pro Port Registers.........................................................................................................................................54

FM Registers......................................................................................................................................................................................... 54

Mixer Registers .....................................................................................................................................................................................54

Sound Processor Registers ....................................................................................................................................................................54

Game Port Registers............................................................................................................................................................. 55

PCI Configuration Space I/O...............................................................................................................................................56

Function 0 Registers - PCI to ISA Bridge...........................................................................................................................57

PCI Configuration Space Header.......................................................................................................................................................... 57

ISA Bus Control.................................................................................................................................................................................... 57

Plug and Play Control........................................................................................................................................................................... 61

Distributed DMA / Serial IRQ Control.................................................................................................................................................63

Miscellaneous / General Purpose I/O.................................................................................................................................................... 64

Function 1 Registers - Enhanced IDE Controller..............................................................................................................69

PCI Configuration Space Header.......................................................................................................................................................... 69

IDE-Controller-Specific Confiiguration Registers................................................................................................................................ 71

IDE I/O Registers.................................................................................................................................................................................. 76

Function 2 Registers - USB Controller Ports 0-1...............................................................................................................77

PCI Configuration Space Header.......................................................................................................................................................... 77

USB-Specific Configuration Registers..................................................................................................................................................78

USB I/O Registers................................................................................................................................................................................. 79

Function 3 Registers - USB Controller Ports 2-3...............................................................................................................80

PCI Configuration Space Header.......................................................................................................................................................... 80

USB-Specific Configuration Registers..................................................................................................................................................81

USB I/O Registers................................................................................................................................................................................. 82

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VT8231

Function 4 Regs - Power Management, SMBus and HWM..............................................................................................83

PCI Configuration Space Header.......................................................................................................................................................... 83

Power Management-Specific PCI Configuration Registers .................................................................................................................. 84

Hardware-Monitor-Specific Configuration Registers ........................................................................................................................... 91

System Management Bus-Specific Configuration Registers................................................................................................................. 91

Power Management I/O-Space Registers ..............................................................................................................................................92

System Management Bus I/O-Space Registers.................................................................................................................................... 101

Hardware Monitor I/O Space Registers .............................................................................................................................................. 104

Function 5 & 6 Registers - AC97 Audio & Modem Codecs............................................................................................108

PCI Configuration Space Header – Function 5 Audio........................................................................................................................ 108

PCI Configuration Space Header – Function 6 Modem...................................................................................................................... 109

Function 5 & 6 Codec-Specific Configuration Registers....................................................................................................................110

Function 5 I/O Base 0 Regs – DXSn Scatter/Gather DMA................................................................................................................. 112

Function 5 I/O Base 1 Registers –Audio FM NMI Status................................................................................................................... 117

Function 5 I/O Base 2 Registers –MIDI / Game Port.......................................................................................................................... 117

Function 6 I/O Base 0 Regs –Modem Scatter/Gather DMA............................................................................................................... 118

FUNCTIONAL DESCRIPTIONS................................................................................................................................................120

OWER MANAGEMENT

Power Management Subsystem Overview.......................................................................................................................................... 120

Processor Bus States........................................................................................................................................................................... 120

System Suspend States and Power Plane Control............................................................................................................................... 121

General Purpose I/O Ports...................................................................................................................................................................121

Power Management Events................................................................................................................................................................. 122

System and Processor Resume Events................................................................................................................................................ 122

Legacy Power Management Timers.................................................................................................................................................... 123

System Primary and Secondary Events............................................................................................................................................... 123

Peripheral Events................................................................................................................................................................................ 123

..............................................................................................................................................................120

ELECTRICAL SPECIFICATIONS.............................................................................................................................................124

BSOLUTE MAXIMUM RATINGS

HARACTERISTICS

DC C

UTPUT DRIVE

NPUT VOLTAGE

..........................................................................................................................................................................125

..............................................................................................................................................................124

........................................................................................................................................................................125

...............................................................................................................................................124

PACKAGE MECHANICAL SPECIFICATIONS......................................................................................................................126

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IST OF FIGURES

FIGURE 1. PC SYSTEM CONFIGURATION USING THE VT8231......................................................................................... 6

FIGURE 2. VT8231 BALL DIAGRAM (TOP VIEW) .................................................................................................................. 7

FIGURE 3. VT8231 PIN LIST (NUMERICAL ORDER)............................................................................................................. 8

FIGURE 4. VT8231 PIN LIST (ALPHABETICAL ORDER)......................................................................................................9

FIGURE 5. STRAP OPTION CIRCUIT.......................................................................................................................................62

FIGURE 6. POWER MANAGEMENT SUBSYSTEM BLOCK DIAGRAM.........................................................................120

FIGURE 8. MECHANICAL SPECIFICATIONS – 376 PIN BALL GRID ARRAY PACKAGE.........................................126

IST OF TABLES

TABLE 1. PIN DESCRIPTIONS...................................................................................................................................................10

TABLE 2. SYSTEM I/O MAP.......................................................................................................................................................29

TABLE 3. REGISTERS..................................................................................................................................................................30

TABLE 4. KEYBOARD CONTROLLER COMMAND CODES ..............................................................................................43

TABLE 5. CMOS REGISTER SUMMARY.................................................................................................................................46

VT8231

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VT8231

SOUTH BRIDGE

PC99 COMPLIANT

INTEGRATED SUPER-I/O (FDC, LPT, COM, AND FIR),

NTEGRATED FAST ETHERNET, LPC, ISA / LPC BIOS ROM,

NTEGRATED SOUNDBLASTER PRO / MULTICHANNEL

DIRECT SOUND AC97 AUDIO AND MC97 MODEM INTERFACE,

LTRADMA-33/66/100 MASTER MODE EIDE CONTROLLER,

ORT USB CONTROLLER, KEYBOARD CONTROLLER, RTC,

4 P

ERIAL IRQ, SMBUS, SERIAL EEPROM,

LUG AND PLAY, ACPI, ENHANCED POWER MANAGEMENT,

EMPERATURE, VOLTAGE, AND FAN-SPEED MONITORING

VT8231

• Inter-operable with VIA and other Host-to-PCI Bridges

−

Combine with VT82C598 for a complete Super-7 (66 / 75 / 83 / 100MHz) AGP 2x system (Apollo MVP3)

−

Combine with VT8501 for a complete Super-7 system with integrated 2D / 3D graphics (Apollo MVP4)

−

Combine with VT82C694X for a complete 66 / 100 / 133 MHz Socket370 / Slot1 AGP 4x system (Apollo Pro133A)

−

Combine with VT8601 for a complete 66 / 100 / 133 MHz Socket370 / Slot1 system with integrated 2D / 3D graphics (Apollo ProMedia)

−

Inter-operable with Intel or other Host-to-PCI bridges for a complete PC99 compliant PCI / AGP / LPC system

• Integrated Peripheral Controllers

−

Integrated Fast Ethernet Controller with 1 / 10 / 100 Mbit capability

−

Integrated USB Controller with two root hub and four function ports

−

Dual channel UltraDMA-33 / 66 /100 master mode EIDE controller

−

AC-link interface for AC-97 audio codec and modem codec

−

HSP modem support

−

Interface for optional external modem DSP

−

Integrated SoundBlasterPro / DirectSound compatible digital audio controller

−

LPC interface for Low Pin Count interface to Super-I/O or ROM

• Integrated Legacy Functions

−

Integrated Keyboard Controller with PS2 mouse support

−

Integrated DS12885-style Real Time Clock with extended 256 byte CMOS RAM and Day/Month Alarm for ACPI

−

Integrated Bus Controller including DMA, timer, and interrupt controller

−

Serial IRQ for docking and non-do cking applications

−

Flash EPROM, 32Mbit (4Mbyte) EPROM and combined BIOS support

−

Fast reset and Gate A20 operation

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• Fast Ethernet Controller

−

High performance PCI master interface with scatter / gather and bursting capability

−

Standard MII interface to PHYceiver

−

1 / 10 / 100 MHz full and half duplex operation

−

Transmit data buffer byte alignment for low CPU utilization

−

Separate 2K byte FIFOs for receive and transmit of full Ethernet packets

−

Flexible dynamically loadable EEPROM algorithm

−

Physical, Broadcast, and Multicast address filtering using hashing function

−

Flexible wakeup events: link status change, magic packet, unicast physical address match, predefined pattern match

−

Software controllable power down

• UltraDMA-33 / 66 / 100 Master Mode PCI EIDE Controller

−

Dual channel master mode PCI supporting four Enhanced IDE devices

−

Transfer rate up to 100MB/sec to cover up to PIO mode 4, multi-word DMA mode 2, and UltraDMA mode 5

−

Thirty-two levels (doublewords) of prefetch and write buffers per channel

−

Dual DMA engine for concurrent dual channel operatio n

−

Bus master programming interface for SFF-8038i rev.1.0 and Windows-95 / 98 / 2000 compliant

−

Full scatter gather capability

−

Support ATAPI compliant devices including DVD devices

−

Support PCI native and ATA compatibility modes

−

Complete software driver support

VT8231

• Integrated Super IO Controller

−

Supports 2 serial ports, IR port, parallel port, and floppy disk controller functions

−

Two UARTs for Complete Serial Ports Programmable character lengths (5,6,7,8) Even, odd, stick or no parity bit generation and detection Programmable baud rate generator High speed baud rate (230Kbps, 460Kbps) support Independent transmit/receiver FIFOs Modem Control Plug and play with 96 base IO address and 12 IRQ options

−

Fast IR (FIR) port IrDA 1.0 SIR and IrDA 1.1 FIR compliant IR function through the second serial port Infrared-IrDA (HPSIR) and ASK (Amplitude Shift Keyed) IR

−

Multi-mode parallel port Standard mode, ECP and EPP support Dynamic and static switch between parallel port pinout and FDC pinout Plug and play with 192 base IO address, 12 IRQ and 4 DMA options

−

Floppy Disk Controller 16 bytes of FIFO Data rates up to 1Mbps Perpendicular recording driver support Two FDDs with drive swap support Plug and play with 48 base IO address, 12 IRQ and 4 DMA options

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• SoundBlaster Pro Hardware and Direct Sound Ready AC97 Digital Audio Controller

−

Up to six concurrent AC97 output channels for six-speaker surround sound experience

−

Multiple Direct Sound channels between system memory and AC97 link 10 Direct Sound output channels 4 Direct Sound input channels 8-channel hardware sample-rate-converter / mixer 1 Surround Sound channel of up to six data st reams

−

PCI bus master interface with scatter / gather and bursting capability

−

32 byte FIFO for each direct sound channel

−

Host based wave table synthesis

−

Standard v1.03 or v2.1 AC97 Codec interface with up to four AC97 codec’s from multiple vendors

−

Loopback capability for re-directing mixed audio streams into USB and 1394 speakers

−

Hardware SoundBlaster Pro for legacy compatibility

−

Plug and play with 4 IRQ, 4 DMA, and 4 I/O space options for SoundBlaster Pro and MIDI hardware

−

Hardware assisted FM synthesis for legacy compatibility

−

Direct two game ports and one MIDI port interface

−

Complete software driver support for Windows-95 / 98 / 2000 and Windows-NT

• MC97 HSP Modem Controller

−

PCI bus master interface with scatter / gather and burst capability

−

Standard AC97 codec interface for MC or AMC codec

−

Wake on ring in APM or ACPI mode through AC97 link

−

Supported by most HSP modem vendors

VT8231

• Universal Serial Bus Controller

−

USB v.1.1 and Intel Universal HCI v.1.1 compatible

−

Eighteen level (doublewords) data FIFO with full scatter and gather capability

−

Root hub and four function ports

−

Integrated physical layer transceivers with optional over-current detection status on USB inputs

−

Legacy keyboard and PS/2 mouse support

• System Management Bus Interface

−

One master / slave SMBus and one slave-only SMBus

−

Host interface for processor communications

−

Slave interface for external SMBus masters

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• Voltage, Temperature, Fan Speed Monitor and Controller

−

Five universal input channels for voltage or temperature sensing

−

Two fan-speed moni toring channels

−

Input channel for thermal diode in Intel™ high speed Pentium II™ / Pentium III™ CPUs

−

Programmable control, status, monitor and alarm for flexible desktop management

−

External thermister or internal bandgap temperature sensing

−

Automatic clock throttling with integrated temperature sensing

−

Internal core VCC voltage sensing

−

Flexible external voltage sensing arrangement (any positive supply and battery)

• Sophisticated PC99-Compatible Mobile Power Management

−

Supports both ACPI (Advanced Configuration and Power Interface) and legacy (APM) power management

−

ACPI v1.0 Compliant

−

APM v1.2 Compli ant

−

CPU clock throttling and clock stop control for complete ACPI C0 to C3 state support

−

PCI bus cloc k run, Power Management Enable (PME) control, and PCI/CPU c lock generator stop control

−

Supports multiple system suspend types: power-on suspends with flexible CPU/PCI bus reset options, suspend to DRAM, and suspend to disk (soft-off), all with hardware automatic wake-up

−

Multiple suspend power plane controls and suspend status indicators

−

One idle timer, one peripheral timer and one general purpose timer, plus 24/32-bit ACPI compliant timer

−

Normal, doze, sleep, suspend and conserve modes

−

Global and local device power control

−

System event monitoring with two event classes

−

Primary and secondary interrupt differentiation for individual channels

−

Dedicated input pins for power and sleep buttons, external modem ring indicator, and notebook lid open/close for system wake-up

−

Multiple internal and external SMI sources for flexible power management models

−

One programmable chip select and one microcontroller chip select

−

Enhanced integrated real time clock (RTC) with date alarm, month alarm, and century field

−

Thermal alarm on either external or any combination of three internal temperature sensing circuits

−

Hot docking support

−

I/O pad leakage control

VT8231

• Plug and Play Controller

−

PCI interrupts steerable to any interrupt channel

−

Steerable interrupts for integrated peripheral controllers: USB, floppy, serial, parallel, audio, soundblaster, MIDI

−

Steerable DMA channels for integrated floppy, parallel, and soundblaster pro controllers

−

One additional steerable interrupt channel for on-board plug and play devices

−

Microsoft Windows 2000TM, Windows 98SETM, Windows 98TM, Windows NTTM, Windows 95 BIOS compliant

and plug and play

• Built-in NAND-tree pin scan test capability

• 0.30um, 3.3V, low power CMOS process

• Single chip 27x27 mm, 376 pin BGA

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VERVIEW

The VT8231 South Bridge is a high integration, high performance, power-efficient, and high compatibility device that supports Intel, AMD, and VIA / Cyrix based processor to PCI bus bridge functionality to make a complete Microsoft PC99-compliant PCI / LPC system. The VT8231 includes standard intelligent peripheral controllers:

a) Master mode enhanced IDE controller with dual channel DMA engine and interlaced dual channel commands. Dedicated

FIFO coupled with scatter and gather master mode operation allows high performance transfers between PCI and IDE devices. In addition to standard PIO and DMA mode operation, the VT8231 also supports the UltraDMA-33, 66, and 100 standards to allow reliable data transfer rates up to 100 MB/sec throughput. The IDE controller is SFF-8038i v1.0 and Microsoft Windows-family compliant.

b) Integrated LAN Fast Ethernet controller (MAC) with Media Independent Interface (MII) to external PHY. The LAN

controller operates at 1 / 10 / 100 Mbit/sec transfer rates using either full and half duplex operation and has separate 2Kbyte FIFOs for receive and transmit of full ethernet packets. The internal high-performance PCI interface has scatter / gather and bursting capability and can align bytes in the transmit data buffer to reduce CPU utilization. The LAN interface can perform address filtering on physical, broadcast, and multicast packets. The interface can also be configured for system wake up on link status change, receipt of magic packet, unicast physical address match on incoming packets, and predefined pattern

match in the incoming data. c) LPC (Low Pin Count) interface for BIOS ROM plus optional conventional BIOS ROM support d) Universal Serial Bus controller that is USB v1.1 and Universal HCI v1.1 compliant. The VT8231 includes the root hub with

four function ports with integrated physical layer transceivers. The USB controller allows hot plug and play and isochronous

peripherals to be inserted into the system with universal driver support. The controller also implements legacy keyboard and

mouse support so that legacy software can run transparently in a non-USB-aware operating system environment. e) Keyboard controller with PS2 mouse support f) Real Time Clock with 256 byte extended CMOS. In addition to standard RTC functionality, the integrated RTC also includes

the date alarm, century field, and other enhancements for compatibility with the ACPI standard. g) Notebook-class power management functionality compliant with ACPI and legacy APM requirements. Multiple sleep states

(power-on suspend, suspend-to-DRAM, and suspend-to-Disk) are supported with hardware automatic wake-up. Additional

functionality includes event monitoring, CPU clock throttling and stop (Intel processor protocol), PCI b us clock sto p co ntrol,

modular power, clock and leakage control, hardware-based and software-based event handling, general purpose I/O, chip

select and external SMI. h) Hardware monitoring subsystem for managing system / motherb oard voltage level s , temperatures, and fa n speeds i) Full System Management Bus (SMBus) interface with one master / slave port and one slave-only port j) 16550-compatible serial I/O port with “Fast-IR” infrared communications port option. k) Integrated PCI-mastering dual full-duplex direct-sound AC97-link-compatible sound system. Hardware soundblaster-pro and

hardware-assisted FM blocks are included for Windows DOS box and real-mode DOS compatibility. Loopback capability is

also implemented for directing mixed audio streams into USB and 1394 speakers for high quality digital audio. l) Game port and MIDI port m) Standard floppy disk drive interface n) ECP/EPP-capable parallel port with floppy disk controller pinout option o) Serial IRQ for docking and non-docking applications p) Plug and Play controller that allows complete steerability of all PCI interrupts and internal interrupts to any interrupt channel.

One additional steerable interrupt channel is provided to allow plug and play and reconfigurability of on-board peripherals for

Windows family compliance.

VT8231

Preliminary Revision 0.8 October 29, 1999 -5- Overview

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VT8231

CPU / Cache

Sideband Signals:

Init / CPUre s et

IRQ / NMI

SMI / StopClk

FERR / IGNNE

SLP# (Slot-1)

Boot ROM

Onboard LPC I/O

LPC

RTC Crystal

CA CD

North Bridge

VT8231

376 BGA

MA/Command

PCI

SMB USB Ports 0-3

Keyboard / Mouse MIDI / Game Ports Parallel Port Serial Ports 1 and 2 Infrared Comm Port IDE Primary and Secondary Floppy Disk Interface AC97 Lin k Hardware Monitor Inputs GPIO, Power Cont rol, Reset Fast Ethernet Interface

Figure 1. PC System Configuration Using the VT8231

System Memory

DIMM Module ID

Expansion

Cards

Preliminary Revision 0.8 October 29, 1999 -6- Overview

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INOUTS

VT8231

Pin Diagram

Figure 2. VT8231 Ball Diagram (Top View)

Key1234567891011121314151617181920

AD30AD31AD26AD24AD21AD16DEV

PINTB#PINTA#AD28AD25AD23AD18T

PREQH#PINTD#PINTC#AD27CBE3#AD19I

PGNTL#PREQL#PGNTH#AD29AD20CBE2#STOP#AD14AD7AD2PD0SLCT

RTCX2RTCX1PWRGDPCI

JBB1V

K VREF

BAT

SYNCACRSTJAB1

SDIN0ACSDIN1ACSDOJBB2JAY

PCS1#

GPIOCAC

SDIN2

FAN1FAN2

UIC5DTD+DTD-UIC

UIC1UIC3UIC2KB

KBDTMSCKSUSC#MSDTSUS

SUSA

SUSB#AOL

#/strap

SMB

CK2

DT2

SMB

ALRT#

DT1

PWR

PME#

BTN#

PCK

GPIOAGPI1WSC#

RUN#

PCI

CPU

STP#

GPIO

LID

RST#AD22AD17

INTR

GPI0RSM

UDR#

MSI

I2SJAX

MSO

BCLK

SPDIFJBY

SLPB#JAB2JBX

SUS

GPI

CLK

SMB

GPO0CPU

CK1

BAT

EXT

LOW#

SMI#

RING#CPU

RST

ARQ#

GPIOEAPICD0A20M#MCCS

APIC

CLK

FRM#

RST#

VCC GND VCC VCC VCC GND VCC

VCC H7 8 9 10 11 12 13 H14 GND

VCC J GND GND GND GND GND GND J VCC

GND K GND GND GND GND GND GND K VCC

GND

VCC L GND GND GND GND GND GND L GND

HWM

VCC

VCC M GND GND GND GND GND GND M VCC

HWM

VCC N7 8 9 10 11 12 13 N14 GND

ST#

VCC

SUS

INTR

MISS

IGN

NMI

NE#IOW#IRRX2

FERR

SLP#

STP

INIT

CLK#LAD3LAD0

#/strapLAD2LFRM# PCS0#

SMI#

/strapLAD1LDRQ#

CBE1#AD9AD

SEL#

RDY#AD15AD10AD4

AD12AD6AD0PD1PD4PD7USB

PAR

RDY#

SERR#AD13AD8AD3AUTO

VCC

GND VCC VCC GND VCC VCC VCC GND VCC

VCC

IOR#IR

VCC

VCC VCC

ROM

CS#

SPKR

SER IRQ

MEMR#SD14

MEMW#SD13

CBE

SD11

HG2#

SD12

LR1#

SD15

LG2#

LR2#

LG1#

STR#

ERR#

SD10

HR2#

HG1#

HR1#

PD2PD

AD1P

INIT#PD5

IN#

FD#PD3

VCC VCC

SD6SD

OSC

SD5SD4SA18IRQ15SA7

SD1SA19SA5

SD9

SD2LA20SA9

SD8

SD3LA21SA16

BUSY RTS# DTR#

ACK# TXD CTS#

CLK

PE DSR#

SLCT RXD

GND

RAM

VCC VCC VCC

SA17 /strap

GND

USB

VCC

USB

DCD#

VCC VCC

GND

RAM

IRQ14SA8

SDD8PDD0PDD15PDD13PDD3PDD12

SDD7

SA11

SDD11

SDD5

SA4

SDD9

SDD4

SA10

/strap

SDD10

USB

OC0#

USB

P3-

USB

RI#

P3+EECS#EEDIEEDO

USB

OC1#MDCKMDIO

EECKMRX

CLK

MTX

VCC

CLK

MII

CRSMCOL

TRK

WRT

00#

PRT#

MTR1#DS

VCC

GND

SDD6SDDRQ

SDD2

SA12

SDD12

SDD3

DRV

DEN1

MII

DRV

DEN0

PLL

PCI

CLKPDA1PDA0PDA2

PLL

D10PDD5PDIOR#PDRDY

PDD4PD

D11PDD8PDDRQPDIOW#

PDD1PD

D14PDD7PDD9PDD6

SA6

SA2

SA14

SDD14SDA1SDA0SDA2

SA1

SDD1

SDD15SDIOR#

SA3

SA13

SDD13

USB

P2-

USB

P2+

P1+

MRXD3MRX

MRXD1MRXD0MRX

MRX

MTX

ERR

ENA

MTXD1MTXD2MTX

DSK

CHG#HDSEL#

STEP#

DATA#WGATE#

MTR0#DS

PDCS1#PDCS3#IN

SDCS1#SDCS3#PD

SA15

SA0

SDD0SDIOW#SDRDY

P1-

USB

P0-

USB

P0+

MTX

DATA#

DIR#

DEX#

DACK#

Note: Some of the pins above have alternate functions and alternate names. The table above contains only one name (usually the most often used function), but the pin lists and pin descriptions contain all names.

Preliminary Revision 0.8 October 29, 1999 -7- Pinouts

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VT8231

Pin Lists

Figure 3. VT8231 Pin List (Numerical Order)

Pin Pin Name Pin Pin Name Pin Pin Name Pin Pin Name Pin Pin Name

A01 IO AD30 D12 IO SLCTIN#/STEP# H03 O ACSDOUT P02 O SUSB# / GPIO2 U13 IO SA18 A02 IO AD31 D1 3 I PE / WDATA# H04 I JBB2 / GAMED7 P03 I AOLGPI/THRM/I17 U14 I IRQ15 A03 IO AD26 D14 I DSR# H05 I JAY / GAMED1 P04 O SUSCLK / GP O4 U15 IO SA07 / SDD07 A04 IO AD24 A05 IO AD21 D16 I USBOC1# A06 IO AD16 D17 O MDCK H16 I TRK00# A07 IODEVSEL# D18 IOMDIO H17 I WRTPRT# A08 IO CBE1# D19 I MRXD3 H18 I DSKCHG#

D15 P GNDUSB H06 P VCC P05 P VCCSUS

H15 P GND P06 P VCCSUS

P07 P GND P08 P VCC P09 P VCC

U16 IO SA06 / SDD06 U17 I SDDR U18 O SDCS1# U19 O SDCS3# U20 IO PDD02

A12 IO PD2 / WRTPRT# E03 I P WRGD J02 IO GPIOC/IO25/ATST A13 IO PD6 E04 O PCIRST# J03 I ACBITCLK A14 I BUSY / MTR1# E05 IO AD22 J04 O MSO / SPDIF A15 O RTS# E06 IO AD17 J05 I JBY / GAMED3 P16 IO PDD0 4 V07 IO LAD3 A16 O DTR# E07 I SERR# A17 I USBOC0# E08 IO AD13 A18 IO USBP2- E09 IO AD08 J16 OD MTR1# P19 I PDDR A19 IO USBP1- E10 IO AD03 J17 OD DS0# P20 O PDIOW# V11 I HRQ2#/SD10/I11

B02 I PINTA# E13 I SLCT/WGATE# J20 OD WGATE# R03 IO SMBCK1 V14 IO SA05 / SDD05 B04 IO AD25

B05 IO AD23 E16 O EECK K03 I FAN2/SLPB#/IO18 R06 OD INTR V17 IO SA14 / SDD14 B06 IO AD18 E17 I MRXCLK / AIRQK04 I JAB2 / GAMED5 B07 IO TRDY# E18 I MRXD1 K05 I JBX / GAMED2 R08 O IRTX / GPO14 V19 O SDA0 B08 IO AD15 E19 I MRXD0 / AIR

B11 IO AD01 B12 IO PINIT# / DIR# F03 I INTRUDER#/GPI8 K18 OD MTR0# B13 IO PD5 F04 I GPI0 K19 OD DS1# B14 I ACK# / DS1# F05 I RSMRST# K20 OD DIR#

B16 I CTS# B17 IO USBP3- F08 IO AD11 L03 AI DTD- R18 IO PDD07 W09 IO MEMR# B18 IO USBP2+ B19 IO USBP1+ F10 IO CBE0#

C02 I PINTD# C03 I PINTC# F14 I DCD# L17 OD DRVDEN0 T04 IOD EXTSMI# / GPI2 W15 IO SA04 / SDD04 C04 IO AD27 C05 IO CBE3# F16 I MTXCLK / AIRQL19 O PDCS3# T06 OD IGNNE# W17 IO SA01 / SDD01 C06 IO AD19

C08 IO PAR F19 O MTXENA / AIRQM02 AI UIC3 T09 O ROMCS#/KBCS# W20 O SDDACK#

E15 P VCCUSB

F02 P VBAT

F07 P VCC F09 P VCC

F13 P VCC L16 P VCCPLL F15 P VCC F16 P VCCMII

06 P VCC 15 P VCC

K02 I FAN1 R05 I CPUMISS / GPI16 V16 IO SA02 / SDD02

K06 P GND R09 P VCC

K17 OD DRVDEN1 R12 IO SD00 W03 IO GPIOE / GPIO31

L02 AI DTD+ R17 IO PDD14 W08 O LFRAME# L04 AI UIC4 R19 IO PDD09 W10 I LRQ2#/SD14/I13

L05 P GNDHWM

L18 O PDCS1# T05 OD NMI W16 IO SA12 / SDD12 L20 I INDEX# T07 IO IOW# / GPO23 W18 IO SA15 / SDD15

P13 P VCC P14 P GND P15 P VCC

P17 IO PDD11 V08 IO LAD0 P18 IO PDD08 V09 I SERIR

R07 P VCC

R13 P VCC R14 P VCC R15 P VCC

R20 IO PDD06 W11 O HGT1#/SD09/O8

T03 I BATLOW# / GPI5 W14 IO SA09 / SDD09

V04 I WSC#/ARQ#/I24 V05 OD INIT V06 OD STPCLK#

V10 O LGT2#/SD15/O11

V18 O SDA1 V20 O SDA2

W04 O APD0/ACS#/IO28 W05 OD A20M# W06 O MCCS#/O17/stra

C11 IO AD00 G02 O ACRST C12 IO PD1 / TRK00# G03 I JAB1 / GAMED4 C13 IO PD4 / DSKCHG# G04 I MSI / I2S C14 IO PD7 G05 I JAX / GAMED0 C15 I USBCLK C16 I RI# C17 IO USBP3+ C18 O EECS#

D02 O PREQL# D03 I PGNTH# D04 IO AD29 D05 IO AD20 G16 I MCRS / AIR D06 IO CB E 2# G17 I MCOL / AIR D07 IO STOP# G18 O MTXD1 / AIR D08 IO AD14 G19 O MTXD2 / AIR

Center

pins (24 pins): J8-J13, K8-K13, L8-L13, M8-M13

GND

G06 P VCC G07 P GND G08 P VCC G09 P VCC

G13 P GNDRAM G14 P GND G15 P VCCRAM N06 P VCC

M05 P VCCHWM M06 P VCC M15 P VCC M16 P GNDPLL

M17 I PCICLK T16 IO PDD00 Y07 IO LAD1 M18 O PDA1 T17 IO PDD15 Y08 I LDRQ#/SIN3/I15 M19 O PDA0 T18 IO PDD13 Y09 IO MEMW# M20 O PDA2 T19 IO PDD03 Y10 O LG1#/ SD13/O10

N04 IO MSDT / IRQ12 U03 I RING# / GPI3 Y14 IO SA16 / stra N05 O SUSST1# / GPO3 U04 OD CPURST Y15 IO SA10 / SDD10

N15 P GND

N16 IO PDD10 U07 IO IOR# / GPO22 Y18 IO SA00 / SDD00 N17 IO PDD05 U08 I IRRX / GPO15 Y1 9 O SDIOW# N18 O PDIOR# U09 O SPKR Y20 I SDRDY

T12 I OSC Y03 I APICCLK / GPI9 T13 IO SA17 / stra T14 I IRQ14 Y05 OD SMI# T15 IO SA08 / SDD08 Y06 O PCS0#/O16/stra

U05 I FERR# Y16 IO SA03 / SDD03 U06 OD SLP# / GPO7 Y17 IO SA13 / SDD13

Y04 O APD1/AK#/IO29

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06IO

00E20

C16

06PGN

N15PGN

J04OMSO / S

ORTCX2C15IUSBC

0PGN

05PGNDHW

6PGN

G13PGN

5PGNDUS

VCC

09PVCC

VCC

5PVCC

G08PVCC

G10PVCC

06PVCC

J06PVCC

5PVCC

06PVCC

5PVCC

N06PVCC

G03IJ

V19OSDA0

CBE0

05IJ

U18OSDCS

VCC

J05IJ

W19OSDIO

3PVCC

VCC

W13IO

0/OC2#/O20

N16IO

V09IS

05PVCCHW

6PVCC

G15PVCC

05PVCCSUS

06PVCCSUS

5PVCCUS

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VT8231

Figure 4. VT8231 Pin List (Alphabetical Order)

PinPin Name PinPin Name PinPin Name PinPin Name PinPin Name

W05 OD A20M# F11 I ERROR#/HDSEL# D18 IO MDIO C03 I PINTC# P01 O SUSA# / GPO1

J03 I ACBITCLK T04 IOD EXTSMI# / GPI2 W09 IO MEMR# C02 I PINTD# P02 O SUSB# / GPO2

B14 I ACK# / DS1# K02 I FAN1 Y09 IO MEMW# U01 I PME# / GPI6 N03 O SUSC# G02 O ACRST K03 I FAN2/SLPB#/IO18 E17 I MRXCLK / AIRQC01 O PREQH# P04 O SUSCLK H01 I ACSDIN0 U05 I FERR # E19 I MRXD0 / AIRQD02 O PREQL# N05 O SUSST1# / GPO3 H02IACSDIN1F H03 O ACSDOUT G01 O ACSYNC

11 IOAD

B11 IO AD01 D10 IO AD02

E10 IO AD03

B10 IO AD04 A10IOAD

C10 IO AD06 D09 IO AD07

E09 IO AD08 A09 IO AD09

B09 IO AD10

F08 IO AD11

C09 IO AD12 F04 I GPI0 G20 O MTXD3/AIR

E08 IO AD13 V03 I GPI1 / IRQ8# F19 O MTXENA/AIRQV14 IO SA05 / SDD05 B18 IO USBP2+ D08 IO AD14 V02 IO GPIOA/24 T05 OD NMI U16 IO SA06 / SDD06 B17 IO USBP3-

B08 IO AD15 J02 IO GPIOC/25/ATST T12 I OSC U15 IO SA07 / SDD07 C17 IO USBP3+ A06 IO AD16 Y01 IO GPIOD/30/SCIOU# C08 IO PAR T15 IO SA08 / SDD0 8

E06 IO AD17 W03 IO GPIOE V01 IO PCKRUN# W14 IO SA09 / SDD09

B06 IO AD18 H19 OD HDSEL# M17 I PCICLK Y15 IO SA10 / SDD10

C06 IO AD19 W11 O HGNT1#/SD09/O8 E04 O PCIRST# V15 IO SA11 / SDD11 D05 IO AD20 T10 O HGNT2#/SD11/O9 W01 O PCISTP# / GPO6 W16 IO SA12 / SDD12 A05 IO AD21 Y11 I HREQ1#/SD08/I10 Y06 O PCS0#/O16/strapY17 IO SA13 / SDD13

E05 IO AD22 V11 I HREQ2#/SD10/I11 J01 O PCS1#/SIN2/IO19 V17 IO SA14 / SDD14

B05 IO AD23 T06 OD IGNNE# D11 IO PD0/INDEX# W18 IO SA15 / SDD15 A04 IO AD24 L20 I INDEX# C12 IO PD1/TRK00# Y14 IO SA16 / stra

B04 IO AD25 V05 OD INIT A12 IO PD2/WRTPRT# T13 IO SA17 / stra A03 IO AD26 R06 OD INTR E12 IO PD3/RDATA# U13 IO SA18

C04 IO AD27 F03 I INTRUDER#/GPI8 C13 IO PD4/DSKCHG# V13 IO SA19

B03 IO AD28 U0 7 IO IOR# / GPO22 B13 IO PD5 R12 IO SD00 D04 IO AD29 T07 IO IOW# / G PO23 A13 IO PD6 V12 IO SD01 A01 IO AD30 C07 IO IRDY# C14 IO PD7 W12 IO SD02 A02 IO AD31 T14 I IRQ14 M19 O PDA0 Y12 IO SD03

P03 I AOLGPI/THRM/I17 U14 I IRQ15 M18 O PDA1 U12 IO SD04 Y03 O APICLK / GPI9 U08 I IRRX / GPO15 M20 O PDA2 U11 IO SD05 Y04 I APICD1/AK#/IO29 T08 I IRRX2 / GPI L18 O PDCS1# R11 IO SD06 W04 O APICD0/ACS#/IO28 R08 O IRTX / GPO14 L19 O PDCS3# T11 IO SD07

E11 IOAUTOFD# / DR

T03 I BATLOW# / GPI5 K04 I JAB2 / GAMED5 R16 IO PDD01 V18 O SDA1 A14 I BUSY / MTR1# G05 I JAX / GAMED0 U20 IO PDD0 2 V20 O SDA2

F10I A08 IO CBE1# F01 I JBB1 / GAMED6 P16 IO PDD04 U19 O SDCS3# D06 IO CBE 2# H0 4 I JBB2 / GAMED7 N17 IO PDD05 W20 O SDDACK#

C05 IO CBE3# K05 I JBX / GAMED2 R20 IO PDD06 U17 I SDDR

R05ICPUMISS / GPI1 U04 OD CPURST M04 IO KBCK / A20G P18 IO PDD08 Y19 O SDIOW# W02 O CPUSTP# / GPO5 N01 IO KBDT / KBRC R19 IO PDD09 Y20 I SDRDY

B16ICTS#

F14 I DCD# Y13 IO LA21/OC3#/O21 P17 IO PDD11 E07 I SERR# A07 IO DEVSEL# V08 IO LAD0 T20 IO PDD12 E13 I SLCT/WGATE# K20 OD DIR# Y07 IO LAD1 T18 IO PDD13 D12 IO SLCTIN#/STEP#

L17 OD DRVDEN0 W07 IO LAD2 R17 IO PDD14 R04 O SLOWCLK / O0 K17 OD DRVDEN1 V07 IO LAD3 T17 IO PDD15 U06 OD SLP# / GPO7

J17 OD DS0# Y08 I LDRQ#/SDIN3/I15 N20 O PDDACK# T02 I SMBALRT# / I7 K19 OD DS1# W08 O LF RAME# P19 I PDDR H18 I DSKCHG# Y10 O LGNT1#/SD13/O10 N18 O PDIOR# R01 IO SMBCK2 / IO27 D14 I DSR# V10 O LGNT2#/SD15/O11 P20 O PDIOW # T01 IO SMBDT1

L02 AI DTD+ Y02 I LID / GPI4 N19 I P DRDY R02 IO SMBDT2 / IO 26 J19 OD WDATA# L03 AI DTD- U10 I LREQ1#/SD12/I12 D13 I PE / WDATA# Y05 OD SMI# J20 OD WGATE#

A16 O DTR# W10 I LREQ2#/SD14/I13 D03 I PGNTH# U09 O SPKR H17 I WRTPRT#

E16 O EECK W06 O MCCS#/O17/strapD01 I PGNTL# J18 OD STEP# V04 I WSC#/ARQ#/I14 C18 O EECS# G17 I MCOL / AIR C19 I EEDI G16 I MCRS / AIR C20 O EEDO D17 O MDCK B01 I PINTB# A11 IO STROBE#

Center

pins (24 pins): J8-J13, K8-K13, L8-L13, M8-M13

GND

11 P

H15 P GND K L15 P GND

P1 P14 P GND L

FRAME# E18I MRXD1

7PGND

D D D

M DPLL DRAM

AB1 / GAMED4 T16IOPDD

AY / GAMED1 T19IOPDD

BY / GAMED

LA2

D20 I MRXD2 E03 I PWRGD H16 I TRK00# D19 I MRXD3 H20 I RDATA# B15 O T XD

F18 I MRXERR/AIRQU03 I RING# / GPI3 M03 I UIC2 N02 IO MSCK / IR N04 IO MSDT / IRQ12 F05 I RSMRST# L04 I UIC4 G04 I M SI / I2S E02 I RTCX1 L01 I UIC5

K18 OD MTR0# A15 O RTS# A17 I USBOC0#

J16 OD MTR1# E14 I RXD D16 I USBOC1#

F16 I MTXCLK/AIR

F20 O MTXD0/AIR G18 O MTXD1/AIR G19 O MTXD2/AIR

R18IOPDD

B12 IO PINIT# / DIR# D07 IO STOP# B02 I PINTA# V06 OD STPCLK#

IMRXDV / AIR

PDIF E01

PDD1

2IPWRBTN#B07IOTRDY#

IRI# M01IUIC1

1 T09 O ROMCS#/KBCS# M02 I UIC3

Y18 IO SA00 / SDD00 A20 IO USBP0-

W17 IO SA01 / SDD01 B20 IO USBP0+

V16 IO SA02 / SDD02 A19 IO USBP1Y16 IO SA03 / SDD03 B19 IO USBP1+

W15 IO SA04 / SDD04 A18 IO USBP2-

2PVBAT

7P F F12 P F13 P VCC F1

G06 P VCC G09 P VCC G12 P VCC

15 P VCC K1 L

M M1

P08 P VCC P11 P VCC

ERIRQ#

R03 IO SMBCK1

P12 P VCC P15 P VCC

R R09 P VCC

R1 R14 P

F1 K16 P VCCMII L1

P E1 K

1PVREF

MII PLL

RAM

Preliminary Revision 0.8 October 29, 1999 -9- Pinouts

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Pin Descriptions

Table 1. Pin Descriptions

PCI Bus Interface

Signal Name Pin # I/O Signal Description

VT8231

AD[31:0]

C/BE[3:0]#

FRAME#

IRDY# TRDY# STOP# DEVSEL#

PAR SERR#

PINTA-D#

PREQH# PGNTH#

PREQL# PGNTL#

PCICLK PCKRUN#

PCIRST# PCISTP# CPUSTP#

/ GPO6

/ GPO5

(see pin

list) C5, D6, A8, F10

F6 IO

C7 IO

B7 IO D7 IO A7 IO

C8 IO

E7 I

B2, B1,

C3, C2

C1 O D3 I

D2 O D1 I

M17 I

V1 IO

E4 O

W1 O W2 O

Address/Data Bus.

FRAME# assertion and data is driven or received in following cycles.

Command/Byte Enable.

enables corresponding to supplied or requested data are driven on following clocks.

Frame.

one more data transfer is desired by the cycle initiator.

Initiator Ready. Target Ready. Stop. Device Select.

or subtractive decoding. As an input, DEVSEL# indicates the response to a VT8231initiated transaction and is also sampled when decoding whether to subtractively decode the cycle.

Parity. System Error.

error condition. Upon sampling SERR# active, the VT8231 can be programmed to generate an NMI to the CPU.

PCI Interrupt Request

INTD# pins as follows:

PCI Request. PCI Grant.

VT8231.

PCI Request. PCI Grant.

VT8231.

PCI Clock. PCI Bus Clock Run.

(high) or running (low). The VT8231 drives this signal low when the PCI clock is running (default on reset ) and releases it when it st ops the PCI cloc k. External device s may assert this signal low to request that the PCI clock be restarted or prevent it fro m stopping. Connect this pin to ground using a 100 Ω resistor if the function is not used. Refer to the “PCI Mobile Design Guide” and the VIA “Apollo MVP4 Design Guide” for more details.

PCI Reset. PCI Stop. CPU Stop.

Assertion indicates the address phase of a PCI transfer. Negation indicates that

Asserted by the target to request the master to stop the current transaction.

A single parity bit is provided over AD[31:0] and C/BE[3:0]#.

PCI Slot 1 INTA# INTB# INT C# INTD# PCI Slot 2 INTB# INTC# INTD# INTA# PCI Slot 3 INTC# INTD# INTA# INTB# PCI Slot 4 INTD# INTA# INTB# INTC# PCI Slot 5 INTA# INTB# INT C# INTD#

PCLK provides timing for all transactions on the PCI Bus.

The standard PCI address and data lines. The address is driven with

The command is driven with FRAME# assertion. Byte

Asserted when the initiator is ready for data transfer.

Asserted when the target is ready for data transfer.

The VT8231 asserts this signal to claim PCI transactions through positive

SERR# can be pulsed active by any PCI device that detects a system

. These pins are typically connected to the PCI bus INTA#-

PINTA# PINTB#

This signal goes to the North Bridge to request the PCI bus.

This signal is driven by the North Bridge to grant PCI access to the

This signal goes to the North Bridge to request the PCI bus.

This signal is driven by the North Bridge to grant PCI access to the

This signal indicates whether the PCI clock is or will be stopped

PINTC# PINTD#

Preliminary Revision 0.8 October 29, 1999 -10- Pinouts

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CPU Interface

Signal Name Pin # I/O Signal Description

VT8231

CPURST

INTR

NMI

INIT

STPCLK#

SMI#

FERR#

IGNNE#

/ GPO7

SLP#

A20M#

DTD+

DTD-

Note: Connect each of the above signals to 4.7K Ω pullup resistors to VCC3.

U4 OD

R6 OD

T5 OD

V5 OD

V6 OD

Y5 OD

U5 I

T6 OD

U6 OD

W5 OD

L2 Analog I

L3 Analog I

CPU Reset.

power-up.

CPU Interrupt.

an interrupt request is pending and needs service.

Non-Maskable Interrupt.

interrupt to the CPU. The VT8231 generates an NMI when either SERR# or IOCHK# is a sse rted.

Initialization.

special cycle on the PCI bus or if a soft reset is initiated by the register

Stop Clock.

throttle the processor clock.

System Management Interrupt.

the CPU in resp onse to different Power-Management events.

Numerical Coprocessor Error.

error signal on the CPU. Internally generates interrupt 13 if active.

Ignore Numeric Error.

on the CPU.

Sleep

CPUs only. Not currently used with socket-7 CPUs.

A20 Mask.

bit-20 generation. Logical combination of the A20GATE input (from internal or external keyboard controller) and Port 92 bit-1 (Fast_A20).

CPU DTD (Thermal Diode) Channel Plus.

external temperature sensing diode.

CPU DTD (Thermal Diode) Channel Minus.

first external temperature sensing diode.

The VT8231 asserts CPURST to reset the CPU during

INTR is driven by the VT8231 to signal the CPU that

The VT8231 asserts INIT if it detects a shut-down

STPCLK# is asserted by the VT8231 to the CPU to

(Rx75[7] = 0). Used to put the CPU to sleep. Used with slot-1

Connect to A20 mask input of the CPU to control address

NMI is used to force a non-maskable

SMI# is asserted by the VT8231 to

This signal is tied to the coprocessor

This pin is connected to the “ignore error” pin

Connect to cathode of first

Connect to anode of

Strap Options

Signal Name Pin # I/O Signal Description

/ SUSA#

Strap

/ MCCS#

Strap

/ PCS0#

Strap

/ SA16

Strap

/ SA17

Strap

/ KBCS# / ROMCS#

Strap

Preliminary Revision 0.8 October 29, 1999 -11- Pinouts

P1 I / O

W6 I / O

Y6 I / O

Y14 I / IO

T13 I / IO

T9 I / O / O

CPURST / INIT Polarity

H: L:

CPU Frequency Strapping

H: Disable L: Enable

SD Bus Width

H: 16-Bit L: 8-Bit

BIO ROM Interface

H: LPC L: Conventional

Auto Reboot

H: Disable L: Enable

CPU Type

4.7K to GND = Socket-7, 4.7K to VCC3 = Socket-370 / Slot-1

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Advanced Programmable Interrupt Controller (APIC) Interface

Signal Name Pin # I/O Signal Description

VT8231

/ APICREQ# / GPI14

WSC#

APICD0

APICD1

APICCLK SCIOUT#

/ GPIO30 / DTEST

AIRQ AIRQ AIRQ AIRQ AIRQ AIRQ AIRQ AIRQ AIRQ AIRQ AIRQ AIRQ

/ APICCS# / GPIO28

/ APICACK# / GPIO29

/ GPI9

/ GPIOD

/ MCOL / MCRS / MRXCLK / MRXD0 / MRXDV / MRXERR / MTXCLK / MTXD0 / MTXD1 / MTXD2 / MTXD3 / MTXENA

V4 I / I / I

W4 O / O / IO

Y4 O / O / IO

Y3 I / I Y1 O / IO

IO / O

G17 O G16 O E17 O E19 O E20 O

F18 O F16 O

F20 O G18 O G19 O G20 O

F19 O

Internal APIC Write Snoop Complete.

bridge to indicate that all snoop activity on the CPU bus initiated by the last PCI-to-DRAM write is complete and that it is safe to perform an APIC interrupt.

External APIC Request.

to PCICLK prior to sending an interrupt over the APIC serial bus. This signals the VT8231 to flush its internal buffers.

Internal APIC Data 0. External APIC Chip Select.

to select an external APIC (if used). This occurs if the external APIC is enabled and a PCI cycle is detected within the programmed APIC address range.

Internal APIC Data 1. External APIC Acknowledge.

that it internal buffers have been flushed (in response to APICREQ#). This indicates to the external APIC that the VT8231’s internal buffers have been flushed and that it is OK for the APIC to send its interrupt.

APIC Clock. SCI Out.

interrupts to external APIC (if used). Defined as SCIOUT# if external APIC enabled (function 0 Rx74[7] = 1).

APIC IRQ. APIC IRQ. APIC IRQ. APIC IRQ. APIC IRQ. APIC IRQ. APIC IRQ. APIC IRQ. APIC IRQ. APIC IRQ. APIC IRQ. APIC IRQ.

Used to route internally generated SCI and SMBus

Internal condition for connection to external APIC. Internal condition for connection to external APIC. Internal condition for connection to external APIC. Internal condition for connection to external APIC. Internal condition for connection to external APIC. Internal condition for connection to external APIC. Internal condition for connection to external APIC. Internal condition for connection to external APIC. Internal condition for connection to external APIC. Internal condition for connection to external APIC. Internal condition for connection to external APIC. Internal condition for connection to external APIC.

Asserted by external APIC synchronous

The VT8231 drives this signal active

Asserted by the VT8231 to indicate

Asserted by the north

Serial EEPROM Interface

Signal Name Pin # I/O Signal Description EECS#

EECK EEDO EEDI

Preliminary Revision 0.8 October 29, 1999 -12- Pinouts

C18 O E16 O C20 O C19 I

Serial EEPROM Chip Select. Serial EEPROM Clock. Serial EEPROM Data Output. Serial EEPROM Data Input.

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Low Pin Count (LPC) Interface

Signal Name Pin # I/O Signal Description

VT8231

LFRAME# LDRQ# LAD[3-0] HREQ1# HGNT1# HREQ2# HGNT2# LREQ1# LGNT1# LREQ2# LGNT2#

Note: Connect the LPC interface LPCRST# (LPC Reset) signal to PCIRST#

/ ACSDIN3 / GPI15

/ SD8 / GPI10 / SD9 / GPO8 / SD10 / GPI11

/ SD11 / GPO9 / SD12 / GPI12 / SD13 / GPO10 / SD14 / GPI13 / SD15 / GPO11

W8 O

Y8 I / I / I

V7, W7, Y7, V8 IO / IO

Y11 I / IO

W11 O / IO

V11 I / IO

T10 O / IO U10 I / IO Y10 O / IO

W10 I / IO

V10 O / IO

LPC Frame. LPC Data Request. LPC Address / Data. High Priority Request 1. High Priority Grant 1. High Priority Request 2. High Priority Grant 2. Low Priority Request 1. Low Priority Grant 1. Low Priority Request 2. Low Priority Grant 2.

LAN Controller - Media Independent Interface (MII)

Signal Name Pin # I/O Signal Description MCOL

MCRS

MDCK

MDIO

MRXCLK MRXD[3] MRXD[2] MRXD[1] MRXD[0] MRXDV MRXERR

MTXCLK

MTXD[3] MTXD[2] MTXD[1] MTXD[0] MTXENA

/ APICIRQ

/ APICIRQ , , , / APICIRQ

/ APICIRQ

/ APICIRQ, / APICIRQ, / APICIRQ, / APICIRQ

/ APICIRQ

G17 I / I G16 I / I

D17 O

D18 IO

E17 I / I D19 D20

E18

E19

E20 I / I

F18 I / I

F16 I / I

G20 G19 G18

F20

F19 O / I

I I I

I / I

O / I O / I O / I O / I

MII Collision Detect. MII Carrier Sense.

media is active.

MII Management Data Clock.

timing reference for MDIO

MII Manag e ment Data I/O.

the MDO bit.

MII Receive Clock. MII Receive Data.

external PHY synchronous with MRXCLK.

MII Receive Data Valid. MII Receive Error.

decoding error.

MII Transmit Clock.

supplied by the PHY.

MII Transmit Data.

MTXCLK.

MII Transmit Enable.

port to the PHY.

From the external PHY.

Asserted by the external PHY when the

Sent to the external PHY as a

Read from the MDI bit or written to

2.5 or 25 MHz clock recovered by the PHY. Parallel receive data lines driven by the

Asserted by the PHY when it detects a data

Always active 2.5 or 25 MHz clock

Parallel transmit data lines synchronized to

Indicates transmit active from the MII

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Universal Serial Bus Interface

Signal Name Pin # I/O Signal Description

VT8231

USBP0+ USBP0USBP1+ USBP1USBP2+ USBP2USBP3+ USBP3USBCLK USBOC0# USBOC1# USBOC2# USBOC3#

/ LA20 / GPO20 / LA21 / GPO21

B20 IO A20 IO B19 IO A19 IO B18 IO A18 IO C17 IO B17 IO C15 I A17 I D16 I

W13 I / IO / O

Y13 I / IO / O

USB Port 0 Data + USB Port 0 Data USB Port 1 Data + USB Port 1 Data USB Port 2 Data + USB Port 2 Data USB Port 3 Data + USB Port 3 Data USB Clock.

48MHz clock input for the USB interface

USB Port 0 Over Current Detect. USB Port 1 Over Current Detect. USB Port 2 Over Current Detect. USB Port 3 Over Current Detect.

System Management Bus (SMB) Interface (I2C Bus)

Signal Name Pin # I/O Signal Description SMBCK1

SMBCK2

/ GPIO27

SMBDT1 SMBDT2

/ GPIO26

SMBALRT#

/ GPI7

R3 IO R1 IO / IO T1 IO R2 IO / IO T2 I / I

SMB / I2C Channel 1 Clock. SMB / I SMB / I2C Channel 1 Data. SMB / I SMB Alert.

C Channel 2 Clock.

C Channel 2 Data.

(System Management Bus I/O space Rx08[3] = 1) When the chip is enabled to allow it, assertion generates an IRQ or SMI interrupt or a power management resume event. The same pin is used as General Purpose Input 6 whose value is reflected in Rx48[6] of function 4 I/O space

Port 0 is disabled if this input is low. Port 1 is disabled if this input is low Port 2 is disabled if this input is low. Port 3 is disabled if this input is low.

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UltraDMA-33 / 66 Enhanced IDE Interface

Signal Name Pin # I/O Signal Description

VT8231

PDRDY

PDDMARDY / PDSTROBE

SDRDY

SDDMARDY / SDSTROBE

PDIOR#

PHDMARDY / PHSTROBE

SDIOR#

SHDMARDY / SHSTROBE

PDIOW#

PSTOP

SDIOW#

SSTOP

PDDRQ SDDRQ PDDACK# SDDACK# IRQ14 IRQ15

N19 I

Y20 I

N18 O

W19 O

P20 O

Y19 O

P19 I U17 I N20 O

W20 O

T14 I U14 I

EIDE Mode: UltraDMA Mode:

Primary Device DMA Request. Secondary Device DMA Request. Primary Device DMA Acknowledge. Secondary Device DMA Acknowledge. Primary Channel Interrupt Request. Secondary Channel Interrupt Request.

Primary I/O Channel Ready. Primary Device DMA Ready

may assert DDMARDY to pause output transfers

Primary Device Strobe

device may stop DSTROBE to pause input data transfers

Secondary I/O Channel Ready. Secondary Device DMA Ready

device may assert DDMARDY to pause output transfers

Secondary Device Strobe

device may stop DSTROBE to pause input data transfers

Primary Device I/O Read. Primary Host DMA Ready

The host may assert HDMARDY to pause input transfers

Primary Host Strobe

may stop HSTROBE to pause output data transfers

Secondary Device I/O Read. Secondary Host DMA Ready

assert HDMARDY to pause input transfers

Host Strobe B

HSTROBE to pause output data transfers

Primary Device I/O Write. Primary Stop

initiation of an UltraDMA burst; negated by the host before data is transferred in an UltraDMA burst. Assertion of STOP by the host during or after data transfer in UltraDMA mode signals the termination of the burst.

Secondary Device I/O Write. Secondary Stop

. Output strobe (both edges). T he host may stop

. Stop transfer: Asserted by the host prior to

Primary channel DMA request

Secondary channel DMA request

Primary channel DMA acknowledge

Device ready indicator

. Output flow cont rol. The device

. Input data strobe (both edges). The

Device ready indicator

. Output flow control. The

. Input data strobe (both edges). The

Device read strobe

. Primary channel input flow control

. Output data strobe (both edges). The host

Device read strobe

. Input flow control. The host may

Device write strobe

Secondary channel DMA acknowledge

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UltraDMA-33 / 66 Enhanced IDE Interface (continued)

Signal Name Pin # I/O Signal Description

VT8231

PDCS1#

PDCS3#

SDCS1#

SDCS3#

PDA[2-0]

SDA[2-0]

PDD[15-0]

SDD[15-0]

/ SA[15-0]

L18 O

L19 O

U18 O

U19 O

M20, M18, M19 O

V20, V18, V19 O

T17, R17, T18, T20, P17, N16, R19, P18, R18, R20, N17, P16,

T19, U20, R16, T16

W18, V17, Y17, W16,

V15, Y15, W14, T15,

U15, U16, V14, W15,

Y16, V16, W17, Y18

Primary Master Chip Select.

on the primary IDE connector.

Primary Slave Chip Select.

the primary IDE connector.

Secondary Master Chip Select.

CS17X# on the secondary IDE connector.

Secondary Slave Chip Select.

on the secondary IDE connector.

Primary Disk Address.

in either the ATA command block or control block is being accessed.

Secondary Disk Address.

in either the ATA command block or control block is being accessed.

Primary Disk Data

Secondary Disk Data ISA Address

(SPKR strap 4.7K ohms high)

(SPKR strap 4.7K ohms low)

This signal corresponds to CS1FX#

This signal corresponds to CS3FX# on

This signal corresponds to

This signal corresponds to CS37X#

PDA[2:0] are used to indicate which byte

SDA[2:0] are used to indicate which byte

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MIDI Interface

Signal Name Pin # I/O Signal Description

VT8231

MSI MSO

/ I2S

/ SPDIF

G4 I / I

J4 O / O

MIDI Serial In

MIDI Serial Out

Serial Digital Audio Interface

Signal Name Pin # I/O Signal Description

/ MSI

I2S SPDIF

/ MSO

G4 I / I

J4 O / O

Serial Digital Audio In. Serial Digital Audio Out.

AC97 Audio / Modem Interface

Signal Name Pin # I/O Signal Description ACRST

ACSYNC ACSDOUT ACSDIN0 ACSDIN1 ACSDIN2 ACSDIN3 ACBITCLK

/ PCS1# / GPIO19 / LDRQ# / GPI5

G2 O G1 O H3 O H1 I H2 I

J1 I / O / IO

Y8 I / I / I

J3 I

AC97 Reset AC97 Sync AC97 Serial Data Out AC97 Serial Data In 0 AC97 Serial Data In 1 AC97 Serial Data In 2 AC97 Serial Data In 3 AC97 Bit Clock

Game Port Interface

Signal Name Pin # I/O Signal Description

/ GAMED0

JAX

/ GAMED1

JAY

/ GAMED2

JBX

/ GAMED3

JBY

/ GAMED4

JAB1

/ GAMED5

JAB2

/ GAMED6

JBB1

/ GAMED7

JBB2

See Function 0 Rx77[6]

G5 I H5 I K5 I

J5 I G3 I K4 I

F1 I

H4 I

Joystick A X-axis Joystick A Y-axis Joystick B X-axis Joystick B Y-axis Joystick A Button 1 Joystick A Button 2

Joystick B Button 1

Joystick B Button 2

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Floppy Disk Interface

Signal Name Pin # I/O Signal Description

VT8231

DRVDEN0 DRVDEN1 MTR0# MTR1# DS0# DS1# DIR# STEP# INDEX# HDSEL# TRK00# RDATA# WDATA# WGATE# DSKCHG#

WRTPRT#

See also Parallel Port pin descriptions for optional Floppy Disk interface functionality

L17 OD K17 OD K18 OD

J16 OD

J17 OD K19 OD K20 OD

J18 OD

L20 I H19 OD H16 I H20 I

J19 OD

J20 OD H18 I

H17 I

Drive Density Select 0. Drive Density Select 1. Motor Control 0. Motor Control 1. Drive Select 0. Drive Select 1. Direction. Step. Index. Head Select. Track 0. Read Data. Write Data. Write Gate. Disk Change.

since the last drive selection.

Write Protect.

commands to be ignor ed)

Direction of head movement (0 = inward motion, 1 = outward motion)

Low pulse for each track-to-track movement of the head.

Sense to detect that the head is positioned over the beginning of a track

Sense to detect that the head is positioned over track 0.

Select motor on drive 0.

Select motor on drive 1 Select drive 0. Select drive 1

Selects the side for R/W operations (0 = side 1, 1 = side 0)

Raw serial bit stream from the drive for read operatrions.

Encoded data to the drive for write operations.

Signal to the drive to enable current flow in the write head.

Sense that the drive door is open or the diskette has been changed

Sense for detection that the diskette is write protected (causes write

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Parallel Port Interface

Signal Name Pin # I/O Signal Description

VT8231

PINIT# STROBE# AUTOFD#

SLCTIN# SLCT ACK#

ERROR#

BUSY PE PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

As shown by the alternate functions above, in mobile applications the parallel port pins can op tionally be selected to function as a floppy disk interface for attachment of an external floppy drive using the parallel port connector (see Super I/O Configuration Index F6[5]).

/ DIR#

/ nc

/ DRVEN0

/ STEP#

/ WGATE#

/ DS1#

/ HDSEL#

/ MTR1#

/ WDAT A#

/ nc, / nc, / nc, / DSKCHG#, / RDATA#, / WRTPRT#, / TRK00#, / INDEX#

B12 IO / O A11 IO / E11 IO / O

D12 IO / O E13 I / O B14 I / O

F11 I / O

A14 I / O D13 I / O C14 A13 B13 C13 E12 A12 C12 D11

IO / IO / IO / IO / I IO / I IO / I IO / I IO / I

Initialize. Strobe. Auto Feed.

each line is printed. I/O pin in ECP/EPP mode.

Select In. Select. Acknowledge.

the data and is ready to accept new data

Error.

printer.

Busy. Paper End. Parallel Port Data.

Initialize printer. Output in standard mode, I/O in ECP/EPP mode.

Output used to strobe data into the printer. I/O in ECP/EPP mode.

Output used to cause the printer to automatically feed one line after

Output used to select the printer. I/O pin in ECP/EPP mode.

Status output from the printer. High indicates that it is powered on.

Status output from the printer. Low indicates that it has received

Status output from the printer. Low indicates an error condition in the

Status output from the printer. High indicates not ready to accept data.

Status output from the printer. High indicates that it is out of paper.

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Serial Port and Infrared Interface

Signal Name Pin # I/O Signal Description TXD

RXD IRTX

IRRX

IRRX2 RTS#

CTS#

DTR#

DSR#

DCD#

RI#

/ GPO14

/ GPO15

/ GPI

B15 O E14 I

R8 O / O

U8 I / O

T8 I / I

A15 O

B16 I

A16 O

D14 I

F14 I

C16 I

Transmit Data. Receive Data. Infrared Transmit.

1, 2, or 3. General Purpose Output 14 if Rx76[5] = 1

Infrared Receive.

or 3. General Purpose Output 15 if Rx76[5] = 1

Infrared Receive. Request To Send.

Typically used as hardware handshake with CTS# for low level flow control. Designed for direct input to external RS-232C driver.

Clear To Send.

device is ready to receive data. Typically used as hardware handshake with RTS# for low level flow control. Designed for input from external RS-232C receiver.

Data Terminal Ready.

ready. Typically used as hardware handshake with DSR# for overall readiness to communicate. Designed for direct input to external RS-232C driver.

Data Set Ready.

device is powered, initialized, and ready. Typically used as hardware handshake with DTR# for overall readiness to communicate. Designed for direct input from external RS-232C receiver.

Data Carrier Detect.

a carrier signal (i.e., a communications channel is currently open). In direct connect environments, this input will typically be driven by DTR# as part of the DTR/DSR handshake. Designed for direct input from external RS-232C receiver.

Ring Indicator.

condition. Used by software to initiate operations to answer and open the communications channel. Designed for direct input from external RS-232C receiver (whose input is typically not connected in direct connect environments).

Serial port transmit data out.

Serial port receive data in.

Indicator to the serial port that an external communications

Indicator to serial port that an external modem is detecting a ring

VT8231

IR transmit data out (Rx76[5] = 0) selectable from serial port

IR receive data in (Rx76[5] = 0) selectable to serial port 1, 2,

IR receive data in (Rx76[5] = 0)

Indicator that the serial output port is ready to transmit data.

Indicator that serial port is powered, initialized, and

Indicator to serial port that an external serial communications

Indicator to serial port that an external modem is detecting

Preliminary Revision 0.8 October 29, 1999 -20- Pinouts

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Conventional BIOS ROM / ISA Bus Interface

Signal Name Pin # I/O Signal Description

VT8231

/ USBOC3# / GPO21

LA21

/ USBOC2# / GPO20

LA20 SA[19:18],

/ strap,

SA17

/ strap,

SA16 SA[15:0]

SD15 SD14 SD13 SD12 SD11 SD10 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

IOR#

IOW#

MEMR#

MEMW#

IRQ1 IRQ8# IRQ12 IRQ14 IRQ15 SPKR

/ SDD[15:0]

/ LGNT2# / GPO11, / LREQ2# / GPI13, / LGNT1# / GPO10, / LREQ1# / GPI12, / HGNT2# / GPO9,

/ HREQ2# / GPI11, / HGNT1# / GPO8, / HREQ1# / GPI10, , , , , , , ,

/ GPO22

/ GPO23

/ MSCK

/ GPI1 / MSDT

Y13

W13

V13, U13,

T13, Y14,

W18, V17, Y17, W16,

V15, Y15, W14, T15, U15, U16, V14, W15,

Y16, V16, W17, Y18

V10

W10

Y10 U10 T10 V11

W11

Y11 T11 R11 U11 U12 Y12

W12

V12 R12

U7 IO

T7 IO

W9 IO

Y9 IO

N2 I / IO V3 I / I

N4 I / IO T14 I U14 I

U9 O

IO / O / O

IO / I / I

IO / O / O

IO / I / I

IO / O / O

IO / I / I

IO / O / O

IO / I / I

IO IO IO IO IO IO IO IO

System Address Bus

devices (e.g., BIOS ROMs) up to 4 Mbytes.

System Address Bus

interface to BIOS ROMs but may also be used to implement a subset of the ISA bus if required. SA[19-16] are connected to ISA bus SA[19-16] directly. SA[19-17] are also connected to LA[19-17] of the ISA bus.

System Data.

ROMs and for devices residing on the ISA bus. SD0-7 also output general purpose output information when GPOWE# is active.

I/O Read.

device that the slave may drive data on to the ISA data bus.

I/O Write.

device that the slave may latch data from the ISA data bus.

Memory Read.

slave that it may drive data onto the ISA data bus.

Memory Write.

slave that it may latch data from the ISA data bus.

Interrupt 1 (optional external Keyboard Controller). Interrupt 8 (optional external RTC). Interru Interrupt 14 (IDE Primary Channel). Interrupt 15 (IDE Secondary Channel). Speaker Drive.

IOR# is the command to an ISA I/O slave

IOW# is the command to an ISA I/O slave

t 12 (optional external PS2 Mouse Controller).

. Allows access to physical memory

. These address lines are used to

SD[15:0] provide the data path for BIOS

MEMR# is the command to a memory

MEMW # is t he comma nd to a memory

Output of internal timer/counter 2.

Serial IRQ

Signal Name Pin # I/O Signal Description SERIRQ

Preliminary Revision 0.8 October 29, 1999 -21- Pinouts

V9 I

Serial IRQ

(Rx68[3] = 1 and Rx74[6] = 0)

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Internal Keyboard Controller

Signal Name Pin # I/O Signal Description

VT8231

MSCK

MSDT

KBCK

KBDT

KBCS#

/ IRQ1

/ IRQ12

/ A20GATE

/ KBRC

/ ROMCS# / strap

N2 IO / I

N4 IO / I

M4 IO / I

N1 IO / I

T9 O / O / I

MultiFunction Pin

Rx5A[1]=1 Rx5A[1]=0

MultiFunction Pin

Rx5A[1]=1 Rx5A[1]=0

MultiFunction Pin

Rx5A[0]=1 Rx5A[0]=0

MultiFunction Pin

Rx5A[0]=1 Rx5A[0]=0

for CPURST# generation

Keyboard Chip Select

Mouse Clock. Interrupt Request 1

Mouse Data. Interrupt Request 12

Keyboard Clock. Gate A20.

Keyboard Data.

Keyboard Reset.

Chip Selects

Signal Name Pin # I/O Signal Description ROMCS#

MCCS#

PCS0#

PCS1#

/ KBCS# / strap

/ GPO17 / strap

/ GPO16 / strap

/ ACSDIN2 / GPIO19

T9 O / O / I

W6 O / IO

Y6 O / IO / IO

J1 O / I / IO

ROM Chip Select Microcontroller Chip Select

Asserted during read or write accesses to I/O ports 62h or 66h.

Programmable Chip Select 0.

during I/O cycles to programmable read or write ISA I/O port ranges. See also Rx59[3] and Rx77[2].

Programmable Chip Select 1.

(Internal mouse controller enabled by Rx5A[1])

From internal mouse controller.

. Interrupt 1 (external KBC).

(Internal mouse controller enabled by Rx5A[1])

From internal mouse controller.

. Interrupt 12 (ext PS2 mouse ctlr).

(Internal keyboard controller enabled by Rx5A[0])

From internal keyboard controller

Input from external keyboard controller.

(Internal keyboard controller enabled by Rx5A[0])

From internal keyboard controller.

From external keyboard controller (KBC)

(Rx5A[0]=0). To external keyboard controller chip.

(Rx5A[0]=1). Chip Select to the BIOS ROM.

(Rx76[3] = 1, Rx76[4] = 0, Rx77[0] = 1).

(Rx76[1] = 1 and Rx8B[0] = 1). Asserted

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General Purpose Inputs

Signal Name Pin # I/O Signal Description

VT8231

GPI0

/ IRQ8#

GPI1

/ EXTSMI#

GPI2

/ RING#

GPI3

/ LID

GPI4

/ BATLOW#

GPI5

/ PME#

GPI6

/ SMBALRT#

GPI7

/ INTRUDER#

GPI8

/ APICCLK

GPI9

/ SD8 / HREQ1#

GPI10

/ SD10 / HREQ2#

GPI11

/ SD12 / LREQ1#

GPI12

/ SD14 / LREQ2#

GPI13

/ WSC# / APICREQ#

GPI14

/ LDRQ# / ACSDIN3

GPI15

/ CPUMISS

GPI16

/ AOLGPI / THRM

GPI17

/ GPO18 / FAN2 / SLPBTN#

GPI18

/ GPO19 / ACSDIN2 / PCS1#

GPI19 GPI20 General Purpose Input 20 GPI21 General Purpose Input 21 GPI22 General Purpose Input 22 GPI23 General Purpose Input 23

/ GPO24 / GPIOA

GPI24

/ GPO25 / GPIOC / ATEST

GPI25

/ GPO26 / SMBDT2

GPI26

/ GPO27 / SMBCK2

GPI27

/ GPO28 / APICD0 / APICCS#

GPI28

/ GPO29 / APICD1 / APICACK#

GPI29

/ GPO30 / GPIOD / DTEST / SCIOUT#

GPI30

/ GPO31 / GPIOE

GPI31

F4 I V3 I / I T4 I / IO U3 I / I Y2 I / I T3 I / I U1 I / I T2 I / I F3 I / I

Y3 I / I Y11 I / IO / I W11 I / I O / I U10 I / IO / I W10 I / I O / I

V4 I / I / I

Y8 I / I / I

R5 I / I

P3 I / I / I

K3 I / O / I / I

J1 I / O / I / O

V2 I / O / IO

J2 I / O / IO / O R2 I / O / IO R1 I / O / IO

W4 I / O / O / O

Y4 I / O / O / O Y1 I / O / IO / O / O

W3 I / O / IO

General Purpose Input 0 General Purpose Input 1 General Purpose Input 2 General Purpose Input 3 General Purpose Input 4 General Purpose Input 5 General Purpose Input 6 General Purpose Input 7 General Purpose Input 8 General Purpose Input 9 General Purpose Input 10 General Purpose Input 11 General Purpose Input 12 General Purpose Input 13 General Purpose Input 14 General Purpose Input 15 General Purpose Input 16 General Purpose Input 17 General Purpose Input 18 General Purpose Input 19

General Purpose Input 24 General Purpose Input 25 General Purpose Input 26 General Purpose Input 27 General Purpose Input 28 General Purpose Input 29 General Purpose Input 30 General Purpose Input 31

(Rx5A[2] = 1)

Preliminary Revision 0.8 October 29, 1999 -23- Pinouts

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General Purpose Outputs

Signal Name Pin # I/O Signal Description

VT8231

/ SLOWCLK

GPO0

/ SUSA#

GPO1

/ SUSB#

GPO2

/ SUSST1#

GPO3

/ SUSCLK

GPO4

/ CPUSTP#

GPO5

/ PCISTP#

GPO6

/ SLP#

GPO7

/ SD9 / HGNT1#

GPO8

/ SD11 / HGNT2#

GPO9 GPO10 GPO11 GPO12 General Purpose Output 12. GPO13 General Purpose Output 13. GPO14 GPO15 GPO16 GPO17 GPO18 GPO19 GPO20 GPO21 GPO22 GPO23 GPO24 GPO25 GPO26 GPO27 GPO28 GPO29 GPO30 GPO31

/ SD13 / LGNT1# / SD15 / LGNT2#

/ IRTX / IRRX / PCS0# / MCCS# / / / LA20 / USBOC2# / LA21 / USBOC3# / IOR# / IOW# / / / / / / / /

/ FAN2 / SLPBTN#

GPI18

/ PCS1# / ACSDIN2

GPI19

/ GPIOA

GPI24

/ GPIOC / ATEST

GPI25

/ SMBDT2

GPI26

/ SMBCK2

GPI27

/ APICD0 / APICCS#

GPI28

/ APICD1 / APICACK#

GPI29

/ GPIOD / DTEST / SCIOUT#

GPI30

/ GPIOE

GPI31

R4 O / O

P1 O / O P2 O / O N5 O / O P4 O / O

W2 O / O W1 O / O

U6 O / O

W11 O / IO / O

T10 O / IO / O Y10 O / IO / O V10 O / IO / O

R8 O / O U8 O / I Y6 O / O

W6 O / O

K3 O / I / I / I

J1 O / I / O / I W13 O / IO / I Y13 O / IO / I

U7 O / O T7 O / O V2 O / I / IO

J2 O / I / IO / O

R2 O / I / IO R1 O / I / IO

W4 O / I / O / O

Y4 O / I / O / O Y1 O / I / IO / O / O

W3 O / I / IO

General Purpose Output 0.

00). Output value determined by PMU I/O Rx4C[0]

General Purpose Output 1. General Purpose Output 2. General Purpose Output 3. General Purpose Output 4. General Purpose Output 5. General Purpose Output 6. General Purpose Output 7. General Purpose Output 8. General Purpose Output 9. General Purpose Output 10. General Purpose Output 11.

General Purpose Output 14 General Purpose Output 15 General Purpose Output 16. General Purpose Output 17. General Purpose Output 18. General Purpose Output 19. General Purpose Output 20. General Purpose Output 21. General Purpose Output 22. General Purpose Output 23. General Purpose Output 24. General Purpose Output 25. General Purpose Output 26. General Purpose Output 27. General Purpose Output 28. General Purpose Output 29. General Purpose Output 30. General Purpose Output 31.

(Func 4 Rx54[1-0] =

(Rx76[5] = 1) (Rx76[5] = 1)

Preliminary Revision 0.8 October 29, 1999 -24- Pinouts

+ 102 hidden pages

VIA VT8231 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual