No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into
any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise
without the prior written permission of VIA Technologies Incorporated.
VT8231 may only be used to identify products of VIA Technologies, Inc.
is a registered trademark of VIA Technologies, Incorporated.
TM
PS/2
Pentium
Windows 95
PCI
All trademarks are the properties of their respective owners.
is a registered trademark of International Business Machines Corp.
TM
, Pentium-ProTM, Pentium-IITM, Pentium-IIITM, CeleronTM,and GTL+TM are registered trademarks of Intel Corp.
TM
TM
is a registered trademark of the PCI Special Interest Group.
, Windows 98TM, Windows NTTM, and Plug and PlayTM are registered trademarks of Microsoft Corp.
Disclaimer Notice:
No license is granted, implied or otherwise, under any patent or patent rights of VIA Technologies. VIA Technologies
makes no warranties, implied or otherwise, in regard to this document and to the products described in this document.
The information provided by this document is believed to be accurate and reliable as of the publication date of this
document. However, VIA Technologies assumes no responsibility for any errors in this document. Furthermore, VIA
Technologies assumes no responsibility for the use or misuse of the information in this document and for any patent
infringements that may arise from the use of this document. The information and product specifications within this
document are subject to change at any time, without notice and without obligation to notify any person of such change.
1.6 3/1/01 Removed ATEST and DTEST functions (reserved for internal test purposes)
Fixed GPI10-13 & GPO10-13 pin descriptions and Device 0 F4 RxE5[3-2]
Fixed note under General Purpose Inputs pin description table
Fixed STPCLK# errors in F4 Rx4C[0], PMIO Rx10[9], Rx2C[3]
Changed F5/6 Rx1C-1F to reserved and removed I/O Base 3 registers
1.7 3/19/01 Fixed heading in pin descriptions for UDMA pins
Fixed pin descriptions for JAB1, JBB1, GPI10-13, GPI28-29, GPO8-11
Fixed Device 0 Function 0 Rx40[2], Device 0 Function 4 RxE5[3-2]
1.8 4/30/01 Updated north bridge compatibility list in feature bullets
Added IRQ8# function to GPI1 pin; Added IOCHRDY to LREQ2#/GPI13 pin
Added function summary at beginning of Registers section
Added F0 Rx67[3-2] and added related notes in pin descriptions section
Removed SMB I/O register E;; Removed Temp Reading 3 from HWM I/O registers
Fixed definitions of F1 Rx43[3-0]; 50[28,20,12,4], F4 Rx55[7-6]
1.81 7/2/01 Updated company addresses; Updated Func 0 Rx4C[3:0]
Changed INIT pin to INIT# and added note to pin description
1.9 9/11/02 Removed incorrect register reference from PME# pin description
Fixed Device 0 Func 4 Rx42[4] description; Updated VBAT voltage specs
Added estimated power supply current / power dissipation specs based on test report data
1.91 11/4/02 Updated VIA logos on cover page and page headings to use new VIA corporate logo
Updated LAN Rx74 & added Rx78; fixed typo in electrical specs input voltage table
1.92 11/4/02 Fixed formatting problem in PDF mechanical spec page DH
2.0 11/20/02 Added ACSDIN2-3 functions & removed PCS1#; Updated GPI15, GPIO19 descriptions
Fixed typos in F2-6 Rx0-3; Updated F4 RxE4[5] and E5[7]; Updated LAN registers
2.01 12/19/02 Updated Port 61 (bits 7-6 and 3-2) and Port 92 (bits 7-6 and 3) DH
Updated pin name for G13 and G15 in pin diagram and pin descriptons
2.31 5/10/04 Updated Device1 Function 0 Rx8B VL
2.32 9/1/04 Added a lead-free package in Mechanical Specification VL
DH
DH
DH
DH
DH
DH
DH
DH
DH
DH
VL
Revision 2.32, September 1, 2004 -i- Revision History
Page 4
VT8231 South Bridge
TABLE OF CONTENTS
REVISION HISTORY .......................................................................................................................................................................I
TABLE OF CONTENTS.................................................................................................................................................................. II
LIST OF FIGURES .........................................................................................................................................................................IV
LIST OF TABLES ...........................................................................................................................................................................IV
Super-IO / KBC Configuration Index / Data Registers..................................................................................................... 51
Floppy Disk Controller Registers.......................................................................................................................................................... 55
Parallel Port Registers ........................................................................................................................................................................... 56
Serial Port 1 Registers ........................................................................................................................................................................... 57
SoundBlaster Pro Port Registers......................................................................................................................................... 58
FM Registers ......................................................................................................................................................................................... 58
Game Port Registers............................................................................................................................................................. 59
Fast IR Registers................................................................................................................................................................... 60
PCI Configuration Space I/O .............................................................................................................................................. 67
Device 0 Function 0 Registers - PCI to ISA Bridge ........................................................................................................... 68
PCI Configuration Space Header...........................................................................................................................................................68
ISA Bus Control .................................................................................................................................................................................... 68
Function Control.................................................................................................................................................................................... 72
Serial IRQ and PC/PCI DMA Control...................................................................................................................................................72
Plug and Play Control - PCI .................................................................................................................................................................. 73
Fast IR Control...................................................................................................................................................................................... 75
ISA Decoding Control........................................................................................................................................................................... 76
Device 0 Function 1 Registers - Enhanced IDE Controller............................................................................................... 78
PCI Configuration Space Header...........................................................................................................................................................78
Revision 2.32, September 1, 2004 -ii-Table of Contents
Page 5
VT8231 South Bridge
IDE I/O Registers.................................................................................................................................................................................. 84
Device 0 Function 2 Registers - USB Controller Ports 0-1................................................................................................ 85
PCI Configuration Space Header...........................................................................................................................................................85
USB I/O Registers................................................................................................................................................................................. 87
Device 0 Function 3 Registers - USB Controller Ports 2-3................................................................................................ 88
PCI Configuration Space Header...........................................................................................................................................................88
USB I/O Registers................................................................................................................................................................................. 90
Device 0 Function 4 Regs - Power Management, SMBus and HWM............................................................................... 91
PCI Configuration Space Header...........................................................................................................................................................91
Power Management-Specific PCI Configuration Registers................................................................................................................... 92
System Management Bus-Specific Configuration Registers ................................................................................................................. 99
General Purpose I/O Control Registers ............................................................................................................................................... 100
Power Management I/O-Space Registers ............................................................................................................................................ 101
System Management Bus I/O-Space Registers.................................................................................................................................... 110
Hardware Monitor I/O Space Registers............................................................................................................................................... 113
PCI Configuration Space Header – Function 5 Audio......................................................................................................................... 119
PCI Configuration Space Header – Function 6 Modem ......................................................................................................................120
Function 5 & 6 Codec-Specific Configuration Registers ....................................................................................................................121
I/O Base 0 Registers –Audio/Modem Scatter/Gather DMA................................................................................................................ 123
I/O Base 1 Registers – Audio FM NMI Status Registers..................................................................................................................... 127
I/O Base 2 Registers – MIDI / Game Port ........................................................................................................................................... 127
Device 1 Function 0 Registers - LAN ................................................................................................................................ 130
PCI Configuration Space Header.........................................................................................................................................................130
LAN I/O Registers............................................................................................................................................................................... 132
POWER MANAGEMENT.............................................................................................................................................................. 141
Power Management Subsystem Overview.......................................................................................................................................... 141
Processor Bus States............................................................................................................................................................................ 141
System Suspend States and Power Plane Control................................................................................................................................ 142
General Purpose I/O Ports................................................................................................................................................................... 142
Power Management Events ................................................................................................................................................................. 143
System and Processor Resume Events................................................................................................................................................. 143
Legacy Power Management Timers .................................................................................................................................................... 144
System Primary and Secondary Events ...............................................................................................................................................144
ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................... 145
DC CHARACTERISTICS ............................................................................................................................................................. 146
POWER CHARACTERISTICS ....................................................................................................................................................... 146
INPUT VOLTAGE ........................................................................................................................................................................ 147
TABLE 3. FUNCTION SUMMARY............................................................................................................................................. 31
TABLE 4. SYSTEM I/O MAP....................................................................................................................................................... 31
− Steerable DMA channels for integrated floppy, parallel, and soundblaster pro controllers
− One additional steerable interrupt channel for on-board plug and play devices
− Microsoft Windows 2000
BIOS compliant
TM
, Windows 98SETM, Windows 98TM, Windows NTTM, Windows 95
• Built-in NAND-tree pin scan test capability
• 0.30um, 3.3V, low power CMOS process
• Single chip 27x27 mm, 376 pin BGA
TM
and plug and play
Revision 2.32, September 1, 2004 -4- Product Features
Page 11
VT8231 South Bridge
OVERVIEW
The VT8231 South Bridge is a high integration, high performance, power-efficient, and high compatibility device that supports
Intel, AMD, and VIA / Cyrix based processor to PCI bus bridge functionality to make a complete Microsoft PC99-compliant PCI /
LPC system. The VT8231 includes standard intelligent peripheral controllers:
a) Master mode enhanced IDE controller with dual channel DMA engine and interlaced dual channel commands. Dedicated
FIFO coupled with scatter and gather master mode operation allows high performance transfers between PCI and IDE
devices. In addition to standard PIO and DMA mode operation, the VT8231 also supports the UltraDMA-33, 66, and 100
standards to allow reliable data transfer rates up to 100 MB/sec throughput. The IDE controller is SFF-8038i v1.0 and
Microsoft Windows-family compliant.
b) Integrated LAN Fast Ethernet controller (MAC) with Media Independent Interface (MII) to external Ethernet PHY or
HomePNA PHY. The LAN controller operates at 1 / 10 / 100 Mbit/sec transfer rates using either full and half duplex
operation and has separate 2Kbyte FIFOs for receive and transmit of full ethernet packets. The internal high-performance
PCI interface has scatter / gather and bursting capability and can align bytes in the transmit data buffer to reduce CPU
utilization. The LAN interface can perform address filtering on physical, broadcast, and multicast packets. The interface can
also be configured for system wake up on link status change, receipt of magic packet, unicast physical address match on
incoming packets, and predefined pattern match in the incoming data.
c) LPC (Low Pin Count) interface for BIOS ROM plus optional conventional BIOS ROM support
d) Universal Serial Bus controller that is USB v1.1 and Universal HCI v1.1 compliant. The VT8231 includes the root hub with
four function ports with integrated physical layer transceivers. The USB controller allows hot plug and play and isochronous
peripherals to be inserted into the system with universal driver support. The controller also implements legacy keyboard and
mouse support so that legacy software can run transparently in a non-USB-aware operating system environment.
e) Keyboard controller with PS2 mouse support
f) Real Time Clock with 256 byte extended CMOS. In addition to standard RTC functionality, the integrated RTC also
includes the date alarm, century field, and other enhancements for compatibility with the ACPI standard.
g) Notebook-class power management functionality compliant with ACPI and legacy APM requirements. Multiple sleep states
(power-on suspend, suspend-to-DRAM, and suspend-to-Disk) are supported with hardware automatic wake-up. Additional
functionality includes event monitoring, CPU clock throttling and stop (Intel processor protocol), PCI bus clock stop control,
modular power, clock and leakage control, hardware-based and software-based event handling, general purpose I/O, chip
select and external SMI.
h) Hardware monitoring subsystem for managing system / motherboard voltage levels, temperatures, and fan speeds
i) Full System Management Bus (SMBus) interface with one master / slave port and one slave-only port
j) 16550-compatible serial I/O port with “Fast-IR” infrared communications port option.
and hardware-assisted FM blocks are included for Windows DOS box and real-mode DOS compatibility. Loopback
capability is also implemented for directing mixed audio streams into USB and 1394 speakers for high quality digital audio.
l) Game port and MIDI port
m) Standard floppy disk drive interface
n) ECP/EPP-capable parallel port with floppy disk controller pinout option
o) Serial IRQ for docking and non-docking applications
p) Plug and Play controller that allows complete steerability of all PCI interrupts and internal interrupts to any interrupt channel.
One additional steerable interrupt channel is provided to allow plug and play and reconfigurability of on-board peripherals
for Windows family compliance.
Revision 2.32, September 1, 2004 -5- Overview
Page 12
VT8231 South Bridge
CPU / Cache
Sideband Signals:
Init / CPUreset
IRQ / NMI
SMI / StopClk
FERR / IGNNE
SLP# (Slot-1)
Boot ROM
Onboard
LPC I/O
CA
CD
LPC
RTC
Crystal
North Bridge
VT8231
376 BGA
MA/Command
MD
PCI
SMB
USB Ports 0-3
Keyboard / Mouse
MIDI / Game Ports
Parallel Port
Serial Port
Infrared Comm Port
IDE Primary and Secondary
Floppy Disk Interface
AC97 Link
Hardware Monitor Inputs
GPIO, Power Control, Reset
Fast Ethernet Interface
System Memory
DIMM Module ID
Expansion
Cards
Figure 1. PC System Configuration Using the VT8231
Note: Some of the pins above have alternate functions and alternate names. The table above contains only one name (usually the most often used function), but the
pin lists and pin descriptions contain all names.
PGNT
L#
PWR
GD
RSM
RST#
AC
RST#
AC
SDIN1
BCLK
FAN 1 FAN2
SLPB#
MS
CK
SUS
B#
SMB
DT2
SMB
ALRT#
LOW#
PWR
BTN#
LID
IRQ8#
SUS
CLK
AD
C#
27
AD
H#
29
RTC
PCI
X1
RST#
INTR
GPI 0 RTC
UDR#
JA
MSI
B1
AC
SUS
C#
AOL
GPI
CK1
BAT
CLK
JB
B2
MSO
JA Y JB
4
CK
MS
DT
CPU
STP#
GPO 0 PCK
PCI
STP#
RST
WSC#
D0
APIC
D1
SDO
SMB
RING # CPU
GPI1
GPIO E APIC
PCS1#
SDIN2
HWM
HWM
RUN#
FERR
AD
23
18 T RDY#
CBE
AD
3#
19 I RDY#
AD
CBE
20
AD
22
X2
JA
B2
GPIO
C
X
GND
VCC
SUS
ST#
VCC
SUS
NMI
#
INIT # STP
A20
M#
SMI#
STOP # AD
2#
AD
SERR # AD
17
FRM#
VCC
GND VCC VCC VCC GND VCC
VCC
VCC
VCC J GND GND GND GND GND GNDJ VCC
GND K GND GND GND GND GND GNDK VCC
VCC L GND GND GND GND GND GNDL GND
VCC M GND GND GND GND GND GNDM VCC
VCC N7 8 9 10 11 12 13 N14 GND
VCC
SUS
INTR
IGN
NE#
SLP#
CLK# L AD3 L AD0
MCCS
#/strap L AD2 L FRM#
PCS0#
/strap L AD1 L DRQ#
H7 8 9 10 11 12 13 H14 GND
GND VCC VCC GND VCC VCC VCC GND VCC
VCC
IO
W#
IO
R#
AD 9 AD
1#
AD
AD
15
PAR
14
13
AD
11
IR
TX
IR
RX2
IR
RX
AD 4 AD 1 P
10
AD
AD 6 AD 0 PD 1 PD 4 PD 7 USB
12
AD 7 AD 2 PD 0 SLCT
AD 8 AD 3 AUTO
CBE
VCC
VCC VCC
ROM
SPKR
MEM
MEM
CS#
SER
IRQ
R#
W#
0#
HG2#
GPO9
LR1#
GPI12
LG2#
GPO11
LR2#
RDY
LG1#
GPO10
5
ERR#
HR2#
GPI11
HG1#
GPO8
HR1#
STR#
INIT#
FD#
SD 6SD
SD
7
SD
5
PD 2 PD
6
PD
5
PE DSR# DCD#
IN#
PD
SLCT RXD
3
VCC VCC
GND
LAN
VCC VCC VCC
0
SA17
OSC
/strap
SD
SA
4
18
SA
SD
19
1
LA
SD
20
2
SD
LA
3
21
BUSY RTS# DTR#
ACK# TXD CTS#
RI#
CLK
USB
OC1#
EE
VCC
CK
USB
GND
USB
GND
IRQ
14
IRQ
15
SA5
SDD5
SA9
SDD9
SA16
/strap
VCC
VCC
LAN
SA8
SDD8
SA7
SDD7
SA11
SDD11
SA4
SDD4
SA10
SDD10
VCC
MII
M
CRS M COL
TRK
00#
MTR
1#
VCC
MII
VCC
PLL
GND
PLL
PD
D10
PD
D4
PD
D1
PD
D0
SA6
SDD6
SA2
SDD2
SA12
SDD12
SA3
SDD3
USB
OC0#
USB
P3-
USB
P3+
EE
DO
EE
DI
MTX
CLK
WRT
PRT#
DS
0#
DRV
DEN1
DRV
DEN0
PCI
CLK
PD
D5
PD
D11
PD
D14
PD
D15
SD
DRQ
SA14
SDD14
SA1
SDD1
SA13
SDD13
USB
P0-
USB
P0+
EE
CS#
MD
IO
MRX
D1
MRX
ERR
MTX
D1
DSK
CHG#
STEP#
MTR
0#
PDCS
1#
PD
A1
PD
IOR#
PD
D8
PD
D7
PD
D13
SDCS
1#
SD
A1
SA15
SDD15
SA0
SDD0
USB
USB
P1-
P2-
USB
USB
P1+
P2+
MRX
MD
CLK
CK
MRX
MRX
D3
D2
MRX
MRX
D0
DV
MTX
MTX
ENA
D0
MTX
MTX
D2
D3
HD
R
DATA#
SEL#
W
DATA#W GATE#
DS
DIR#
1#
PDCS
RDY
DRQ
SDCS
IOR#
IOW#
3#
PD
A0
PD
PD
PD
D9
PD
D3
3#
SD
A0
SD
SD
IN
DEX#
PD
A2
PD
DACK#
PD
IOW#
PD
D6
PD
D12
PD
D2
SD
A2
SD
DACK#
SD
RDY
Revision 2.32, September 1, 2004 -7- Pin Diagrams
Page 14
VT8231 South Bridge
Pin Lists
Figure 3. VT8231 Pin List (Numerical Order)
Pin Pin Name Pin Pin Name Pin Pin Name Pin Pin Name Pin Pin Name
A01 IO AD30 D12 IO SLCTIN#/STEP# H03 O ACSDOUT P02 O SUSB# / GPIO2 U13 IO SA18
A02 IO AD31 D13 I PE / WDATA# H04 I JBB2 / GPO13 P03 I AOLGPI/THRM/I17 U14 I IRQ15
A03 IO AD26 D14 I DSR# H05 I JAB2 / GPO12 P04 O CPUSTP# / GPO5 U15 IO SA07 / SDD07
A04 IO AD24 D15 I DCD#
A05 IO AD21 D16 I USBOC1#
A06 IO AD16 D17 I EEDO H16 I TRK00#
A07 IO DEVSEL# D18 IO MDIO H17 I WRTPRT#
A08 IO CBE1# D19 I MRXD3 H18 I DSKCHG#
A09 IO AD09 D20 I MRXD2 H19O HDSEL#
A10 IO AD05
A11 IO STROBE# E02 I PWRGD J01I JAX
A12 IO PD2 / WRTPRT# E03 I RTCX1 J02 I JBY
A13 IO PD6 E04 O PCIRST# J03 I ACBITCLK
A14 I BUSY / MTR1# E05 IO AD22 J04 O MSO
A15 O RTS# E06 IO AD17 J05 IO GPIOC/IO25/CHSIO P16 IO PDD04 V07 IO LAD3
A16 O DTR# E07 I SERR#
A17 I USBOC0# E08 IO AD13
A18 IO USBP0- E09 IO AD08 J16 O MTR1# P19 I PDDRQ V10 O LGNT2# / GPO11
A19 IO USBP1- E10 IO AD03 J17 O DS0# P20 O PDIOW# V11 I HREQ2# / GPI11
A20 IO USBP2- E11 IO AUTOFD#/DRV0 J18O STEP#R01 IO SMBCK2 / GPIO27 V12 IO SD01
B01 I PINTB# E12 IO PD3 / RDATA# J19O WDATA#R02 IO SMBDT2 / GPIO26 V13 IO SA19
B02 I PINTA# E13 I SLCT/WGATE# J20 O WGATE# R03 IO SMBCK1 V14 IO SA05 / SDD05
B03 IO AD28 E14 I RXD
B04 IO AD25
B05 IO AD23 E16 O EECK K03 I FAN2/SLPB#/IO18 R06 OD INTR V17 IO SA14 / SDD14
B06 IO AD18 E17 O EEDI K04 I JAY
B07 IO TRDY# E18 I MRXD1 K05 I JBX R08 O IRTX / GPO14 V19 O SDA0
B08 IO AD15 E19 I MRXD0
B09 IO AD10 E20 I MRXDV
B10 IO AD04 F01 I JBB1 / GPI29
B11 IO AD01 F02 I RSMRST# K17 O DRVDEN1 R12 IO SD00 W03 IO GPIOE / GPIO31
B12 IO PINIT# / DIR# F03 I INTRUDER#/GPI8 K18 O MTR0#
B13 IO PD5 F04 I GPI0 K19 O DS1#
B14 I ACK# / DS1# F05 O RTCX2 K20 O DIR#
B15 O TXD F06 IO FRAME# L01AI UIC5R16 IO PDD01W07 IO LAD2
B16 I CTS#
B17 IO USBP3- F08 IO AD11 L03 AI DTD- R18 IO PDD07 W09 IO MEMR#
B18 IO USBP0+
B19 IO USBP1+ F10 IO CBE0#
B20 IO USBP2+ F11 I ERROR#/HDSEL#
C01 O PREQH#
C02 I PINTD#
C03 I PINTC#
C04 IO AD27
C05 IO CBE3#
C06 IO AD19 F17 I MTXCLK L20 I INDEX# T07 IO IOW# / GPIO23 W18 IO SA15 / SDD15
C07 IO IRDY# F18 I MRXERR M01 AI UIC1T08I IRRX2 / GPIOB W19 O SDIOR#
C08 IO PAR F19 O MTXENA M02 AI UIC3 T09 O ROMCS# / KBCS# W20 O SDDACK#
C09 IO AD12 F20 O MTXD0 M03 AI UIC2T10O HGNT2# / GPO9 Y01 IO GPIOD / GPIO30
C10 IO AD06 G01 O ACSYNC M04 IO KBCK / A20GT11IO SD07Y02 IO GPIOA / GPIO24
C11 IO AD00 G02 O ACRST#
C12 IO PD1 / TRK00# G03 I JAB1 / GPI28
C13 IO PD4 / DSKCHG# G04 I MSI
C14 IO PD7 G05 O ACSDIN2 / GPIO19
C15 I USBCLK
C16 I RI#
C17 IO USBP3+
C18 O EECS#
C19 I MRXCLK
C20 O MDCK
D01 I PGNTL#
D02 O PREQL#
D03 I PGNTH#
D04 IO AD29
D05 IO AD20 G16 I MCRS
D06 IO CBE2# G17 I MCOL N16 IO PDD10 U07 IO IOR# / GPIO22 Y18 IO SA00 / SDD00
D07 IO STOP# G18 O MTXD1 N17 IO PDD05 U08 I IRRX / GPO15 Y19 O SDIOW#
D08 IO AD14 G19 O MTXD2 N18 O PDIOR# U09 O SPKR Y20 I SDRDY
D09 IO AD07 G20 O MTXD3 N19I PDRDYU10I LREQ1# / GPI12
D10 IO AD02 H01 I ACSDIN0 N20O PDDACK#U11 IO SD05
D11 IO PD0 / INDEX# H02 I ACSDIN1 P01O SUSA#/GPO1/strapU12 IO SD04
E01 P VBAT
E15 P VCCUSB
F07 P VCC
F09 P VCC
F12 P VCC L15 P GND
F13 P VCC L16 P VCCPLL
F14 P GNDUSB
F15 P VCC
F16 P VCCMII
G06 P VCC
G07 P GND
G08 P VCC
G09 P VCC
G10 P VCC
G11 P GND
G12 P VCC
G13 P GNDLAN
G14 P GND
G15 P VCCLAN N06 P VCC
H06 P VCC P05 P VCCSUS
H15 P GND P06 P VCCSUS
H20IRDATA#
J06 P VCC
J15 P VCC
K01O VREF
K02 I FAN1 R05 IO PCKRUN# V16 IO SA02 / SDD02
K06 P GND R09 P VCC
K15P VCCR10P VCC
K16P VCCMII
L02 AI DTD+ R17 IO PDD14 W08 O LFRAME#
L04 AI UIC4 R19 IO PDD09 W10 I LREQ2#/GPI13/OCHRDY
L05 P GNDHWM
L06P VCC
L17 O DRVDEN0 T04 O PCISTP# / GPO6 W15 IO SA04 / SDD04
L18 O PDCS1# T05 OD NMI W16 IO SA12 / SDD12
L19 O PDCS3# T06 OD IGNNE# W17 IO SA01 / SDD01
M05 P VCCHWM
M06 P VCC
M15 P VCC
M16 P GNDPLL
M17 I PCICLK T16 IO PDD00 Y07 IO LAD1
M18 O PDA1 T17 IO PDD15 Y08 I LDRQ# / GPI15 / SDIN3
M19 O PDA0 T18 IO PDD13 Y09 IO MEMW#
M20 O PDA2 T19 IO PDD03 Y10 O LGNT1# / GPO10
N01 IO KBDT / KBRCT20 IO PDD12Y11 I HREQ1# / GPI10
N02 IO MSCK / IRQ1U01I PME# / GPI6Y12 IO SD03
N03O SUSC# / GPOU02I PWRBTN#Y13 IO LA21/OC3#/IO21
N04 IO MSDT / IRQ12 U03 I RING# / GPI3 Y14 IO SA16 / strap
N05 O SUSST1# / GPO3 U04 OD CPURST Y15 IO SA10 / SDD10
N15 P GND
P07 P GND
P08 P VCC
P09 P VCC
P10P GND
P11P VCC
P12P VCC
P13 P VCC
P14 P GND
P15 P VCC
T12 I OSC Y03 I APICCLK / GPI9
T13 IO SA17 / strap Y04 O APICD1 / GPO29
T14 I IRQ14 Y05 OD SMI#
T15 IO SA08 / SDD08 Y06 O PCS# / GPO16
U05 I FERR# Y16 IO SA03 / SDD03
U06 OD SLP# / GPO7 Y17 IO SA13 / SDD13
Center GND pins (24 pins): J8-J13, K8-K13, L8-L13, M8-M13
U16 IO SA06 / SDD06
U17 I SDDRQ
U18 O SDCS1#
U19 O SDCS3#
U20 IO PDD02
V01 I CPUMISS / GPI16
V02 I LID / GPI4
V03 I GPI1 / IRQ8#
V04 I WSC# / GPI24
V05 OD INIT#
V06 OD STPCLK#
V18 O SDA1
V20 O SDA2
W01 IOD EXTSMI# / GPI2
W04 O APICD0 / GPIO28
W05 OD A20M#
W06 O MCCS#/O17/strap
Revision 2.32, September 1, 2004 -8- Pin Lists
Page 15
VT8231 South Bridge
K
K
K
K
K
K
Q
Figure 4. VT8231 Pin List (Alphabetical Order)
Pin Pin Name Pin Pin Name Pin Pin Name Pin Pin Name Pin Pin Name
W05 OD A20M# D17 I EEDO C20 O MDCK C03 I PINTC# P01 O SUSA# / GPO1
W04 O APICD0 / GPIO28 T08 I IRRX2 / GPIOB L19 O PDCS3# T11 IO SD07
Y04 O APICD1 / GPIO29 R08 O IRTX / GPO14 T16IO PDD00V19O SDA0
E11 IO AUTOFD# / DRV0 G03 I JAB1 / GPI28 R16IO PDD01V18O SDA1
T03 I BATLOW# / GPI5 H05 I JAB2 / GPO12 U20 IO PDD02 V20 O SDA2
A14 I BUSY / MTR1# J01 I JAX T19IO PDD03U18O SDCS1#
F10 IO CBE0# K04 I JAY P16 IO PDD04U19O SDCS3#
A08 IO CBE1# F01 I JBB1 / GPI29 N17 IO PDD05W20O SDDACK#
D06 IO CBE2# H04 I JBB2 / GPO13 R20 IO PDD06 U17 I SDDRQ
C05 IO CBE3# K05 I JBX R18 IO PDD07W19 O SDIOR#
V01 I CPUMISS / GPI16 J02 I JBY P18IO PDD08Y19O SDIOW#
U04 OD CPURST M04 IO KBCK / A20G R19IO PDD09Y20ISDRDY
P04 O CPUSTP# / GPO5 N01 IO KBDT / KBRC N16 IO PDD10V09ISERIRQ
B16 I CTS# W13 IO LA20 / OC2# / GPIO20P17IO PDD11E07I SERR#
D15 I DCD# Y13 IO LA21 / OC3# / GPIO21T20IO PDD12E13I SLCT/WGATE#
A07 IO DEVSEL# V08 IO LAD0 T18 IO PDD13D12 IO SLCTIN#/STEP#
K20 O DIR# Y07 IO LAD1 R17IO PDD14R04O SLOWCLK / O0
L17 O DRVDEN0 W07 IO LAD2 T17 IO PDD15U06 OD SLP# / GPO7
K17 O DRVDEN1 V07 IO LAD3 N20O PDDACK#T02I SMBALRT# / I7
J17 O DS0# Y08 I LDRQ#/ / GPI15 / SDIN3P19IPDDR
K19 O DS1# W08 O LFRAME# N18O PDIOR#R01IO SMBCK2 / IO27
H18 I DSKCHG# Y10 O LGNT1# / GPO10 P20O PDIOW#T01IO SMBDT1
D14 I DSR# V10 O LGNT2# / GPO11 N19I PDRDYR02IO SMBDT2 / IO26 J19 O WDATA#
L02 AI DTD+ V02 I LID / GPI4 D13I PE / WDATA#Y05 OD SMI# J20 O WGATE#
L03 AI DTD– U10 I LREQ1# / GPI12 D03I PGNTH#U09O SPKR H17 I WRTPRT#
A16 O DTR# W10 I LREQ2#/GPI13/IOCHRDD01I PGNTL#J18O STEP# V04 IWSC# / GPI14
E16 O EECK W06 O MCCS#/O17/strap B12 IO PINIT# / DIR#D07 IO STOP#
C18 O EECS# G17 I MCOL B02I PINTA#V06 OD STPCLK#
E17 O EEDI G16 I MCRS B01 I PINTB# A11 IO STROBE#
G07 P GND
G11 P GND
G14 P GND
H15 P GND
K06 P GND
L15 P GND
N15 P GND
P07 P GND
P10 P GND
P14 P GND
L05 P GNDHWM
M16 P GNDPLL
G13 P GNDLAN
F14 P GNDUSB
D20IMRXD2H20I RDATA# B15 O TXD
D19 IMRXD3C16I RI#M01 I UIC1
E20I MRXDVU03IRING# / GPI3 M03 I UIC2
F18I MRXERRT09O ROMCS#/KBCS# M02 I UIC3
N02 IO MSCK / IRQ1F02IRSMRST# L04 I UIC4
N04 IO MSDT / IRQ12E03IRTCX1 L01 I UIC5
G04IMSIF05O RTCX2 C15 I USBCL
Center GND pins (24 pins): J8-J13, K8-K13, L8-L13, M8-M13
D02O PREQL# N05 O SUSST1# / GPO3
W17 IO SA01 / SDD01 B18 IO USBP0+
E01 P VBAT
F07 P VCC
V15 IO SA11 / SDD11
R03IO SMBCK1
F09 P VCC
F12 P VCC
F13 P VCC
F15 P VCC
G06 P VCC
G08 P VCC
G09 P VCC
G10 P VCC
G12 P VCC
H06 P VCC
J06 P VCC
J15 P VCC
K15 P VCC
L06 P VCC
M06 P VCC
M15 P VCC
N06 P VCC
P08 P VCC
P09 P VCC
P11 P VCC
P12 P VCC
P13 P VCC
P15 P VCC
R07 P VCC
R09 P VCC
R10 P VCC
R13 P VCC
R14 P VCC
R15 P VCC
M05 P VCCHWM
F16 P VCCMII
K16 P VCCMII
L16 P VCCPLL
G15 P VCCLAN
P05 P VCCSUS
P06 P VCCSUS
E15 P VCCUSB
K01 O VREF
Revision 2.32, September 1, 2004 -9- Pin Lists
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VT8231 South Bridge
Pin Descriptions
Table 1. Pin Descriptions
PCI Bus Interface
Signal Name Pin # I/O Signal Description
AD[31:0]
C/BE[3:0]#
FRAME#
IRDY#
TRDY#
STOP#
DEVSEL#
PAR
SERR#
PINTA-D#
PCICLK
PCKRUN#
PCIRST#
PCISTP# / GPO6T4 O
CPUSTP# / GPO5P4 O
(see pin
list)
C5, D6,
A8, F10
F6 IO Frame. Assertion indicates the address phase of a PCI transfer. Negation
C7 IO Initiator Ready. Asserted when the initiator is ready for data transfer.
B7 IO Target Ready. Asserted when the target is ready for data transfer.
D7 IO Stop. Asserted by the target to request the master to stop the current
A7 IO Device Select. The VT8231 asserts this signal to claim PCI transactions
C8 IO Parity. A single parity bit is provided over AD[31:0] and C/BE[3:0]#.
E7 I System Error. SERR# can be pulsed active by any PCI device that detects a
B2, B1,
C3, C2
M17 I PCI Clock. PCLK provides timing for all transactions on the PCI Bus.
R5 IO PCI Bus Clock Run. This signal indicates whether the PCI clock is or will be
E4 O
IO Address/Data Bus. The standard PCI address and data lines. The address is
driven with FRAME# assertion and data is driven or received in following
cycles. IDSEL is internally connected to AD28.
IO Command/Byte Enable. The command is driven with FRAME# assertion.
Byte enables corresponding to supplied or requested data are driven on
following clocks.
indicates that one more data transfer is desired by the cycle initiator.
transaction.
through positive or subtractive decoding. As an input, DEVSEL# indicates
the response to a VT8231-initiated transaction and is also sampled when
decoding whether to subtractively decode the cycle.
system error condition. Upon sampling SERR# active, the VT8231 can be
programmed to generate an NMI to the CPU.
I PCI Interrupt Request. These pins are typically connected to the PCI bus
stopped (high) or running (low). The VT8231 drives this signal low when the
PCI clock is running (default on reset) and releases it when it stops the PCI
clock. External devices may assert this signal low to request that the PCI clock
be restarted or prevent it from stopping. Connect this pin to ground using a
100 Ω resistor if the function is not used. Refer to the “PCI Mobile Design
Guide” and the VIA “Apollo MVP4 Design Guide” for more details.
PCI Reset.
PCI Stop.
CPU Stop.
PINTB# PINTC# PINTD#
Revision 2.32, September 1, 2004 -10- Pin Descriptions
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VT8231 South Bridge
PCI Bus Interface (continued)
Signal Name Pin # I/O Signal Description
PREQH#
PGNTH#
PREQL#
PGNTL#
HREQ1# / GPI10 Y11 I / IO High Priority Request 1. Device 0 Function 4 RxE5[3] = 1.
HGNT1# / GPO8 W11 O / IO High Priority Grant 1. Device 0 Function 4 RxE5[3] = 1.
HREQ2# / GPI11 V11 I / IO High Priority Request 2. Device 0 Function 4 RxE5[3] = 1.
HGNT2# / GPO9 T10 O / IO High Priority Grant 2. Device 0 Function 4 RxE5[3] = 1.
LREQ1# / GPI12 U10 I / IO Low Priority Request 1. Device 0 Function 4 RxE5[2] = 1.
LGNT1# / GPO10 Y10 O / IO Low Priority Grant 1. Device 0 Function 4 RxE5[2] = 1.
LREQ2# / GPI13 / IOCHRDY W10 I / IO Low Priority Request 2. Device 0 Func 4 RxE5[2]=1, Func 0 Rx67[3]=0
LGNT2# / GPO11 V10 O / IO Low Priority Grant 2. Device 0 Function 4 RxE5[2] = 1.
PCI Slot
PCI Slot
PCI Slot
PCI Slot
C1 O PCI Request. This signal goes to the North Bridge REQ4# input to
request the PCI bus for high priority access. The internal LAN requests the
PCI bus using this signal, so if the LAN subsystem is used, this signal must
be connected (one of the H/LREQ/GNT 1 and 2 pairs provided by the
VT8231 may be used to implement the fifth PCI slot if desired). If the
LAN subsystem is not used, PREQH# / PGNTH# may optionally remain
unconnected.
D3 I PCI Grant. This signal is driven by the North Bridge GNT4# signal to
grant high priority PCI access to the VT8231.
D2 O PCI Request. This signal goes to the North Bridge PREQ# input to
request the PCI bus for normal priority access.
D1 I PCI Grant. This signal is driven by the North Bridge PGNT# output to
grant normal priority PCI access to the VT8231.
REQ/GNT 3
REQ/GNT 2
REQ/GNT 1
REQ/GNT 0
PCI Slot
PCI Slot
On-Board
High Priority
PCI Master
On-Board
High Priority
PCI Master
H REQ/GNT 1
H REQ/GNT 2
L REQ/GNT 1
L REQ/GNT 2
VIA
North Bridge
VT8231
South Bridge
REQ/GNT 4
PREQ/GNT
PREQ/GNT L
PREQ/GNT H
Figure 5. PCI Request / Grant Connections Using the VT8231
Revision 2.32, September 1, 2004 -11- Pin Descriptions
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VT8231 South Bridge
CPU Interface
Signal Name Pin # I/O Signal Description
CPURST
INTR
NMI
INIT#
STPCLK#
SMI#
FERR#
IGNNE#
SLP# / GPO7U6 OD Sleep (F4 RxE4[4] = 1). Used to put the CPU to sleep. Used with slot-1
A20M#
DTD+
DTD-
Note: Connect each of the above signals to 4.7K Ω pullup resistors to VCC3.
U4 OD CPU Reset. The VT8231 asserts CPURST to reset the CPU during power-up.
R6 OD CPU Interrupt. INTR is driven by the VT8231 to signal the CPU that an
interrupt request is pending and needs service.
T5 OD Non-Maskable Interrupt. NMI is used to force a non-maskable interrupt to
the CPU. The VT8231 generates an NMI when SERR# is asserted.
V5 OD Initialization. The VT8231 asserts INIT# if it detects a shut-down special
cycle on the PCI bus or if a soft reset is initiated by the register. See strap on
SUSA# / GPO1 for polarity selection.
V6 OD Stop Clock. STPCLK# is asserted by the VT8231 to the CPU to throttle the
processor clock.
Y5 OD System Management Interrupt. SMI# is asserted by the VT8231 to the CPU
in response to different Power-Management events.
U5 I Numerical Coprocessor Error. This signal is tied to the coprocessor error
signal on the CPU. Internally generates interrupt 13 if active. A threshold of
1.5V or 2.5V is selectable via Device 0 Function 0 Rx67[2].
T6 OD Ignore Numeric Error. This pin is connected to the “ignore error” pin on the
CPU.
CPUs only. Not currently used with socket-7 CPUs.
W5 OD A20 Mask. Connect to A20 mask input of the CPU to control address bit-20
generation. Logical combination of the A20GATE input (from internal or
external keyboard controller) and Port 92 bit-1 (Fast A20). See Device 0
Function 0 Rx59[1].
L2 Analog I CPU DTD (Thermal Diode) Channel Plus. Connect to cathode of first
external temperature sensing diode.
L3 Analog I CPU DTD (Thermal Diode) Channel Minus. Connect to anode of first
external temperature sensing diode.
Revision 2.32, September 1, 2004 -12- Pin Descriptions
WSC# / GPI14V4 I / I Internal APIC Write Snoop Complete. F0 Rx58[6] = 1.
Asserted by the north bridge to indicate that all snoop activity
on the CPU bus initiated by the last PCI-to-DRAM write is
complete and that it is safe to perform an APIC interrupt.
APICD0 / GPO28 W4 O / O Internal APIC Data 0. F0 Rx58[6] = 1.
APICD1 / GPO29Y4 O / O Internal APIC Data 1. F0 Rx58[6] = 1.
APICCLK / GPI9Y3 I / I APIC Clock. F0 Rx58[6] = 1.
Low Pin Count (LPC) Interface
Signal Name Pin # I/O Signal Description
LFRAME#
LDRQ# / GPI15Y8 I / I LPC Data Request. F0 Rx58[5] = 1 and F4 RxE5[7] = 0.
LAD[3-0]
Note: For LPC control, see Device 0 Function 0 Rx58[5] and Rx59[4-3]
Note: Connect the LPC interface LPCRST# (LPC Reset) signal to PCIRST#
W8 O
V7, W7, Y7, V8 IO
LPC Frame.
LPC Address / Data.
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VT8231 South Bridge
LAN Controller - Media Independent Interface (MII)
The internal LAN controller uses the high priority PCI bus request / grant pair (PREQH# / PGNTH#) to request PCI bus access
from the chipset north bridge.
G17 I MII Collision Detect. From the external PHY.
G16 I MII Carrier Sense. Asserted by the external PHY when the media is active.
C20 O MII Management Data Clock. Sent to the external PHY as a timing reference for MDIO
D18 IO MII Management Data I/O. Read from the MDI bit or written to the MDO bit.
C19 I MII Receive Clock. 2.5 or 25 MHz clock recovered by the PHY.
D19
D20
E18
E19
E20 I
F18 I MII Receive Error. Asserted by the PHY when it detects a data decoding error.
F17 I MII Transmit Clock. Always active 2.5 or 25 MHz clock supplied by the PHY.
G20
G19
G18
F20
F19 O MII Transmit Enable. Indicates transmit active from the MII port to the PHY.
I
MII Receive Data. Parallel receive data lines driven by the external PHY synchronous with
I
MRXCLK.
I
I
MII Receive Data Valid.
O
MII Transmit Data. Parallel transmit data lines synchronized to MTXCLK.
O
O
O
Serial EEPROM Interface
Signal Name Pin # I/O Signal Description
EECS#
EECK
EEDO
EEDI
C18 O
E16 O
D17 I Serial EEPROM Data Output. Connect to EEPROM Data Out pin.
E17 O Serial EEPROM Data Input. Connect to EEPROM Data In pin.
Serial EEPROM Chip Select.
Serial EEPROM Clock.
Revision 2.32, September 1, 2004 -15- Pin Descriptions
/ GPI21 / GPO21
For USB interface configuration and control see also Functions 2 and 3 plus Function 0 Rx48[3-2], 4A[1], 4D[1-0], 50[5-4]
B18 IO
A18 IO
B19 IO
A19 IO
B20 IO
A20 IO
C17 IO
B17 IO
C15 I USB Clock. 48MHz clock input for the USB interface
A17 I USB Port 0 Over Current Detect. Port 0 is disabled if this input is low.
D16 I USB Port 1 Over Current Detect. Port 1 is disabled if this input is low
W13 I / IO
/ I / O
Y13 I / IO
/ I / O
USB Port 0 Data +
USB Port 0 Data USB Port 1 Data +
USB Port 1 Data USB Port 2 Data +
USB Port 2 Data USB Port 3 Data +
USB Port 3 Data -
USB Port 2 Over Current Detect. Port 2 is disabled if this input is low. Device 0 Function 4 RxE4[6] = 0 and Power Management I/O Rx4E[4] = 1
USB Port 3 Over Current Detect. Port 3 is disabled if this input is low. Device 0 Function 4 RxE4[6] = 0 and Power Management I/O Rx4E[5] = 1
System Management Bus (SMB) Interface (I2C Bus)
Signal Name Pin # I/O Signal Description
SMBCK1
SMBCK2 / GPIO27R1 IO / IO SMB / I2C Channel 2 Clock†. F4 Rx55[3] = 0.
SMBDT1
SMBDT2 / GPIO26R2 IO / IO SMB / I2C Channel 2 Data†. F4 Rx55[3] = 0.
SMBALRT# / GPI7 T2 I / I SMB Alert. (System Management Bus I/O space Rx08[3] = 1) When the
For SMB interface configuration and control see also Function 4 Rx54[7], 55[3-2], 56[4], 90-93, D2-D6 plus SMB I/O Rx0-F,
HWM I/O Rx48, and PMIO Rx45[1-0]
† Note: SMBus #2 is a slave-only device used to supply status for external Alert-On-LAN (AOL)
R3 IO
T1 IO
SMB / I2C Channel 1 Clock.
SMB / I2C Channel 1 Data.
chip is enabled to allow it, assertion generates an IRQ or SMI interrupt or a
power management resume event. The same pin is used as General Purpose
Input 6 whose value is reflected in Rx48[6] of function 4 I/O space
Revision 2.32, September 1, 2004 -16- Pin Descriptions
UltraDMA Mode: Primary Stop. Stop transfer: Asserted by the host prior to
initiation of an UltraDMA burst; negated by the host before data
is transferred in an UltraDMA burst. Assertion of STOP by the
host during or after data transfer in UltraDMA mode signals the
termination of the burst.
UltraDMA Mode: Secondary Stop. Stop transfer: Asserted by the host prior to
initiation of an UltraDMA burst; negated by the host before data
is transferred in an UltraDMA burst. Assertion of STOP by the
host during or after data transfer in UltraDMA mode signals the
termination of the burst.
P19 I Primary Device DMA Request. Primary
U17 I Secondary Device DMA Request. Secondary
N20 O Primary Device DMA Acknowledge. Primary
L18 O Primary Master Chip Select. This signal corresponds to CS1FX#
on the primary IDE connector.
L19 O Primary Slave Chip Select. This signal corresponds to CS3FX# on
the primary IDE connector.
U18 O Secondary Master Chip Select. This signal corresponds to
CS17X# on the secondary IDE connector.
U19 O Secondary Slave Chip Select. This signal corresponds to CS37X#
on the secondary IDE connector.
M20, M18, M19 O Primary Disk Address. PDA[2:0] are used to indicate which byte
in either the ATA command block or control block is being
accessed.
V20, V18, V19 O Secondary Disk Address. SDA[2:0] are used to indicate which
byte in either the ATA command block or control block is being
accessed.
IO
Primary Disk Data
IO
Secondary Disk Data / ISA Address
Revision 2.32, September 1, 2004 -18- Pin Descriptions
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VT8231 South Bridge
MIDI Interface
Signal Name Pin # I/O Signal Description
MSI
MSO
For MIDI interface configuration and control see also SuperIO RxF9[0], Function 0 Rx6D[2-0], Function 4 Rx40[0], Function 5
Rx18 and I/O Base 2 Rx0, and Function 5/6 Rx42[7,6,1], 43[3-2]
G4 I
J4 O
MIDI Serial In
MIDI Serial Out
AC97 Audio / Modem Interface
Signal Name Pin # I/O Signal Description
ACRST#
ACSYNC
ACSDOUT
ACSDIN0
ACSDIN1
ACSDIN2 / GPIO19G5 I AC97 Serial Data In 2. Function 4, RxE4[5] = 0
ACSDIN3 / GPI15 / LDRQ#Y8 I AC97 Serial Data In 3. Function 4, RxE5[7] = 1
ACBITCLK
For AC97 interface configuration and control see also Functions 5 and 6 plus Function 0 Rx4D[3-2], 50[7-6], PMIO Rx20[13].
G2 O
G1 O
H3 O
H1 I
H2 I
J3 I
AC97 Reset
AC97 Sync
AC97 Serial Data Out
AC97 Serial Data In 0
AC97 Serial Data In 1
AC97 Bit Clock
Game Port Interface
Signal Name Pin # I/O Signal Description
JAX
JAY
JBX
JBY
JAB1 / GPI28G3 I / I
JAB2 / GPO12H5 I / O Joystick A Button 2. Device 0 Function 4 RxE5[4] = 1.
JBB1 / GPI29F1 I / I
JBB2 / GPO13H4 I / O Joystick B Button 2. Device 0 Function 4 RxE5[4] = 1.
For Game Port interface configuration and control see also Game Port I/O registers (port 201h), Function 0 Rx6D[3], Function 4
Rx40[2], and Function 5/6 Rx42[3] and 4A
J1 I
K4 I
K5 I
J2 I
Joystick A X-axis
Joystick A Y-axis
Joystick B X-axis
Joystick B Y-axis
Joystick A Button 1.
Joystick B Button 1.
Revision 2.32, September 1, 2004 -19- Pin Descriptions
See also Parallel Port pin descriptions for optional Floppy Disk interface functionality
L17 O
K17 O
K18 O Motor Control 0. Select motor on drive 0.
J16 O Motor Control 1. Select motor on drive 1
J17 O Drive Select 0. Select drive 0.
K19 O Drive Select 1. Select drive 1
K20 O Direction. Direction of head movement (0 = inward motion, 1 = outward motion)
J18 O Step. Low pulse for each track-to-track movement of the head.
L20 I Index. Sense to detect that the head is positioned over the beginning of a track
H19 O Head Select. Selects the side for R/W operations (0 = side 1, 1 = side 0)
H16 I Track 0. Sense to detect that the head is positioned over track 0.
H20 I Read Data. Raw serial bit stream from the drive for read operatrions.
J19 O Write Data. Encoded data to the drive for write operations.
J20 O Write Gate. Signal to the drive to enable current flow in the write head.
H18 I Disk Change. Sense that the drive door is open or the diskette has been changed
H17 I Write Protect. Sense for detection that the diskette is write protected (causes write
Drive Density Select 0.
Drive Density Select 1.
since the last drive selection.
commands to be ignored)
Revision 2.32, September 1, 2004 -20- Pin Descriptions
Page 27
VT8231 South Bridge
Parallel Port Interface
Signal Name Pin # I/O Signal Description
PINIT# / DIR#B12 IO / O Initialize. Initialize printer. Output in standard mode, I/O in ECP/EPP mode.
STROBE# / ncA11 IO / - Strobe. Output used to strobe data into the printer. I/O in ECP/EPP mode.
AUTOFD# / DRVEN0E11 IO / O Auto Feed. Output used to cause the printer to automatically feed one line after
each line is printed. I/O pin in ECP/EPP mode.
SLCTIN# / STEP#D12 IO / O Select In. Output used to select the printer. I/O pin in ECP/EPP mode.
SLCT / WGATE#E13 I / O Select. Status output from the printer. High indicates that it is powered on.
ACK# / DS1#B14 I / O Acknowledge. Status output from the printer. Low indicates that it has received
the data and is ready to accept new data
ERROR# / HDSEL#F11 I / O Error. Status output from the printer. Low indicates an error condition in the
printer.
BUSY / MTR1#A14 I / O Busy. Status output from the printer. High indicates not ready to accept data.
PE / WDATA#D13 I / O Paper End. Status output from the printer. High indicates that it is out of paper.
PD7 / nc,
PD6 / nc,
PD5 / nc,
PD4 / DSKCHG#,
PD3 / RDATA#,
PD2 / WRTPRT#,
PD1 / TRK00#,
PD0 / INDEX#
As shown by the alternate functions above, in mobile applications the parallel port pins can optionally be selected to function as a
floppy disk interface for attachment of an external floppy drive using the parallel port connector (see Super I/O Configuration
Index F6[5]).
C14
A13
B13
C13
E12
A12
C12
D11
IO / IO / IO / IO / I
IO / I
IO / I
IO / I
IO / I
Parallel Port Data.
Revision 2.32, September 1, 2004 -21- Pin Descriptions
Page 28
VT8231 South Bridge
Serial Port and Infrared Interface
Signal Name Pin # I/O Signal Description
TXD
RXD
IRTX / GPO14 R8 O / O Infrared Transmit. IR transmit data out (Function 4 RxE5[5] = 0).
IRRX / GPO15 U8 I / O Infrared Receive. IR receive data in (Function 4 RxE5[5] = 0).
IRRX2 / GPIOB T8 I Infrared Receive. IR receive data in (see FIR I/O Rx33 and 34)
RTS#
CTS#
DTR#
DSR#
DCD#
RI#
B15 O Transmit Data. Serial port transmit data out.
E14 I Receive Data. Serial port receive data in.
A15 O Request To Send. Indicator that the serial output port is ready to transmit data.
Typically used as hardware handshake with CTS# for low level flow control.
Designed for direct input to external RS-232C driver.
B16 I Clear To Send. Indicator to the serial port that an external communications
device is ready to receive data. Typically used as hardware handshake with RTS#
for low level flow control. Designed for input from external RS-232C receiver.
A16 O Data Terminal Ready. Indicator that serial port is powered, initialized, and
ready. Typically used as hardware handshake with DSR# for overall readiness to
communicate. Designed for direct input to external RS-232C driver.
D14 I Data Set Ready. Indicator to serial port that an external serial communications
device is powered, initialized, and ready. Typically used as hardware handshake
with DTR# for overall readiness to communicate. Designed for direct input from
external RS-232C receiver.
D15 I Data Carrier Detect. Indicator to serial port that an external modem is detecting
a carrier signal (i.e., a communications channel is currently open). In direct
connect environments, this input will typically be driven by DTR# as part of the
DTR/DSR handshake. Designed for direct input from external RS-232C receiver.
C16 I Ring Indicator. Indicator to serial port that an external modem is detecting a ring
condition. Used by software to initiate operations to answer and open the
communications channel. Designed for direct input from external RS-232C
receiver (whose input is typically not connected in direct connect environments).
Revision 2.32, September 1, 2004 -22- Pin Descriptions
IRQ1 / MSCKN2 I
IRQ8# / GPI1V3 I Interrupt 8 (optional external RTC). Enabled if Rx51[3]
IRQ12 / MSDTN4 I
IRQ14
IRQ15
SPKR
W18, V17, Y17, W16,
V15, Y15, W14, T15,
U15, U16, V14, W15,
Y16, V16, W17, Y18
T11, R11, U11, U12,
Y12, W12, V12, R12
Y13
W13
V13, U13,
T13,
Y14,
W9 IO Memory Read. Command to memory slave to indicate that
Y9 IO Memory Write. Command to memory slave to indicate that
T14 I
U14 I
U9 O Speaker Drive. Output of internal timer/counter 2.
O
System Address Bus. Allows access to physical memory
devices (e.g., BIOS ROMs) up to 4 Mbytes. F4 RxE4[6] =
O
1.
IO System Address Bus. These address lines are used to
interface to BIOS ROMs but may also be used to implement
a subset of the ISA bus if required. SA[19-16] are connected
to ISA bus SA[19-16] directly. SA[19-17] are also
connected to LA[19-17] of the ISA bus.
SA17 strap – 0/1 = Enable / Disable Auto Reboot
SA16 strap – 0/1 = Disable / Enable LPC ROM
IO System Data. SD[7:0] provide the data path for BIOS
ROMs and other 8-bit devices residing on the ISA bus.
slave devices to indicate that the slave may drive data on to
the ISA data bus.
slave devices to indicate that the slave may latch data from
the ISA data bus.
it may drive data onto the ISA data bus.
it may latch data from the ISA data bus.
pulled high on the motherboard. Devices on the ISA Bus
assert IOCHRDY low to indicate that additional time (wait
states) is required to complete the cycle.
KBCK / A20GATE M4 IO / I MultiFunction Pin (Internal keyboard controller enabled by F0 Rx51[0])
Rx51[0]=1 Keyboard Clock. From internal keyboard controller Rx51[0]=0 Gate A20. Input from external keyboard controller.
KBDT / KBRC N1 IO / I MultiFunction Pin (Internal keyboard controller enabled by F0 Rx51[0])
Rx51[0]=1 Keyboard Data. From internal keyboard controller. Rx51[0]=0 Keyboard Reset. From external keyboard controller (KBC)
for CPURST# generation
KBCS# / ROMCS#T9 O / O Keyboard Chip Select (Rx51[0]=0). To external keyboard controller chip.
For Keyboard Controller configuration and control see also I/O Ports 60h and 64h, Configuration Index ports 3F0h and 3F1h (and
configuration registers at offsets E0-E6h) plus Function 0 Rx51[2-0] and PMIO Rx20[2], 30[9], 34[9], and 38[7].
Chip Selects
Signal Name Pin # I/O Signal Description
ROMCS# / KBCS# T9 O / O ROM Chip Select (Rx51[0]=1). Chip Select to the BIOS ROM. See also
Device 0 Rx40[5-4] and Rx41.
MCCS# / GPO17 / strapW6 O / IO Microcontroller Chip Select (Device 0 Function 4 RxE4[3] = 0). Asserted
during read or write accesses to I/O ports 62h or 66h.
Strap: 0/1 = Enable / Disable CPU Frequency Strapping
PCS# / GPO16 Y6 O / IO / IO Programmable Chip Select. (Device 0 Function 4 RxE4[2] = 0). Asserted
during I/O cycles to programmable read or write ISA I/O port ranges.
Revision 2.32, September 1, 2004 -24- Pin Descriptions
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VT8231 South Bridge
General Purpose Inputs
Signal Name Pin # I/O Signal Description
GPI0 [VBAT]
GPI1 / IRQ8# [VCCSUS] V3 I General Purpose Input 1. F0 Rx51[3] = 1.
GPI2 / EXTSMI# [VCCSUS] W1 I / IO General Purpose Input 2. (Use as GPI -or- as EXTSMI#)
GPI3 / RING# [VCCSUS] U3 I / I General Purpose Input 3. (Use as GPI -or- as RING#)
GPI4 / LID [VCCSUS] V2 I / I General Purpose Input 4. (Use as GPI -or- as LID)
GPI5 / BATLOW# [VCCSUS] T3 I / I General Purpose Input 5. (Use as GPI -or- as BATLOW#)
GPI6 / PME# [VCCSUS] U1 I / I General Purpose Input 6. (Use as GPI -or- as PME#)
GPI7 / SMBALRT# [VCCSUS] T2 I / I General Purpose Input 7. (Use as GPI -or- as SMBALRT#)
GPI8 / INTRUDER# [VBAT] F3 I / I General Purpose Input 8. (Use as GPI -or- as INTRUDER#)
GPI9 / APICCLK Y3 I / I General Purpose Input 9. Rx58[6]=0
GPI10 / HREQ1# Y11 I / I General Purpose Input 10. F4 RxE5[3]=1
GPI11 / HREQ2# V11 I / I General Purpose Input 11. F4 RxE5[3]=1
GPI12 / LREQ1# U10 I / I General Purpose Input 12. F4 RxE5[2]=1
GPI13 / LREQ2# / IOCHRDY W10 I / I / I General Purpose Input 13. F4 RxE5[2]=1, F0 Rx67[3]=0
GPI14 / WSC# V4 I / I General Purpose Input 14. Rx58[6]=0
GPI15 / LDRQ# / ACSDIN3 Y8 I / I / I General Purpose Input 15. Rx58[5]=0 & F4 RxE5[7]=0
GPI16 / CPUMISS V1 I / I General Purpose Input 16. (Use as GPI -or- as CPUMISS)
GPI17 / AOLGPI / THRM P3 I / I / I General Purpose Input 17. F4 Rx40[7]=0
GPI18 / GPO18 / FAN2 / SLPBTN# K3 I / O / I / I General Purpose Input 18. F4 RxE5[0]=0
GPI19 / GPO19 / ACSDIN2 G5 I / O / I General Purpose Input 19. F4 RxE5[1]=0 & E4[5]=0
GPI20 / GPO20 / LA20 / USBOC2# W13 I / OD / IO / I General Purpose Input 20. F4 RxE4[6]=0 & PMIO 4E[4]=1
GPI21 / GPO21 / LA21 / USBOC3# Y13 I / OD / IO / I General Purpose Input 21. F4 RxE4[6]=0 & PMIO 4E[5]=1
GPI22 / GPO22 / IOR# U7 I / OD / IO General Purpose Input 22. F4 RxE4[7]=0 & PMIO 4E[6]=1
GPI23 / GPO23 / IOW# T7 I / OD / IO General Purpose Input 23. F4 RxE4[7]=0 & PMIO 4E[7]=1
GPI24 / GPO24 / GPIOA Y2 I / OD / IO General Purpose Input 24. F4 RxE6[0]=0
GPI25 / GPO25 / GPIOC
/ CHSINOUT
GPI26 / GPO26 / SMBDT2 [VCCSUS] R2 I / OD / IO General Purpose Input 26. F4 Rx55[2]=1 & 55[3]=0
GPI27 / GPO27 / SMBCK2 [VCCSUS] R1 I / OD / IO General Purpose Input 27. F4 Rx55[2]=1 & 55[3]=0
GPI28 / JAB1 G3 I / I General Purpose Input 28. (Use as GPI -or- as JAB1)
GPI29 / JBB1 F1 I / I General Purpose Input 29. (Use as GPI -or- as JBB1)
GPI30 / GPO30 / GPIOD Y1 I / OD / IO General Purpose Input 30. F4 RxE6[6]=0
GPI31 / GPO31 / GPIOE W3 I / OD / IO General Purpose Input 31. F4 RxE6[7]=0
Note: See also Power Management I/O Registers Rx50 and 52 for GPI pin status and SCI/SMI select.
Note. The state of each GPI pin may be read at the corresponding bit of PMIO Rx4B-48.
Note: Each of the pins above may be used as a GPI pin or as one of the alternate functions listed above for that pin. Descriptions
of these alternate functions are given elsewhere in the pin descriptions section of this document. If a control bit must be set to
enable / select each of the above pins for use as a General Purpose Input, the bit setting is listed above. If no bit setting is listed,
either function may be used (no bit setting is required to select the GPI function), however note that typical designs may use the
pin as one or the other (but not both GPI and alternate function at the same time).
F4 I
J5 I / OD / IO
/ IO
General Purpose Input 0.
General Purpose Input 25. F4 RxE6[1]=0 & E5[6]=0
(F4 RxE5[6]=1 to enable CHSINOUT function on this pin)
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VT8231 South Bridge
General Purpose Outputs
Signal Name Pin # I/O Signal Description
GPO0 / SLOWCLK [VCCSUS] R4 O / O General Purpose Output 0. (Func 4 Rx54[1-0] = 00).
Output value determined by PMU I/O Rx4C[0]
GPO1 / SUSA# / strap [VCCSUS] P1 O / O / I General Purpose Output 1. F4 Rx54[2]=1
GPO2 / SUSB# [VCCSUS] P2 O / O General Purpose Output 2. F4 Rx54[3]=1
GPO3 / SUSST1# [VCCSUS] N5 O / O General Purpose Output 3. F4 Rx54[4]=1
GPO4 / SUSCLK [VCCSUS] W2 O / O General Purpose Output 4. F4 Rx55[1]=1
GPO5 / CPUSTP# P4 O / O General Purpose Output 5. F4 RxE4[0]=1
GPO6 / PCISTP# T4 O / O General Purpose Output 6. F4 RxE4[1]=1
GPO7 / SLP# U6 O / O General Purpose Output 7. F4 RxE4[4]=1
GPO8 / HGNT1# W11 O / O General Purpose Output 8. F4 RxE5[3]=1
GPO9 / HGNT2# T10 O / O General Purpose Output 9. F4 RxE5[3]=1
GPO10 / LGNT1# Y10 O / O General Purpose Output 10. F4 RxE5[2]=1
GPO11 / LGNT2# V10 O / O General Purpose Output 11. F4 RxE5[2]=1
GPO12 / JAB2 H5 O / I General Purpose Output 12. F4 RxE5[4]=1 & F0Rx53[7]=0
GPO13 / JBB2 H4 O / I General Purpose Output 13. F4 RxE5[4]=1 & F0Rx53[7]=0
GPO14 / IRTX R8 O / O General Purpose Output 14. F4 RxE5[5]=1
GPO15 / IRRX U8 O / I General Purpose Output 15. F4 RxE5[5]=1
GPO16 / PCS# Y6 O / O General Purpose Output 16. F4 RxE4[2]=1
GPO17 / MCCS# W6 O / O General Purpose Output 17. F4 RxE4[3]=1
GPO18 / GPI18 / FAN2 / SLPBTN# K3 O / I / I / I General Purpose Output 18. F4 RxE5[0]=1
GPO19 / GPI19 / ACSDIN2 G5 O / I / I General Purpose Output 19. F4 RxE4[5]=1 & RxE5[1]=1
GPO20 / GPI20 / LA20 / USBOC2# W13 OD / I / IO / I General Purpose Output 20. F4 RxE4[6]=0
GPO21 / GPI21 / LA21 / USBOC3# Y13 OD / I / IO / I General Purpose Output 21. F4 RxE4[6]=0
GPO22 / GPI22 / IOR# U7 OD / I / IO General Purpose Output 22. F4 RxE4[7]=0
GPO23 / GPI23 / IOW# T7 OD / I / IO General Purpose Output 23. F4 RxE4[7]=0
GPO24 / GPI24 / GPIOA Y2 OD / I / IO General Purpose Output 24. F4 RxE6[0]=1
GPO25 / GPI25 / GPIOC /CHSINOUT J5 OD / I / IO / IO General Purpose Output 25. F4 RxE6[1]=1 & RxE5[5]=0
GPO26 / GPI26 / SMBDT2 [VCCSUS] R2 OD / I / IO General Purpose Output 26. F4 Rx55[3-2]=11
GPO27 / GPI27 / SMBCK2 [VCCSUS] R1 OD / I / IO General Purpose Output 27. F4 Rx55[3-2]=11
GPO28 / APICD0 W4 O / O General Purpose Output 28. Rx58[7-6]=00
GPO29 / APICD1 Y4 O / O General Purpose Output 29. Rx58[7-6]=00
GPO30 / GPI30 / GPIOD Y1 OD / I / IO General Purpose Output 30. F4 RxE6[6]=1
GPO31 / GPI31 / GPIOE W3 OD / I / IO General Purpose Output 31. F4 RxE6[7]=1
Note: See also Power Management I/O Registers Rx4C-4F to set GPO pin output values. General purpose outputs 20-27 and 30-
31 are OD, so to use these pins as input pins, a one must be written to the corresponding bit of PMIO Rx4C-4F.
Revision 2.32, September 1, 2004 -26- Pin Descriptions
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VT8231 South Bridge
General Purpose I/Os
Signal Name Pin # I/O Signal Description
GPIOA / GPI24 / GPO24 Y2 IO / I / O General Purpose I/O A / 24. (F4 RxE6[0] defines as GPI or GPO)
GPIOB / IRRX2 T8 IO / I General Purpose I/O B. (See FIR I/O Rx33 and 34)
GPIOC / GPI25 / GPO25
/ CHSINOUT
GPIOD / GPI30 / GPO30Y1 IO / I / O General Purpose I/O D / 30. (F4 RxE6[6] defines as GPI or GPO)
GPIOE / GPI31 / GPO31W3 IO General Purpose I/O E / 31. (F4 RxE6[7] defines as GPI or GPO)
J5 IO / I / O
/ IO
General Purpose I/O C / 25. (F4 RxE6[1] defines as GPI or GPO)
Hardware Monitoring
Signal Name Pin # I/O Signal Description
UIC1
UIC2
UIC3
UIC4
UIC5
DTD+
DTDVREF
FAN1
FAN2 / SLPBTN# / GPI18 / GPO18 K3 I / I / I / O Fan Speed Monitor 2. (3.3V only) (F4 RxE5[0] = 0)
For HWM configuration and control, see also HWM I/O Space Registers on page 113 plus Function 4 Rx45[2], 70, and 74
M1 Analog I Universal Input Channel. For temperature / voltage monitoring.
M3 Analog I Universal Input Channel. For temperature / voltage monitoring.
M2 Analog I Universal Input Channel. For temperature / voltage monitoring.
L4 Analog I Universal Input Channel. For temperature / voltage monitoring.
L1 Analog I Universal Input Channel. For temperature / voltage monitoring.
L2 Analog I
L3 Analog I
K1 O
K2 I Fan Speed Monitor 1. (3.3V only)
CPU DTD (Thermal Diode) Channel Plus.
CPU DTD (Thermal Diode) Channel Minus.
Voltage Reference for Thermal Sensing (2.2V ±5%)
Revision 2.32, September 1, 2004 -27- Pin Descriptions
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VT8231 South Bridge
Power Management and External State Monitoring
Signal Name Pin # I/O Signal Description
PME# / GPI6U1 I / I Power Management Event. (1K PU to VCCS if not used)
EXTSMI# / GPI2W1 IOD / I External System Management Interrupt. When enabled to allow it, a
falling edge on this input causes an SMI# to be generated to the CPU to
enter SMI mode. (10K PU to VCCS if not used) (3.3V only)
SMBALRT# / GPI7 T2 I / I SMB Alert (System Management Bus I/O space Rx08[3] = 1). When the
chip is enabled to allow it, assertion generates an IRQ or SMI or power
management event. (10K PU to VCCS if not used)
THRM / AOLGPI / GPI17 P3 I / I / I Monitor Input - Thermal Alarm. (F4 Rx40[7]=0) (1K PU to VCCS if
not used)
LID / GPI4 V2 I / I
RING# / GPI3 U3 I / I Monitor Input – Modem Ring. May be connected to external modem
BATLOW# / GPI5 T3 I / I Monitor Input - Battery Low. (10K PU to VCCS if not used)
CPUMISS / GPI16V1 I / I Monitor Input - CPU Missing. Indicates whether the CPU is plugged in
AOLGPI / GPI17 / THRMP3 I / I / I Monitor Input - Awake On LAN External Event. F4 Rx40[7]=1
INTRUDER# / GPI8F3 I / I
RSMRST#
SUSA# / GPO1 / strap P1 O / O / I Suspend Plane A Control (Function 4 Rx54[2]=0). Asserted during
SUSB# / GPO2 P2 O / O Suspend Plane B Control (Function 4 Rx54[3]=0). Asserted during
SUSC# / GPON3 O / O Suspend Plane C Control. Asserted during power management STD
SUSST1# / GPO3 N5 O / O Suspend Status 1 (Function 4 Rx54[4] = 0). Typically connected to the
SUSCLK / GPO4W2 O / O Suspend Clock (Function 4 Rx55[1]=0). 32.768 KHz output clock for
F2 I Resume Reset. Resets the internal logic connected to the VCCS power
Monitor Input - Notebook Computer Display Lid Open / Closed.
Used by the Power Management subsystem to monitor the opening and
closing of the display lid of notebook computers. Can be used to detect
either low-to-high and/or high-to-low transitions to generate an SMI#.
The VT8231 performs a 200 usec debounce of this input if Function 4
Rx40[5] is set to 1. (10K PU to VCCS if not used)
circuitry to allow the system to be re-activated by a received phone call.
(10K PU to VCCS if not used)
correctly.
Monitor Input – Chassis Intrusion.
plane and also resets portions of the internal RTC logic.
power management POS, STR, and STD suspend states. Used to control
the primary power plane. (10K PU to VCCS if not used)
power management STR and STD suspend states. Used to control the
secondary power plane. (10K PU to VCCS if not used)
suspend state. Used to control the tertiary power plane. Also connected to
ATX power-on circuitry.
North Bridge to provide information on host clock status. Asserted when
the system may stop the host clock, such as Stop Clock or during POS,
STR, or STD suspend states. Connect 10K PU to VCCS.
use by the North Bridge (e.g., Apollo MVP3 or MVP4) for DRAM refresh
purposes. Stopped during Suspend-to-Disk and Soft-Off modes. Connect
10K PU to VCCS.
Revision 2.32, September 1, 2004 -28- Pin Descriptions
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VT8231 South Bridge
Resets, Clocks, and Clock Control
Signal Name Pin # I/O Signal Description
PWRGD
PWRBTN#
SLPBTN# /
FAN2 /
GPIO18
PCIRST#
RTCX1
RTCX2
OSC
SLOWCLK /
GPO0
CPUSTP# /
GPO5
PCISTP# /
GPO6
E2 I Power Good. Connected to the PWRGOOD signal on the Power Supply.
U2 I Power Button. Used by the Power Management subsystem to monitor an
external system on/off button or switch. The VT8231 performs a 200us
debounce of this input if Function 4 Rx40[5] is set to 1. (3.3V only)
K3 I
E4 O PCI Reset. Active low reset signal for the PCI bus. The VT8231 will assert
E3 I RTC Crystal Input: 32.768 KHz crystal or oscillator input. This input is
F5 O RTC Crystal Output: 32.768 KHz crystal output
T12 I Oscillator. 14.31818 MHz clock signal used by the internal Timer.
R4 O Slow Clock. Frequency selectable if PMU function 4 Rx54[1-0] is nonzero
P4 O /
T4 O /
Sleep Button (Function 4 Rx40[6] = 0). Used by the power management
/ I
subsystem to monitor an external system sleep button or switch. Connect to
/ IO
VCC if not used.
this pin during power-up or from the control register.
used for the internal RTC and for power-well power management logic.
(set to 01, 10, or 11).
CPU Clock Stop (Function 4 RxE4[0] = 0). Signals the system clock
O
generator to disable the CPU clock outputs. Not connected if not used. See
also PMU I/O Rx2C[3].
PCI Clock Stop (Function 4 RxE4[1] = 0). Signals the system clock
O
generator to disable the PCI clock outputs. Not connected if not used.
Revision 2.32, September 1, 2004 -29- Pin Descriptions
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VT8231 South Bridge
Power and Ground
Signal Name Pin # I/O Signal Description
VCC (27 Pins)F7, F9, F12-F13, F15,
G6, G8-G10, G12,
H6, J6, J15, K15,
L6, M6, M15, N6,
P8-P9, P11-P13, P15,
R7, R9-R10, R13-R15
GND (27 Pins) G7, G11, G14, H15,
J8-J13, K6, K8-K13,
L8-L13, L15, M8-M13,
N15, P7, P10, P14
VCCSUS
VBAT
VCCHWM
GNDHWM
VCCMII
VCCLAN
GNDLAN
VCCPLL
GNDPLL
VCCUSB
GNDUSB
P5, P6 P Suspend Power. Always available unless the mechanical switch of the
E1 P RTC Battery. Battery input for internal RTC. Signals powered by or
M5 P Hardware Monitor / Game Port Power. Power for hardware monitoring
L5 P Hardware Monitor / Game Port Ground. Connect to GND through a
F16, K16 P LAN MII Power. Power for LAN Media Independent Interface (interface to
G15 P LAN Power. Connect to VCC through a ferrite bead.
G13 P LAN Ground. Connect to GND through a ferrite bead.
L16 P PLL Power. Power for internal UDMA PLL. Connect to VCC through a
M16 P PLL Ground. Connect to GND through a ferrite bead.
E15 P USB Differential Output Power. Power for USB differential outputs
F14 P USB Differential Output Ground. Connect to GND through a ferrite bead.
P Core Power. 3.3V nominal (3.15V to 3.45V). This supply is turned on only
when the mechanical switch on the power supply is turned on and the
PWRON signal is conditioned high. These pins should be connected to the
same voltage as the CPU I/O circuitry. Internally connected to hardware
monitoring system voltage detection circuitry for 3.3V monitoring.
P Ground. Connect to primary motherboard ground plane.
power supply is turned off. If the “soft-off” state is not implemented, then
this pin can be connected to VCC. Signals powered by or referenced to this
plane are: SMBCK1/DT1, KBCK/DT, MSCK/DT, PWRBTN#, SUSC#,
GPO0 / SLOWCLK, GPO1 / SUSA#, GPO2 / SUSB#, GPO3 / SUSST1#,
GPO4 / SUSCLK, GPI1, GPI2 / EXTSMI#, GPI3 / RING#, GPI4 / LID,
GPI5 / BATLOW#, GPI6 / PME#, GPI7 / SMBALRT#, GPI16 / CPUMISS,
GPI17 / AOLGPI / THRM, GPIO26 / SMBDT2, GPIO27 / SMBCK2
referenced to this plane are: RTCX1, RTCX2, PWRGD, RSMRST#, GPI0,
and INTRUDER#.
subsystem (voltage monitoring, temperature monitoring, and fan speed
monitoring) and game port pins. Connect to VCC through a ferrite bead.
Signals powered by or referenced to this plane are: UIC[5:1], DTD+/-,
FAN1, FAN2 / SLPBTN# / GPIO18, JAX/Y, JBX/Y, JAB1/2 and JBB1/2.
ferrite bead.
external PHY). Connect to VCC through a ferrite bead. Signals powered by
or referenced to this plane are: MCRS, MCOL, MDCK, MDIO, MTXD[3:0],
MTXENA, MTXCLK, MRXERR, MRXCLK, MRXDV, and MRXD[3:0]
ferrite bead.
(USBP0+, P0-, P1+, P1-, P2+, P2-, P3+, P3-). Connect to VCC through a
ferrite bead.
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VT8231 South Bridge
REGISTERS
Register Overview
The following tables summarize the configuration and I/O
registers of the VT8231. These tables also document the
power-on default value (“Default”) and access type (“Acc”)
for each register. Access type definitions used are RW
(Read/Write), RO (Read/Only), “—” for reserved / used
(essentially the same as RO), and RWC (or just WC) (Read /
Write 1’s to Clear individual bits). Registers indicated as RW
may have some read/only bits that always read back a fixed
value (usually 0 if unused); registers designated as RWC or
WC may have some read-only or read write bits (see
individual register descriptions for details).
Detailed register descriptions are provided in the following
section of this document. All offset and default values are
shown in hexadecimal unless otherwise indicated
Table 2. Memory Mapped Registers
FEC00000 APIC Index (8-bit)
FEC00010 APIC Data (32-bit)
FEC00020 APIC IRQ Pin Assertion (8-bit)
FEC00040 APIC EOI (8-bit)
CFC-CFF PCI Configuration Data 0000 1100 1111 11xx
D00-FFFF -available for system use-
* On-Chip Super-I/O Functions – PC-Standard Port Addresses
200-20F Game Port
2E8-2EF COM4
2F8-2FF COM2
378-37F Parallel Port (Standard & EPP)
3E8-3EF COM3
3F0-3F1 Configuration Index / Data
3F0-3F7 Floppy Controller
3F8-3FF COM1
778-77A Parallel Port (ECP Extensions)
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VT8231 South Bridge
Table 5. Registers
Legacy I/O Registers
Master DMA Controller Registers Default Acc
Port
00 Channel 0 Base & Current Address RW
01 Channel 0 Base & Current Count RW
02 Channel 1 Base & Current Address RW
03 Channel 1 Base & Current Count RW
04 Channel 2 Base & Current Address RW
05 Channel 2 Base & Current Count RW
06 Channel 3 Base & Current Address RW
07 Channel 3 Base & Current Count RW
08 Status / Command RW
09 Write Request
60 Keyboard Controller Data RW
61 Misc Functions & Speaker Control RW
64 Keyboard Ctrlr Command / Status RW
Port
CMOS / RTC / NMI Registers Default Acc
70 CMOS Memory Address & NMI Disa
71 CMOS Memory Data (128 bytes) RW
74 CMOS Memory Address
75 CMOS Memory Data (256 bytes) RW
NMI Disable is port 70h (CMOS Memory Address) bit-7.
RTC control occurs via specific CMOS data locations (0-Dh).
Ports 72-73 may be used to access all 256 locations of CMOS.
Ports 74-75 may be used to access CMOS if the internal RTC
is disabled.
C0 Channel 0 Base & Current Address RW
C2 Channel 0 Base & Current Count RW
C4 Channel 1 Base & Current Address RW
C6 Channel 1 Base & Current Count RW
C8 Channel 2 Base & Current Address RW
CA Channel 2 Base & Current Count RW
CC Channel 3 Base & Current Address RW
CE Channel 3 Base & Current Count RW
D0 Status / Command RW
D2 Write Request
D4 Write Single Mask
D6 Write Mode
D8 Clear Byte Pointer FF
DA Master Clear
DC Clear Mask
DE Read / Write Mask RW
WO
WO
WO
WO
WO
WO
RW
RW
Revision 2.32, September 1, 2004 -32- Register Overview
values E0-EF) accessible if Function 0 PCI Configuration
register Rx51[1] = 1. Super-I/O configuration registers
(index values F0-FF) accessible if Function 0 PCI
Configuration register Rx50[2] = 1.
Super-IO / KBC Config Registers (Indexed via Port 3F0/1)
Reserved DefaultAcc
Offset
00-DF -reserved- --RO
Offset
Keyboard Ctrlr Cfg (Rx51[1]=1) DefaultAcc
E0 Keyboard / Mouse Wakeup Enable
E1 Keyboard Scan Code Reference Set 0
E2 Keyboard Scan Code Reference Set 1 00
E3 Keyboard Scan Code Reference Set 2 00
E4 Keyboard Scan Code Reference Set 3 00
E5 Keyboard Scan Code Reference Set 4 00
E6 PS/2 Mouse Button Status Scan Code
E7-EF -reserved- --RO
Offset
Super-I/O Config (Rx50[2]=1) DefaultAcc
F0 Super-I/O Device ID
F1 Super-I/O Device Revision
F2 Function Select
F3 Power Down Control 00
F4 Serial Port Base Addr (def = 3F8-F)
F5 -reserved- -- RO
F6 Parallel Port Base Addr (def = 378-F)
F7 Floppy Ctrlr Base Addr (def = 3F0-7)
F8 -reserved- -- RO
F9 Serial Port Control 00
FA Parallel Port Control 00
FB Floppy Controller Control 00
FC Floppy Controller Drive Type 00
FD -reserved- -- RO
FE Test Mode A (Do Not Program) 00
FF Test Mode B (Do Not Program) 2 00
80RW
F0RW
RW
RW
RW
RW
09RW
3C
01
03 RW
FE RW
DE RW
FC RW
RO
RO
RW
RW
RW
RW
RW
RW
RW
Super-I/O I/O Ports
Offset
00-01 -reserved- 00 --
Offset
Offset
Floppy Disk Controller (3F0-3F7) Default Acc
02 FDC Command -- RW
03 -reserved- 00 -04 FDC Main Status -04 FDC Data Rate Select
05 FDC Data -- RW
06 -reserved- 00 -07 Diskchange Status --
Parallel Port (378-37F typical) Default Acc
00 Parallel Port Data -- RW
01 Parallel Port Status -02 Parallel Port Control -- RW
03 EPP Address RW
04 EPP Data Port 0 RW
05 EPP Data Port 1 RW
06 EPP Data Port 2 RW
07 EPP Data Port 3 RW
400h ECP Data / Configuration A RW
401h ECP Configuration B RW
402h ECP Extended Control RW
Serial Port (COM1=3F8, 3=3E8) Default Acc
0 Transmit (Wr) / Receive (Rd) Buffer RW
1 Interrupt Enable RW
2 FIFO Control
2 Interrupt Status
3 UART Control RW
4 Handshake Control RW
5 UART Status RW
6 Handshake Status RW
7 Scratchpad RW
9-8 Baud Rate Generator Divisor RW
A-F -undefined- --
RO
02 WO
RO
RO
WO
RO
Revision 2.32, September 1, 2004 -33- Register Overview
Page 40
VT8231 South Bridge
Fast IR Registers (I/O Space)
Fast IR DefaultAcc
Offset
0-F -reserved- 00--
11-10 Infrared Configuration 0 0000RW
12 Infrared SIR BOF
13 Infrared SIR EOF
14 -reserved- 00--
15 Infrared Status and Control 0 00RW
17-16 Infrared Status 1 0000
19-18 Infrared Configuration 1 0000RW
Configuration Space PCI-to-ISA Bridge-Specific Registers
ISA Bus Control DefaultAcc
Offset
40 ISA Bus Control 00 RW
41 BIOS ROM Decode Control 00 RW
42 Line Buffer Control 00 RW
43 Delay Transaction Control 00 RW
44 ISA PNP DMA Request Control 00 RW
45 ISA PNP IRQ Routing Control 1 00 RW
46 ISA PNP IRQ Routing Control 2 00 RW
47 ISA PNP IRQ Routing Control 3 00 RW
Offset
PCI Bus ArbitrationControl DefaultAcc
48 Grant Timeout Select 1 00 RW
49 Grant Timeout Select 2 00 RW
4A PCI Master Arbitration Control 00 RW
4B -reserved- 00 —
Offset
Miscellaneous Control DefaultAcc
4C IDE Interrupt Routing 00 RW
4D External APIC IRQ Output Control 00 RW
4E Internal RTC Test Mode 00 RW
4F PCI Bus & CPU Interface Control 00 RW
1106
8231
0087 RW
0200 WC
nn
01
06
80
C0
RO
RO
RO
RO
RO
RO
RO
Offset
Offset
Offset
Offset
5A-5B -reserved- 00 —
Offset
5D-5C PCS0# I/O Port Address 0000 RW
Offset
6B-6A Fast IR I/O Base
Offset
7D-FF -reserved- 00 —
Function ControlDefaultAcc
50 Function Control 1 00 RW
51 Function Control 2 00 RW
Serial IRQ & PC/PCI Control DefaultAcc
52 Serial IRQ Control 00 RW
53 Reserved (Do Not Program) 00 RW
Plug and Play Control DefaultAcc
54 PCI Interrupt Polarity 00 RW
55 PnP Routing for PCI INTA 00 RW
56 PnP Routing for PCI INTB-C 00 RW
57 PnP Routing for PCI INTD 00 RW
Miscellaneous Control DefaultAcc
58 Miscellaneous Control 0
59 Miscellaneous Control 1 00 RW
Programmable Chip Select ControlDefaultAcc
5F-5E PCS1# I/O Port Address 0000 RW
61-60 PCS2# I/O Port Address 0000 RW
63-62 PCS3# I/O Port Address 0000 RW
65-64 PCSn# I/O Port Address Mask 0000 RW
66 PCSn# Control 00 RW
Fast IR ControlDefaultAcc
67 Fast IR, FERR, IOCHRDY Config
68-69 -reserved- 00 —
MiscellaneousDefaultAcc
6C ISA Positive Decoding Control 1 00 RW
6D ISA Positive Decoding Control 2 00 RW
6E ISA Positive Decoding Control 3 00 RW
6F ISA Positive Decoding Control 4 00 RW
73-70 Subsystem ID Write n/a WO
74-77 -reserved- 00 —
79-78 PnP IRQ/DRQ Test (do not program)00 RW
7A IDE / USB Test (do not program) 00 RW
7B PLL Test (do not program) 00 RW
7C I/O Pad Control 00 RW
40
08
0001
RW
RW
RW
Revision 2.32, September 1, 2004 -35- Register Overview
Page 42
VT8231 South Bridge
PCI Device 0 Function 1 Registers – IDE Controller
Configuration Space IDE Header Registers
PCI Configuration Space Header DefaultAcc
Offset
1-0 Vendor ID
3-2 Device ID
5-4 Command
7-6 Status
8 Revision ID
9 Programming Interface
A Sub Class Code
B Base Class Code
C -reserved- (cache line size) 00 —
D Latency Timer 00
E Header Type 00 RO
F Built In Self Test (BIST) 00 RO
13-10 Base Address – Pri Data / Command
17-14 Base Address – Pri Control / Status
1B-18 Base Address – Sec Data / Command
1F-1C Base Address – Sec Control / Status
23-20 Base Address – Bus Master Control
24-2F -reserved- (unassigned) 00 —
30-33 -reserved- (expan ROM base addr) 00 —
34 Capability Pointer
35-3B -reserved- (unassigned) 00 —
3C Interrupt Line
3D Interrupt Pin
3E Minimum Grant 00 RO
3F Maximum Latency 00 RO
Configuration Space IDE-Specific Registers
Configuration Space IDE Registers DefaultAcc
Offset
40 IDE Chip Enable
41 IDE Configuration 1
42 IDE Configuration 2
43 IDE FIFO Configuration
44 IDE Miscellaneous Control 1
45 IDE Miscellaneous Control 2 00 RW
46 IDE Miscellaneous Control 3
4B-48 IDE Drive Timing Control
4C IDE Address Setup Time
4D -reserved- (do not program) 00 RW
4E-4F -reserved- 00 —
1106
0571
0080
0290 RW
nn
85 RW
01
01
000001F0
000003F4
00000170
00000374
0000CC01 RW
C0
0E RW
01
08
06
C0
0A
68
C0
A8A8A8A8
FF
RO
RO
RO
RO
RO
RO
RW
RO
RO
RO
RO
RO
RO
RW
RW
RW
RW
RW
RW
RW
RW
Configuration Space IDE-Specific Registers (continued)
Revision 2.32, September 1, 2004 -42- Register Overview
RO
RO
RO
Page 49
VT8231 South Bridge
I/O Registers – SoundBlaster Pro
SB Pro Registers (220 or 240h typ) Default Acc
Offset
0 FM Left Channel Index / Status RW
1 FM Left Channel Data
2 FM Right Channel Index / Status RW
3 FM Right Channel Data
4 Mixer Index
5 Mixer Data RW
6 Sound Processor Reset
7 -reserved- 00 -8 FM Index / Status (Both Channels) RW
9 FM Data (Both Channels)
A Sound Processor Data
B -reserved- 00 -C Sound Processor Command / Data
Sound Processor Buffer Status
D -reserved- 00 --
E Snd Processor Data Available Status
F -reserved- 00 --
Port
SB Pro Regs (same as offsets 8 & 9) Default Acc
388h FM Index / Status RW
389h FM Data
The above group of registers emulates the “FM”, “Mixer”, and
“Sound Processor” functions of the SoundBlaster Pro.
I/O Registers – Game Port
Game Port (200-20F typical) Default Acc
Offset
0 -reserved- 00 -1 Game Port Status
1 Start One-Shot
2-F -reserved- 00 --
WO
WO
WO
WO
WO
RO
WR
RD
RO
WO
RO
WO
Memory Mapped Registers – IOAPIC
Address
FEC00000 APIC Register Index 00 RW
FEC00001-0F -reserved- 00 --
FEC00013-10 APIC Register 32-bit Data 0000 0000 RW
FEC00014-1F -reserved- 00 --
FEC00020 APIC IRQ Pin Assertion xx
FEC00021-3F -reserved- 00 --
FEC00040 APIC EOI xx
FEC00041-FF -reserved- 00 --
Offset
0 APIC ID 0000 0000 RW
1 APIC Version 0017 0011
2 APIC Arbitration 0000 0000
40-4F -reserved- 0000 0000 -Note: The “I/O Redirection” registers are 64-bit registers, so
each uses two consecutive index locations, with the lower 32
bits at the even index and the upper 32 bits at the odd index.
APIC Index / Data Default Acc
WO
WO
APIC 32-bit Registers Default Acc
RO
RO
Revision 2.32, September 1, 2004 -43- Register Overview
Page 50
VT8231 South Bridge
—
—
—
PCI Device 1 Function 0 Registers - LAN
Configuration Space LAN Header Registers
Offset
PCI Configuration Space Header DefaultAcc
1-0 Vendor ID
3-2 Device ID
5-4 Command 0000RO
7-6 Status
8 Revision ID
9 Programming Interface 00RO
A Sub Class Code 00RO
B Base Class Code 00RO
C Cache Line Size 00
D Latency Timer 00
E Header Type 00RO
F BIST 00RO
17-14 Memory Base Address 0000 0000 RW
18-27 -reserved- 00
23-20 Receive Status 0000 0000 RW
27-24 Receive Data Buffer Control 0000 0000
2B-28 Receive Data Buffer Start Address
2F-2C Receive Data Buffer Branch Address
30-3F -reserved- 00
1106
3065
0400WC
40
01 RO
0002 RO
08
RO
RO
RO
RW
RW
RO
RO
WC
—
RW
—
RO
RO
RO
—
I/O Space LAN Registers (continued)
Offset
4B-48 Transmit Data Buffer Start Address
4F-4C Transmit Data Buffer Branch Addr
50-6B -reserved- 00
7C-7F -reserved- 00
9D-9C Soft Timer 0 0000 RW
9F-9E Soft Timer 1 0000 RW
A0/A4 Wake On LAN Control Set / Clear 00 / 00 RW
A1/A5 Power Configuration Set / Clear 00 / 00 RW
A2/A6 Test Set / Clear 00 / 00 RW
A3/A7 Wake On LAN Config Set / Clear 00 / 00 RW
Revision 2.32, September 1, 2004 -44- Register Overview
Page 51
VT8231 South Bridge
Register Descriptions
Legacy I/O Ports
This group of registers includes the DMA Controllers,
Interrupt Controllers, and Timer/Counters as well as a number
of miscellaneous ports originally implemented using discrete
logic on original PC/AT motherboards. All of the registers
listed are integrated on-chip. These registers are implemented
in a precise manner for backwards compatibility with previous
generations of PC hardware. These registers are listed for
information purposes only. Detailed descriptions of the
actions and programming of these registers are included in
numerous industry publications (duplication of that
information here is beyond the scope of this document). All
of these registers reside in I/O space.
Port 61 - Misc Functions & Speaker Control................. RW
7 SERR# Status .......................................................RO
0 SERR# has not been asserted ................ default
1 SERR# was asserted by a PCI agent
Note: This bit is set when the PCI bus SERR# signal
is asserted. Once set, this bit may be cleared
by setting bit-2 of this register. Bit-2 should
be cleared to enable recording of the next
SERR# (i.e., bit-2 must be set to 0 to enable
The keyboard controller handles the keyboard and mouse
interfaces. Two ports are used: port 60 and port 64. Reads
from port 64 return a status byte. Writes to port 64h are
command codes (see command code list following the register
descriptions). Input and output data is transferred via port 60.
A “Control” register is also available. It is accessable by
writing commands 20h / 60h to the command port (port 64h);
The control byte is written by first sending 60h to the
command port, then sending the control byte value. The
control register may be read by sending a command of 20h to
port 64h, waiting for “Output Buffer Full” status = 1, then
reading the control byte value from port 60h.
Traditional (non-integrated) keyboard controllers have an
“Input Port” and an “Output Port” with specific pins dedicated
to certain functions and other pins available for general
purpose I/O. Specific commands are provided to set these
pins high and low. All outputs are “open-collector” so to
allow input on one of these pins, the output value for that pin
would be set high (non-driving) and the desired input value
read on the input port. These ports are defined as follows:
Bit
Input Port Lo Code Hi Code
0 P10 - Keyboard Data In B0 B8
1 P11 - Mouse Data In B1 B9
2 P12 - Turbo Pin (PS/2 mode only) B2 BA
3 P13 - user-defined B3 BB
4 P14 - user-defined B6 BE
5 P15 - user-defined B7 BF
6 P16 - user-defined – –
7 P17 - undefined – –
Bit
Output Port Lo Code Hi Code
0 P20 - SYSRST (1=execute reset) – –
1 P21 - GATEA20 (1=A20 enabled) – –
2 P22 - Mouse Data Out B4 BC
3 P23 - Mouse Clock Out B5 BD
4 P24 - Keyboard OBF Interrupt (IRQ1) – –
5 P25 - Mouse OBF Interrupt (IRQ 12) – –
6 P26 - Keyboard Clock Out – –
7 P27 - Keyboard Data Out – –
Bit Test Port
0 T0 - Keyboard Clock In – –
1 T1 - Mouse Clock In – –
Note: Command code C0h transfers input port data to the
output buffer. Command code D0h copies output port values
to the output buffer. Command code E0h transfers test input
port data to the output buffer.
Port 60 - Keyboard Controller Input Buffer ..................WO
Only write to port 60h if port 64h bit-1 = 0 (1=full).
Port 60 - Keyboard Controller Output Buffer ................RO
Only read from port 60h if port 64h bit-0 = 1 (0=empty).
Lo Code Hi Code
Port 64 - Keyboard / Mouse Status .................................. RO
7 Parity Error
0 No parity error (odd parity received)..... default
1 Even parity occurred on last byte received
from keyboard / mouse
6 General Receive / Transmit Timeout
0 No error ................................................. default
Port 64 - Keyboard / Mouse Command ..........................WO
This port is used to send commands to the keyboard / mouse
controller. The command codes recognized by the VT8231
are listed n the table below.
Note: The VT8231 Keyboard Controller is compatible with
the VIA VT82C42 Industry-Standard Keyboard Controller
except that due to its integrated nature, many of the input and
output port pins are not available externally for use as general
purpose I/O pins (even though P13-P16 are set on power-up as
strapping options). In other words, many of the commands
below are provided and “work”, but otherwise perform no
useful function (e.g., commands that set P12-P17 high or low).
Also note that setting P10-11, P22-23, P26-27, and T0-1 high
or low directly serves no useful purpose, since these bits are
used to implement the keyboard and mouse ports and are
directly controlled by keyboard controller logic.
Table 6. Keyboard Controller Command Codes
Code Keyboard Command Code Description
20h Read Control Byte (next byte is Control Byte)
21-3Fh Read SRAM Data (next byte is Data Byte)
60h Write Control Byte (next byte is Control Byte)
61-7Fh Write SRAM Data (next byte is Data Byte)
9xh Write low nibble (bits 0-3) to P10-P13
A1h Output Keyboard Controller Version #
A4h Test if Password is installed
(always returns F1h to indicate not installed)
A7h Disable Mouse Interface
A8h Enable Mouse Interface
A9h Mouse Interface Test (puts test results in port 60h)
(value: 0=OK, 1=clk stuck low, 2=clk stuck high,
3=data stuck lo, 4=data stuck hi, FF=general error)
AAh KBC self test (returns 55h if OK, FCh if not)
ABh Keyboard Interface Test (see A9h Mouse Test)
ADh Disable Keyboard Interface
AEh Enable Keyboard Interface
AFh Return Version #
B0h Set P10 low
B1h Set P11 low
B2h Set P12 low
B3h Set P13 low
B4h Set P22 low
B5h Set P23 low
B6h Set P14 low
B7h Set P15 low
B8h Set P10 high
B9h Set P11 high
BAh Set P12 high
BBh Set P13 high
BCh Set P22 high
BDh Set P23 high
BEh Set P14 high
BFh Set P15 high
Code
Keyboard Command Code Description
C0h Read input port (read P10-17 input data to
the output buffer)
C1h Poll input port low (read input data on P11-13
repeatably & put in bits 5-7 of status
C2h Poll input port high (same except P15-17)
C8h Unblock P22-23 (use before D1 to change
active mode)
C9h Reblock P22-23 (protection mechanism for D1)
CAh Read mode (output KBC mode info to port 60
output buffer (bit-0=0 if ISA, 1 if PS/2)
D0h Read Output Port (copy P10-17 output port values
to port 60)
D1h Write Output Port (data byte following is written to
keyboard output port as if it came from keyboard)
D2h Write Keyboard Output Buffer & clear status bit-5
(write following byte to keyboard)
D3h Write Mouse Output Buffer & set status bit-5 (write
following byte to mouse; put value in mouse input
buffer so it appears to have come from the mouse)
D4h Write Mouse (write following byte to mouse)
E0h Read test inputs (T0-1 read to bits 0-1 of resp byte)
Exh Set P23-P21 per command bits 3-1
Fxh Pulse P23-P20 low for 6usec per command bits 3-0
Channels 0-3 of the Master DMA Controller control System
DMA Channels 0-3. There are 16 Master DMA Controller
registers:
I/O Address Bits 15-0
Register Name
0000 0000 000x 0000 Ch 0 Base / Current Address RW
0000 0000 000x 0001 Ch 0 Base / Current Count RW
0000 0000 000x 0010 Ch 1 Base / Current Address RW
0000 0000 000x 0011 Ch 1 Base / Current Count RW
0000 0000 000x 0100 Ch 2 Base / Current Address RW
0000 0000 000x 0101 Ch 2 Base / Current Count RW
0000 0000 000x 0110 Ch 3 Base / Current Address RW
0000 0000 000x 0111 Ch 3 Base / Current Count RW
0000 0000 000x 1000 Status / Command RW
0000 0000 000x 1001 Write Request WO
0000 0000 000x 1010 Write Single Mask WO
0000 0000 000x 1011 Write Mode WO
0000 0000 000x 1100 Clear Byte Pointer F/F WO
0000 0000 000x 1101 Master Clear WO
0000 0000 000x 1110 Clear Mask WO
0000 0000 000x 1111 R/W All Mask Bits RW
Ports C0-DF - Slave DMA Controller
Channels 0-3 of the Slave DMA Controller control System
DMA Channels 4-7. There are 16 Slave DMA Controller
registers:
I/O Address Bits 15-0
Register Name
0000 0000 1100 000x Ch 4 Base / Current Address RW
0000 0000 1100 001x Ch 4 Base / Current Count RW
0000 0000 1100 010x Ch 5 Base / Current Address RW
0000 0000 1100 011x Ch 5 Base / Current Count RW
0000 0000 1100 100x Ch 6 Base / Current Address RW
0000 0000 1100 101x Ch 6 Base / Current Count RW
0000 0000 1100 110x Ch 7 Base / Current Address RW
0000 0000 1100 111x Ch 7 Base / Current Count RW
0000 0000 1101 000x Status / Command RW
0000 0000 1101 001x Write Request WO
0000 0000 1101 010x Write Single Mask WO
0000 0000 1101 011x Write Mode WO
0000 0000 1101 100x Clear Byte Pointer F/F WO
0000 0000 1101 101x Master Clear WO
0000 0000 1101 110x Clear Mask WO
0000 0000 1101 111x Read/Write All Mask Bits WO
Note that not all bits of the address are decoded.
The Master and Slave DMA Controllers are compatible with
the Intel 8237 DMA Controller chip. Detailed description of
8237 DMA controller operation can be obtained from the Intel
Peripheral Components Data Book and numerous other
industry publications.
Ports 80-8F - DMA Page Registers
There are eight DMA Page Registers, one for each DMA
channel. These registers provide bits 16-23 of the 24-bit
address for each DMA channel (bits 0-15 are stored in
registers in the Master and Slave DMA Controllers). They are
located at the following I/O Port addresses:
The DMA Controller shadow registers are enabled by setting
function 0 Rx77 bit 0. If the shadow registers are enabled,
they are read back at the indicated I/O port instead of the
standard DMA controller registers (writes are unchanged).
Port 0 –Channel 0 Base Address ...................................... RO
Port 1 –Channel 0 Byte Count.......................................... RO
Port 2 –Channel 1 Base Address ...................................... RO
Port 3 –Channel 1 Byte Count.......................................... RO
Port 4 –Channel 2 Base Address ...................................... RO
Port 5 –Channel 2 Byte Count.......................................... RO
Port 6 –Channel 3 Base Address ...................................... RO
Port 7 –Channel 3 Byte Count.......................................... RO
Port 8 –1
Port 8 –2
Port 8 –3
Port 8 –4
Port 8 –5
Port 8 –6
Note that not all bits of the address are decoded.
The Master Interrupt Controller is compatible with the Intel
8259 Interrupt Controller chip. Detailed descriptions of 8259
Interrupt Controller operation can be obtained from the Intel
Peripheral Components Data Book and numerous other
industry publications.
Ports A0-A1 - Slave Interrupt Controller
The Slave Interrupt Controller controls system interrupt
channels 8-15. The slave system interrupt controller also
occupies two register locations:
The Slave Interrupt Controller is compatible with the Intel
8259 Interrupt Controller chip. Detailed descriptions of 8259
Interrupt Controller operation can be obtained from the Intel
Peripheral Components Data Book and numerous other
industry publications.
Interrupt Controller Shadow Registers
The following shadow registers are enabled by setting
function 0 Rx47[4]. If the shadow registers are enabled, they
are read back at the indicated I/O port instead of the standard
interrupt controller registers (writes are unchanged).
Port 20 - Master Interrupt Control Shadow ................... RO
Port A0 - Slave Interrupt Control Shadow ..................... RO
Note that not all bits of the address are decoded.
The Timer / Counters are compatible with the Intel 8254
Timer / Counter chip. Detailed descriptions of 8254 Timer /
Counter operation can be obtained from the Intel Peripheral
Components Data Book and numerous other industry
publications.
Timer / Counter Shadow Registers
The following shadow registers are enabled for readback by
setting function 0 Rx47[4]. If the shadow registers are
enabled, they are read back at the indicated I/O port instead of
the standard timer / counter registers (writes are unchanged).
Port 40 – Counter 0 Base Count Value (LSB 1
Port 41 – Counter 1 Base Count Value (LSB 1
Port 42 – Counter 2 Base Count Value (LSB 1
Port 75 - CMOS Data........................................................RW
7-0 CMOS Data (256 bytes)
Note: Ports 74-75 may be accessed only if Function 0 Rx5B
bit-1 is set to one to enable the internal RTC SRAM
and if Rx48 bit-3 (Port 74/75 Access Enable) is set to
one to enable port 74/75 access.
Note: Ports 70-71 are compatible with PC industry-
standards and may be used to access the lower 128
bytes of the 256-byte on-chip CMOS RAM. Ports 7475 may be used to access the full on-chip extended
256-byte space in cases where the on-chip RTC is
disabled.
Note: The system Real Time Clock (RTC) is part of the
“CMOS” block. The RTC control registers are
located at specific offsets in the CMOS data area (00Dh and 7D-7Fh). Detailed descriptions of CMOS /
RTC operation and programming can be obtained
from the VIA VT82887 Data Book or numerous
other industry publications. For reference, the
definition of the RTC register locations and bits are
summarized in the following table:
Offset
00 Seconds 00-3Bh 00-59h
01 Seconds Alarm 00-3Bh 00-59h 02 Minutes 00-3Bh 00-59h
03 Minutes Alarm 00-3Bh 00-59h 04 Hoursam 12hr: 01-1Ch 01-12h
pm 12hr: 81-8Ch 81-92h
24hr: 00-17h 00-23h
05 Hours Alarm am 12hr: 01-1Ch 01-12h pm 12hr: 81-8Ch 81-92h
24hr: 00-17h 00-23h
06 Day of the Week Sun=1: 01-07h 01-07h
07 Day of the Month 01-1Fh 01-31h
08 Month 01-0Ch 01-12h
09 Year 00-63h 00-99h
0A Register A
7 UIP Update In Progress
6-4 DV2-0 Divide (010=ena osc & keep time)
3-0 RS3-0 Rate Select for Periodic Interrupt
0B Register B
7 SET Inhibit Update Transfers
6 PIE Periodic Interrupt Enable
5 AIE Alarm Interrupt Enable
4 UIE Update Ended Interrupt Enable
3 SQWE No function (read/write bit)
2 DM Data Mode (0=BCD, 1=binary)
1 24/12 Hours Byte Format (0=12, 1=24)
0 DSE Daylight Savings Enable
0C Register C
7 IRQF Interrupt Request Flag
6 PF Periodic Interrupt Flag
5 AF Alarm Interrupt Flag
4 UF Update Ended Flag
3-0 0 Unused (always read 0)
0D Register D
7 VRT Reads 1 if VBAT voltage is OK
6-0 0 Unused (always read 0)
Super-IO / KBC Configuration Index / Data Registers
Super-IO and Keyboard / Mouse Controller configuration
registers are accessed by performing I/O operations to / from
an index / data pair of registers in system I/O space at port
addresses 3F0h and 3F1h. The configuration registers
accessed using this mechanism are used to configure the
Keyboard / Mouse Controller at index values in the range of
E0-EF and Super-I/O registers (parallel port, serial ports, IR
port, and floppy controller) at index values in the range of F0FF.
Super IO and/or Keyboard / Mouse Controller configuration is
accomplished in three steps:
1) Enter configuration mode (set Function 0 Rx50[2] = 1 to
enable Super-IO configuration and/or Rx51[1] = 1 to
enable Keyboard / Mouse Controller configuration)
2) Configure the chip
a) Write index to port 3F0
b) Read / write data from / to port 3F1
c) Repeat a and b for all desired registers
3) Exit configuration mode (set Function 0 Rx51[1] = 0)
Index E1 – Keyboard Scan Code Reference Set 0 (F0h) RW
7-0 Keyboard First Reference Scan Code ......def = F0h
Index E2 – Keyboard Scan Code Reference Set 1 (00h) RW
7-0 Keyboard Second Reference Scan Code...def = 00h
Port 3F0h – Super-IO Configuration Index....................RW
7-0 Index value
Function 0 PCI configuration space register Rx50[2] must be
set to 1 to enable access to the Super-I/O configuration
registers.
Port 3F1h – Super-I/O Configuration Data.................... RW
7-0 Data value
This register shares a port with the Floppy Status Port (which
is read only). This port is accessible only when Rx50[2] is set
to 1 (the floppy status port is accessed if Rx50[2] = 0).
Index E3 – Keyboard Scan Code Reference Set 2 (00h) RW
7-0 Keyboard Third Reference Scan Code..... def = 00h
Index E4 – Keyboard Scan Code Reference Set 3 (00h) RW
7-0 Keyboard Fourth Reference Scan Code...def = 00h
Index E5 – Keyboard Scan Code Reference Set 4 (00h) RW
If EPP is not enabled, the parallel port can be set to 192
locations on 4-byte boundaries from 100h to 3FCh. If EPP is
enabled, the parallel port can be set to 96 locations on 8-byte
boundaries from 100h to 3F8h. 16-bit address decode will be
performed with upper address bits 10-15 equal to zero.
Index F7 – Floppy Controller I/O Base Address............RW
0 Parallel Port (SPP) Mode .......................default
1 FDC or SPP Mode determined by GPI Pin
5 “Software” Floppy Drive On Parallel Port
0 Parallel Port (SPP) Mode .......................default
1 FDC Mode
Bits 6-5 are used in notebook applications to allow
attachment of an external floppy drive using the
parallel port I/O connector (bit-6 enables the mode to
be determined via a general purpose input pin and
bit-5 allows control of the mode unconditionally via
software).
SPP Mode
STROBE# I/O - n/a
PD0 I/O INDEX# I
PD1 I/O TRK00# I
PD2 I/O WRTPRT# I
PD3 I/O RDATA# I
PD4 I/O DSKCHG# I
PD5 I/O - n/a
PD6 I/O - n/a
PD7 I/O - n/a
ACK# I DS1# O
BUSY I MTR1# O
PE I WDATA# O
SLCT I WGATE# O
AUTOFD# I/O DRVEN0 O
ERROR# I HDSEL# O
PINIT# I/O DIR# O
SLCTIN# I/O STEP# O
These registers are located at I/O ports which are offsets from
“FDCBase” (index F7h of the Super-I/O configuration
registers). FDCBase is typically set to allow these ports to be
accessed at the standard floppy disk controller address range
of 3F0-3F7h.
Port FDCBase+2 – FDC Command.................................RW
7 Motor 3 (unused in VT8231: no MTR3# pin)6 Motor 2 (unused in VT8231: no MTR2# pin)5 Motor 1
0 Motor Off
1 Motor On
4 Motor 0
0 Motor Off
1 Motor On
3 DMA and IRQ Channels
0 Disabled
1 Enabled
2 FDC Reset
0 Execute FDC Reset
1 FDC Enabled
1-0 Drive Select
00 Select Drive 0
01 Select Drive 1
1x -reserved-
Port FDCBase+4 – FDC Main Status...............................RO
7 Main Request 0 Data register not ready
1 Data register ready
6 Data Input / Output
0 CPU => FDC
1 FDC => CPU
5 Non-DMA Mode 0 FDC in DMA mode
1 FDC not in DMA mode
4 FDC Busy
0 FDC inactive
1 FDC active
These registers are located at I/O ports which are offsets from
“LPTBase” (index F6h of the Super-I/O configuration
registers). LPTBase is typically set to allow these ports to be
accessed at the standard parallel port address range of 37837Fh.
Port LPTBase+0 – Parallel Port Data .............................RW
7-0 Parallel Port Data
Port LPTBase+1 – Parallel Port Status............................RO
7 BUSY# 0 Printer busy, offline, or error
1 Printer not busy
6 ACK# 0 Data transfer to printer complete
1 Data transfer to printer in progress
5 PE
0 Paper available
1 No paper available
4 SLCT
0 Printer offline
1 Printer online
3 ERROR#
0 Printer error
1 Printer OK
These registers are located at I/O ports which are offsets from
“COM1Base” (index F4h of the Super-I/O configuration
registers). COM1Base is typically set to allow these ports to
be accessed at the standard serial port 1 address range of 3F83FFh.
Port COM1Base+0 – Transmit / Receive Buffer............RW
7-0 Serial Data
Port COM1Base+1 – Interrupt Enable...........................RW
3 Interrupt on Hnadshake Input State Change2 Intr on Parity, Overrun, Framing Error or Break1 Interrupt on Transmit Buffer Empty0 Interrupt on Receive Data Ready
Port COM1Base+2 – Interrupt Status .............................RO
6 Transmitter Empty 0 1 byte in transmit hold or transmit shift
register
1 0 bytes transmit hold and transmit shift regs
5 Transmit Buffer Empty 0 1 byte in transmit hold register
1 Transmit hold register empty
4 Break Detected
0 No break detected
1 Break detected
3 Framing Error Detected
0 No error
1 Error
2 Parity Error Detected
0 No error
1 Error
1 Overrun Error Detected
0 No error
1 Error
0 Received Data Ready 0 No received data available
1 Received data in receiver buffer register
Port COM1Base+6 – Handshake Status......................... RW
7 DCD Status (1=Active, 0=Inactive)6 RI Status (1=Active, 0=Inactive)5 DSR Status (1=Active, 0=Inactive)4 CTS Status (1=Active, 0=Inactive)3 DCD Changed (1=Changed Since Last Read)2 RI Changed (1=Changed Since Last Read)1 DSR Changed (1=Changed Since Last Read)0 CTS Changed (1=Changed Since Last Read)
Port COM1Base+7 – Scratchpad.................................... RW
7 Scratchpad Data
Port COM1Base+9-8 – Baud Rate Generator Divisor .. RW
15-0 Divisor Value for Baud Rate Generator
Baud Rate = 115,200 / Divisor
(e.g., setting this register to 1 selects 115.2 Kbaud)
These registers are located at offsets from “SBPBase” (defined
in Rx43 of Audio Function 5 PCI configuration space).
SBPBase is typically set to allow these ports to be accessed at
the standard SoundBlaster Pro port address of 220h or 240h.
FM Registers
Port SBPBase+0 – FM Left Channel Index / Status.......RW
7-0 FM Right Channel Index / Status
Port SBPBase+1 – FM Left Channel Data......................WO
7-0 Right Channel FM Data
Port SBPBase+2 – FM Right Channel Index / Status ....RW
7-0 FM Right Channel Index / Status
Port SBPBase+3 – FM Right Channel Data ...................WO
7-0 Right Channel FM Data
Register Summary - FM
Index
20-35AM VIB EGT KSR Multi
40-55KSL Total Level (TL)
60-75Attack Rate (AR) Decay Rate (DR)
E0-F5 WS
MFC=Mask Fast Counter SSFC=Start / Stop Fast Counter
MSC=Mask Slow Counter SSSC=Start / Stop Slow Counter
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
01 Test
02 Fast Counter (80 usec)
03 Slow Counter (320 usec)
04 IRQ MFC MSC SSSC SSFC
08 CSMSEL
BD Int AM VIB Ryth Bass Snare Tom Cym HiHat
Port 388h or SBPBase+8 – FM Index / Status................RW
7-0 FM Index / Status (Both Channels)
Writing to this port programs both the left and right channels
(the write programms port offsets 0 and 2 as well)
Port 389h or SBPBase+9 – FM Data ...............................WO
7-0 FM Data (Both Channels)
Writing to this port programs both the left and right channels
(the write programms port offsets 1 and 3 as well)
Mixer Registers
Port SBPBase+4 – Mixer Index .......................................WO
7-0 Mixer Index
Port SBPBase+5 – Mixer Data.........................................RW
7-0 Mixer Data
Sound Processor Registers
Port SBPBase+6 – Sound Processor Reset......................WO
0 1 = Sound Processor Reset
Port SBPBase+A – Sound Processor Read Data .............RO
10 Play 8 bits directly
14 Play 8 bits via DMA
91 Play High-speed 8 bits via DMA
16 Play 2-bit compressed via DMA
17 Play 2-bit compressed via DMA with reference
74 Play 4-bit compressed via DMA
75 Play 4-bit compressed via DMA with reference
76 Play 2.6-bit compressed via DMA
77 Play 2.6-bit compressed via DMA with reference
20 Record Direct
24 Record Via DMA
99 Record High-speed 8 bits via DMA
D1 Speaker Turn on speaker connection
D3 Speaker Turn off speaker connection
D8 Speaker Get speaker setting
40 Misc Set sample rate
48 Misc Set block length
80 Misc Set silence block
D0 Misc Stop DMA
D4 Misc Continue DMA
E1 Misc Get version
30 MIDI Direct MIDI input
31 MIDI MIDI input via interrupt
32 MIDI Direct MIDI input with time stamp
33 MIDI MIDI input via interrupt with time stamp
34 MIDI Direct MIDI UART mode
35 MIDI MIDI UART mode via interrupt
36 MIDI Direct MIDI UART mode with time stamp
37 MIDI MIDI UART mode via interrupt with time stamp
38 MIDI Send MIDI code
Game Port Registers
These registers are fixed at the standard game port address of
201h.
I/O Port 201h – Game Port Status ................................... RO
7 Joystick B Button 2 Status6 Joystick B Button 1 Status5 Joystick A Button 2 Status4 Joystick A Button 1 Status 3 Joystick B One-Shot Status for Y-Potentiometer 2 Joystick B One-Shot Status for X-Potentiometer 1 Joystick A One-Shot Status for Y-Potentiometer 0 Joystick A One-Shot Status for X-Potentiometer
I/O Port 201h – Start One-Shot....................................... WO
9-5 SIR / Indication Pulse Width ................. default = 0
4-0 MIR Start / FIR Preamble Bytes to Send default = 0
MIR: # of start flags plus one (0 = 1 byte)
FIR: # of preamble bytes plus one (0 = 1 byte)
Baud Rate Pulse Width
Mode
SIR (2400) 47 0 12 12 Don’t Care
SIR (9600) 11 0 12 12 Don’t Care
SIR (19200) 5 1 12 12 Don’t Care
SIR (38400) 2 3 12 14 Don’t Care
SIR (57600) 1 5 12 16 Don’t Care
SIR (115200) 0 11 12 20 Don’t Care
MIR 0 8 1
FIR 0 Don’t Care 14
I/O Port Offset 1B-1A – Infrared Configuration 2 (0000)RW
1 Enable
6 Transmit Start Writing a 1 to this bit initiates execution of the IR
transmit mode programmed in the IR configuraton
registers. DMA and all necessary registers must be
set up prior to writing a 1 to this register. Writing 0
has no effect. This bit always reads 0; the “Host
Busy” bit (offset 21 bit-0) can be used to determine
when the IR Host Controller has finished executing
the transmission.
5 Receive Start Writing a 1 to this bit initiates execution of the IR
receive mode programmed in the IR configuraton
registers. DMA and all necessary registers must be
set up prior to writing a 1 to this register. Writing 0
has no effect. This bit always reads 0; the “Host
Busy” bit (offset 21 bit-0) can be used to determine
when the IR Host Controller has finished executing
been transmitted.
5 Bad CRC Write 1 to send inverted or bad CRC to allow test of
CRC verification hardware by the receiver. This bit
will be cleared by hardware when the packet has been
transmitted.
4 Need Pulse Write 1 to transmit an indication pulse after this
packet has been transmitted. This bit will be cleared
by hardware when the packet has been transmitted.
3 Request to Clear “Transmit Enable” BitWrite 1 to clear the “Enable Transmit” bit (offset 10h
bit-5) after this packet has been transmitted. Should
be set on the last packet of a transmit seuence.
2-0 Early EOM Interrupt LevelThis field specifies the number of bytes that must
remain in the Transmit Byte Count before an Early
EOM interrupt is generated. The reason for having
an interrupt occur before transmission is actually
completed is to allow enough time for software to
enter the proper interrupt handler routine, turn the
DMA channel around for reception (Singe DMA
mode), and perpare for another back-to-back
transmission. Once in the interrupt handler routine,
software can poll the EOM bit in the Transmit Status
register to determine exactly when the transmission
ends.
000 Interrupt by EOM
001 EOM int occurs when remaining count is 16
010 EOM int occurs when remaining count is 32
011 EOM int occurs when remaining count is 64
100 EOM int occurs when remaining count is 128
101 EOM int occurs when remaining count is 256
110 EOM int occurs when remaining count is 512
111 EOM int occurs when remaining count is 1024
I/O Port Offset 25 – Transmit Status (00h)..................... RO
3 Transmit FIFO Underrun1 indicates that the Transmit FIFO ran out of data
before the transmitter could finish transmitting all the
data (i.e., Transmit FIFO empty and a Transmit Byte
Count value greater than zero). This bit must be reset
by an explicit FIFO Underrun / EOM Latch
command.
2 End Of Message (EOM)1 indicates transmission completed successfully. The
EOM interrupt occurs immediately after the CRC and
ending flag have been transmitted. This bit is reset
by reading the Transmit Status register or by a Reset
FIFO Underrun / EOM Latch command from the
Reset Command register.
1 Transmit FIFO Ready1 indicates that the Transmit FIFO is ready for more
data transfers. When the “Enable Transmit FIFO
Ready Interrupt” bit is set (“Transmit Control
Register 1” bit-6), an interrupt is generated when this
condition becomes true.
0 Early End Of Message1 indicates that the Transmit Byte Count has reached
the level set by the Early EOM Interrupt Level
(“Transmit Control Register 2” bits 2-0). This bit is
cleared by reading the Transmit Status register.
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I/O Port Offset 26 – Receive Control (00h)..................... RW
7 Receive FIFO Level 0 Not Empty (more than 1 byte of receive data
remaining in the FIFO) ................................def
1 Maximum Receive Packet Length1 indicates that a maximum length packet was
encountered. For SIR, this means that the packet was
closed and another will be opened without any data
being truncated. In other modes, once the maximum
length is reached, no other data will be received.
This bit is automatically cleared upon detection of the
beginning / start flag of the next incoming packet.
0 SIR Bad 1 indicates (if the SIR filter is on) that a begin flag
was seen followed by valid data, then followed by
another begin flag (without an end flag). This bit is
automatically cleared upon detection of the beginning
/ start flag of the next incoming packet.
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I/O Port Offset 28 – Reset Command (00h)....................WO
7-4 Reset Command Used to send a reset signal to the appropriate
hardware in order to clear a particular status
condition, clear a counter, or send a general reset.
These bits are self clearing (i.e., the programmer does
not have to write 0 to the Reset Command register).
0000 No reset ..................................................default
14-0 Receive Byte Count
Used in back-to-back packet reception to provide the
end-of-packet pointer value (i.e., pointer to the last
byte of a frame received in the receive buffer). The
order of byte access to the Ring Packet Pointer is
critical for obtaining a valid pointer value. The
programmer must ensure that the low byte is read
first, followed by the high byte.
I/O Port Offset 32 – General Purpose Timer (00).......... RW
7-0 Timer Target Value (W) / Current Value (R)This counter increments every 125 usec and stops
when it reaches the programmed target value.
Reading this register returns the current value of the
up counter. Writes set the target value and reset the
counter to 0.
I/O Port Offset 33 – IR Configuration 4 (00) ................. RW
7 IRRX2 Source 0 IRRX2 source depends on Rx10[6-4] IrDA
11-0 Transmit Byte CountProvides a running count of the number of bytes
remaining to be transmitted. Before enabling
transmission, software loads this register with the
byte length of the data packet. Each time the
Transmit FIFO is written to, the value of this counter
decrements by one. When the counter reaches zero,
the transmitter ceases to make DMA requests.
Transmission continues until the Transmit FIFO is
depleted.
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PCI Configuration Space I/O
PCI configuration space accesses for functions 0-6 use PCI
configuration mechanism 1 (see PCI specification revision 2.2
for more details). The ports respond only to double-word
accesses. Byte or word accesses will be passed on unchanged.
Port CFB-CF8 - Configuration Address.........................RW
23-16 PCI Bus Number Used to choose a specific PCI bus in the system
15-11 Device Number Used to choose a specific device in the system
10-8 Function Number Used to choose a specific function if the selected
device supports multiple functions
7-2 Register Number Used to select a specific DWORD in the device’s
Port CFF-CFC - Configuration Data .............................. RW
There are 7 “functions” implemented in the VT8231:
Function #
0 PCI to ISA Bridge
1 IDE Controller
2 USB Controller Ports 0-1
3 USB Controller Ports 2-3
4 Power Management, SMBus & Hardware
5 AC97 Audio Codec Controller
6 MC97 Modem Codec Controller
The following sections describe the registers and register bits
of these functions.
Function
Monitor
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Device 0 Function 0 Registers - PCI to ISA Bridge
All registers are located in the device 0 function 0 PCI
configuration space of the VT8231. These registers are
accessed through PCI configuration mechanism #1 via I/O
address CF8/CFC.
PCI Configuration Space Header
Offset 1-0 - Vendor ID = 1106h.........................................RO
Offset 3-2 - Device ID = 8231h ..........................................RO
3 Special Cycle Enable .....Normally RW†, default = 0
2 Bus Master ........................................ always reads 1
1 Memory Space.................. Normally RO†, reads as 1
0I/O Space ...................... Normally RO†, reads as 1
† If the test bit at offset 46 bit-4 is set, access to the above
indicated bits is reversed: bit-3 above becomes read only
(reading back 1) and bits 0-1 above become read / write (with
a default of 1).
1 Enable
Set if internal RTC is disabled but SRAM access is
desired via ports 74-75 (bit-3 must also be set). If the
internal RTC is enabled, setting this bit does nothing
(internal RTC SRAM may be accessed at either ports
70/71).
0 RTC Test Mode Enable (do not program) . default=0
Offset 4F – PCI Bus and CPU Interface Control........... RW
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Device 0 Function 1 Registers - Enhanced IDE Controller
This Enhanced IDE controller interface is fully compatible
with the SFF 8038i v.1.0 specification. There are two sets of
software accessible registers -- PCI configuration registers and
Bus Master IDE I/O registers. The PCI configuration registers
are located in the function 1 PCI configuration space of the
VT8231. The Bus Master IDE I/O registers are defined in the
SFF8038i v1.0 specification.
PCI Configuration Space Header
Offset 1-0 - Vendor ID (1106h=VIA)................................RO
Offset 3-2 - Device ID (0571h=IDE Controller)...............RO
Native PCI Mode (registers are programmable in I/O space)
In this mode, IRQs for the primary and secondary IDE
channels are programmable via configuration register Rx3C
and the registers of the IDE channels are relocatable in I/O
space (using base addresses provided in the IDE Controller
PCI configuration space). Specific base address registers are
used to map the different register blocks as defined below:
Command Block Control Block
Channel
Pri BA @offset 10h BA @offset 14h
Sec BA @offset 18h BA @offset 1Ch
Registers Registers
Command register blocks are 8 bytes of I/O space
Control registers are 4 bytes of I/O space (only byte 2 is used)
Offset A - Sub Class Code (01h=IDE Controller)........... RO
Offset B - Base Class Code (01h=Mass Storage Ctrlr)... RO
Offset C – Cache Line Size (00h)...................................... RO
Offset D - Latency Timer (Default=0)............................. RW
Offset E - Header Type (00h)............................................ RO
Offset F - BIST (00h)......................................................... RO
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Offset 13-10 - Pri Data / Command Base Address ......... RW
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Device 0 Function 2 Registers - USB Controller Ports 0-1
This Universal Serial Bus host controller interface is fully
compatible with UHCI specification v1.1. There are two sets
of software accessible registers: PCI configuration registers
and USB I/O registers. The PCI configuration registers are
located in the function 2 PCI configuration space of the
VT8231. The USB I/O registers are defined in UHCI
specification v1.1. The registers in this function control USB
ports 0-1 (see function 3 for ports 2-3).
PCI Configuration Space Header
Offset 1-0 - Vendor ID .......................................................RO
15-0 Vendor ID ................. (1106h = VIA Technologies)
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Device 0 Function 3 Registers - USB Controller Ports 2-3
This Universal Serial Bus host controller interface is fully
compatible with UHCI specification v1.1. There are two sets
of software accessible registers: PCI configuration registers
and USB I/O registers. The PCI configuration registers are
located in the function 3 PCI configuration space of the
VT8231. The USB I/O registers are defined in UHCI
specification v1.1. The registers in this function control USB
ports 2-3 (see function 2 for ports 0-1).
PCI Configuration Space Header
Offset 1-0 - Vendor ID .......................................................RO
15-0 Vendor ID ................. (1106h = VIA Technologies)
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Device 0 Function 4 Regs - Power Management, SMBus
and HWM
This section describes the ACPI (Advanced Configuration and
Power Interface) Power Management system of the VT8231
which includes a System Management Bus (SMBus) interface
controller and Hardware Monitoring (HWM) subsystem. The
power management system of the VT8231 supports both
ACPI and legacy power management functions and is
compatible with the APM v1.2 and ACPI v1.0 specifications.
PCI Configuration Space Header
Offset 1-0 - Vendor ID .......................................................RO
15-0 Vendor ID ................. (1106h = VIA Technologies)
Offset 41 - General Configuration 1................................ RW
7 I/O Enable for ACPI I/O Base
0 Disable access to ACPI I/O block .........default
1 Allow access to Power Management I/O
Register Block (see offset 4B-48 to set the
base address for this register block). The
definitions of the registers in the Power
Management I/O Register Block are included
later in this document, following the Power
Management Subsystem overview.
6 ACPI Timer Reset
0 Normal Timer Operation ....................... default
1 Reset Timer
5-4 PMU Timer Test Mode (Do Not Program)....def = 0
Port Address for the base of the 128-byte Power
Management I/O Register block, corresponding to
AD[15:7]. The "I/O Space" bit at offset 41 bit-7
enables access to this register block. The definitions
of the registers in the Power Management I/O
Register Block are included later in this document,
following the Power-Management-Specific PCI
Configuration register descriptions and the Power
Management Subsystem overview.
6-0 0000001b
Offset 4C – Host Bus Power Management Control........RW
7-4 Thermal Duty CycleThis field determines the duty cycle of STPCLK#
when the THRM# pin is asserted. The STPCLK#
duty cycle when THRM# is NOT asserted is
controlled by PMIO Rx10[3:0]. The duty cycle
indicates the percentage of performance (the lower
the percentage, the lower the performance and the
higher the power savings). If the Throttling Timer
Width (Function 0 Rx8D[6-5]) is set to 3-bit width,
bit-0 of this field should be set to 0 (and the
performance increment will be 12.5%). If the
Throttling Timer Width is set to 2-bit width, bits 1-0
of this field should be set to 0 (and the performance
increment will be 25%).
10 3-Bit
11 2-Bit
(see also Rx8C[7-4] and PMIO Rx10[3-0])
4 Fast Clock (7.5us) as Throttle Timer Tick This bit controls whether the throttle timer tick uses
7.5 usec as its time base (120 usec cycle time when
using a 4-bit timer).
0 Timer Tick is selected by Rx81[1] ........ default
1 Timer Tick is 7.5 usec (Rx81[1] is ignored)
3 SMI Level Output (Low)