VIA VT6516 Datasheet

VIA Technologies, Inc. Preliminary VT6516 Datasheet

VT6516

16/12-PORT 10/100BASE-T/TX

ETHERNET SWITCH CONTROLLER

REVISION ‘E’ DATASHEET

(Preliminary)

ISSUE 1: July 31, 1999

VIA Technologies, Inc.

VIA Technologies, Inc. Preliminary VT6516 Datasheet

PRELIMINARY RELEASE

Please contact VIA Technologies for the latest documentation.

Copyright © 1995, VIA Technologies Incorporated. Printed in Taiwan. ALL RIGHTS RESERVED. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise without the prior written permission of VIA Technologies Incorporated. The VT86C100P may only be used to identify products of VIA Technologies. All trademarks are the properties of their respective owners.

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VIA Technologies, Inc. Preliminary VT6516 Datasheet

TABLE OF CONTENTS

TABLE OF CONTENTS................................................................................................................................3

FIGURES AND TABLES ...............................................................................................................................4

REVERSION HISTORY ................................................................................................................................5

FEATURES ................................................................................................................................................6

BLOCK DIAGRAM...................................................................................................................................... 9

BALL OUT DIAGRAM............................................................................................................................... 11

RMII-mode Ball out Diagram ........................................................................................................... 11

MII-mode Ballout Diagram............................................................................................................... 12

LOGIC SYMBOL ...................................................................................................................................... 13

PIN DESCRIPTIONS.................................................................................................................................. 14

JUMPER STRAPPING................................................................................................................................. 18

SECTION I FUNCTIONAL DESCRIPTIONS ...................................................................................... 19

1. GENERAL DESCRIPTION ...................................................................................................................... 19

2. THE VIA ETHER SWITCH ARCHITECTURE............................................................................................ 19

2.1 Switch initialization procedures .................................................................................................. 19

2.2 Packet receiving and forwarding follow .......................................

3. INTERFACE DESCRIPTIONS................................................................................................................... 20

3.1 Buffer Memory (SDRAM) Interface and Table (SRAM) interface..

4. FUNCTIONAL DESCRIPTION ................................................................................................................. 33

4.1 Packet Reception and Address recognition.................................................................................. 33

4.2 Packet Forwarding and VLAN..................................................................................................... 33

4.3 Network Management Features................................................................................................... 34

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SECTION II REGISTER MAP...............................................................................................................36

1. REGISTER TABLES ............................................................................................................................. 36

2 CPU INTERFACE REGISTERS MAP......................................................................................................... 36

3 SWITCH INTERNAL REGISTERS MAP..................................................................................................... 37

4. DETAIL OF SWITCH REGISTER.............................................................................................................. 44

4.1 Registers of SDRAM Control Module ......................................................................................... 44

4.2 Registers of SRAM Control Module............................................................................................ 46

4.4 Registers of Buffer Control Module............................................................................................. 48

4.5 Registers of Forwarding Control Module................................................................................... 49

4.6 Registers of PHY Control Module .............................................................................................. 53

4.7 Registers of EEPROM Control Module....................................................................................... 55

4.8 Registers of CPU Interface Module ............................................................................................. 56

4.9 Registers of MAC/IO Control Module......................................................................................... 59

4.10 Registers of CPU IO Control Module....................................................................................... 63

SECTION III ELECTRICAL SPECIFICATIONS.................................................................................65

ABSOLUTE MAXIMUM RATINGS............................................................................................................... 65

DC CHARACTERISTICS............................................................................................................................ 65

AC CHARACTERISTICS............................................................................................................................ 65

PACKAGE MECHANICAL SPECIFICATIONS................................................................................................. 73

VIA Technologies, Inc. Preliminary VT6516 Datasheet

FIGURES AND TABLES

Figure 1: Block Diagram .............................................................................................9

Figure 3-3 .................................................................................................................22

Figure 3-6: Algorithm of Initialization of Free Link Lists. ..........................................22

Figure 3-1 SRAM......................................................................................................26

Figure 3-2 Free buffer link structure ..........................................................................27

Table 1-0 Free buffer link structure............................................................................27

Figure 3-5 The Address table entries structure +........................................................27

Table 1-1 Address table structure ..............................................................................28

Table 3-1 RMII interface signals ................................................................................30

Figure 3-1 RMII timing diagram................................................................................30

Table 3-2 MII interface signals ..................................................................................31

Figure 3-2 MII timing diagram .................................................................................. 31

VIA Technologies, Inc. Preliminary VT6516 Datasheet

REVERSION HISTORY

Reversion Date Reason for change By V0.90 2/18/1999 First release version JeffreyChang V0.91 6/2/1999 Add D version silicon features

modification

V0.92 8/23/1999 Add E version silicon features

modification

V0.93 9/9/1999 Revision according to Weipin’s,

Kevin’s, and Ruth’ s comments

JeffreyChang

MurphyChen

VIA Technologies, Inc. Preliminary VT6516 Datasheet

FEATURES

l Single chip 16/12 ports 10/100M Ethernet switch controller

- Highly integrated single chip shared memory switch engine

- With option for 16 RMII (Reduced Media Independent Interface) ports or 12 MII

(Media Independent Interface) ports

- Non-blocking layer 2 switch, 148,810 packets/sec on each 100Mbps Ethernet port

l Media Access Control (MAC)

- Dual 192-bytes FIFO’s of receive and transmit for each port

- CRC generator for outgoing packets from CPU port

- IEEE 802.3X compliant flow control for full duplex ports

- Backpressure for half duplex ports

l Two switching mechanisms

- Supports ‘store and forward’ switching without forwarding CRC-bad packets

- Supports ‘cut through’ switching subject to long packets of length over 290 bytes for

100Mbps ports or of length over 98 bytes for 10Mbps ports

l Packet buffering

- Glueless 64-bit interface to SDRAM as a packet buffer pool with size from 2M bytes

(SGRAM) to 512 M bytes

- 1536 bytes for each packet buffer

l External 32 bits SSRAM interface for forwarding table and memory link table

- Link list structure initialized by software

- 2K up to 32K unicast/multicast addresses table entries with VLAN information

- Supports static entries for upper-layer multicast protocols, e.g. IGMP

l Advanced address recognition

- Layer 2 MAC address recognition engine to enable wire-speed forwarding rate

- Self learning mechanism

- Supports multiple MAC address per-port from 2K up to 32K unicast/multicast

addresses

l Switch management support

- Supports port mirroring (Sniffer feature)

- Supports spanning tree algorithm

- Supports CPU direct access to SDRAM and SSRAM

- Supports five statistical counters in each port

l Supports I l Support port-grouping VLAN

- Configurable server ports belonging to multiple VLAN groups

l Support port-based trunking

- Three types of trunk grouping: one trunk group with 2 or 4 ports, two trunk groups

each with 2 ports

- Load balance according to MAC address and port number

l CPU interface VIA 8/16 bits ISA-like interface

C EEPROM interface for customized configuration

VIA Technologies, Inc. Preliminary VT6516 Datasheet

- Chip initialization, auto-aging and spanning tree algorithm support by firmware

- Auto-sensing 10/100M media speed, duplex mode, and flow-control capability by

firmware

l 50MHz internal reference clock rate l 50~100MHz SDRAM clock rate, typically 83MHz l 50~100MHz SSRAM clock rate, typically 83MHz l Single +3.3V supply, 0.3µm standard CMOS technology l 476 ball BGA package

VIA Technologies, Inc. Preliminary VT6516 Datarsheet

BLOCK DIAGRAM

forwarding control

input control

RMAC

SRAM control

buffer control

output control

queue control

TMAC

CPU interface

scheduler

SDRAM control

Figure 1: Block Diagram

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VIA Technologies, Inc. Preliminary VT6516 Datarsheet

BALL OUT DIAGRAM

RMII-mode Ball out Diagram

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 CSDV2 CRS.DV1RXD1.1 TXEN1 TXD1.0 RXD0.0 MD1 MD3 MD5 MD7 MD9 MD11 MD45 MD47 RAS0 MA3 MA7 MA11 DCS2 DWE0 MD49 MD20 MD22 MD24 MD57 MD58

RXD1.2 TXD1.2 TXD1.1 RXD0.1 CSDV0 TXD0.0 MD32 MD34 MD36 MD38 MD40 MD42 MD14 CAS1 MA0 MA4 MA8 BA0 DCS1 DWE1 MD18 MD52 MD54 MD56 MD26 MD27

TXEN2 RXD0.2 TXD0.2 TXD0.1 TXEN0 RXD1.0 MD0 MD2 MD4 MD6 MD8 MD10 MD46 CAS0 MA1 MA5 MA9 BA1 DCS0 MD16 MD50 MD21 MD23 MD25 MD59 MD28

TXD1.3 CSDV3 TXEN3 NC NC NC MD33 GND MD37 MD39 MD41 MD43 MD13 MD15 RAS1 MA2 MA6 MA10 DCS3 MD48 MD19 MD53 MD55 MD60 MD29 MD61

RXD0.3 TXD0.3 RXD1.3 NC VDDI GNDI GND MD35 VDD VDD VDD MD12 MD44 GND GND GND VDD VDD VDD MD17 MD51 GNDI DCLK MD30 MD62 MD31

RXD1.4 TXD0.4 RXD0.4 TXEN4 RCLK50VDDI GND NC NC GND GNDI VDDI MD63 SD16 SD17 SD18

RXD0.5 CSDV4 TXD1.4 TXEN5 VDD GND GND SCLK SD19 SD20 SD21 SD22

TXD1.5 RXD1.5 TXD0.5 NC VDD VDD NC SD23 SD24 SD25 SD26 SD27

TXD0.6 RXD0.6 CSDV5 NC VDD VDD SD31 SD28 SD29 SD30

CSDV6 TXD1.6 RXD1.6 TXEN6 NC VDD SA4 SA6 SA7 SA5

RXD1.7 TXD0.7 RXD0.7 NC GND GND GND GND GND GND GND VDD SA3 SA2 SA13 SA0

CSRV7 TXD1.7 TXEN7 NC GND GND GND GND GND GND GND SA10 SA11 SA12 SA13 SA14

RXD1.8 TXD1.8 CSDV8 TXEN8 NC GND GND GND GND GND GND SA15 SA16 SA17 SA9 SA8

TXD0.8 RXD0.8 CSDV9 TXEN9 NC GND GND GND GND GND GND GND SD0 SD3 SD2 SD18

TXD1.9 RXD1.9 TXD0.9 NC VDD GND GND GND GND GND GND GND SD4 SD7 SD6 SD5

RXD0.9 RXD0.10TXD0.10TXEN10VDD GND GND GND GND GND GND SD11 SD12 SD10 SD9 SD8

RXD1.10TXD1.10CSDV10NC VDD VPP SADS# SD15 SD14 SD13

RXD0.11TXD0.11RXD1.11TXEN11VDD VPP SOE# SCS1# SCS0# SWE#

TXD1.11CSDV11RXD0.12TXEN12NC GND GND SCS3# SCS2# HA0 HCS# SCS4#

TXD0.12RXD1.12TXD1.12NC GND GNDI GNDI HCLK HD15 INTRQ HA1 HA2

CSDV12RXD0.13TXD0.13NC GNDI VDDI VDD VDD GND GND GND GNDI HD1 HD0 IOW# IOR#

RXD1.13TXEN13TXD1.13NC VDDI VDD VDD NC VPP VPP NC NC GND GND NC NC VPP VPP VPP TEST12 VDDI GND HD3 HD13 HD2 HD14

CSDV13CSDV14TXD1.14NC EEC NC NC NC NC NC NC NC NC NC NC NC NC NC TEST7 TEST11 TEST16 TEST17 HD5 HD11 HD4 HD12

RXD1.14TXD0.14RXD1.15TXEN15EEIO NC NC NC NC NC NC NC NC NC NC NC NC TEST3 TEST6 TEST10 TEST15 TEST20 TEST23 HD9 HD6 HD10

RXD0.14CSDV15TXD0.15MDC NC NC NC NC NC NC NC NC NC NC NC NC NC TEST2 TEST5 TEST9 TEST14 TEST19 TEST22 TEST25 HD8 HD7

TXEN14TXD1.15RXD0.15MDIO NC NC NC NC NC NC NC NC NC NC NC NC NC TEST1 TEST4 TEST8 TEST13 TEST18 TEST21 TEST24 TEST26 RESET

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VIA Technologies, Inc. Preliminary VT6516 Datarsheet

MII-mode Ballout Diagram

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

CRS1 RXD3_0COL0 TXD1_0RXD0_0MD1 MD32 MD34 MD36 MD38 MD40 MD42 MD14 CAS1# MA0 MA4 MA8 BA0 DCS1# DWE1# MD18 MD20 MD22 MD24 MD57 MD58

RXD1_1RXDV0 TXD3_0RXD2_0CRS0 TXD0_0MD0 MD2 MD4 MD6 MD8 MD10 MD46 CAS0# MA1 MA5 MA9 BA1 DCS0# MD16 MD50 MD52 MD54 MD56 MD26 MD27

TXEN1 TXD1_1TXD0_1TXD2_0TXEN0 RXD1_0MD33 MD35 MD37 MD39 MD41 MD43 MD13 MD15 RAS1# MA2 MA6 MA10 DCS3# MD48 MD19 MD21 MD23 MD25 MD59 MD28

TXD3_1RXD0_1COL1 NC NC NC MD3 VSS MD7 MD9 MD11 MD12 MD44 RAS0# MA3 MA7 MA11 DCS2# DWE0# MD17 MD51 MD53 MD55 MD60 MD29 MD61

RXD2_1RXDV1 RXD3_1NC VDD GND VSS MD5 VCC VCC VCC MD45 MD47 VSS VSS VSS VCC VCC VCC MD49 NC GND DCLK MD30 MD62 MD31

RXD1_2TXD2_1RXD0_2TXEN2 RCLK50VDD VSS NC NC VSS GND VDD MD63 SD16 SD17 SD18

RXD2_2TXD0_2TXD1_2COL2 VCC VSS VSS SCLK SD19 SD20 SD21 SD22

TXD3_2CRS2 TXD2_2RCLK2 VCC VCC NC SD23 SD24 SD25 SD26 SD27

TXD0_3RXD3_2RXDV2 TCLK2 VCC VCC SD31 SD28 SD29 SD30

RXD0_3CRS3 TXD1_3RXD1_3TXEN3 VCC SA4 SA6 SA7 SA5

RXD3_3TXD2_3RXD2_3RCLK3 VSS VSS VSS VSS VSS VSS VSS VCC SA3 SA2 SA1 SA0

RXDV3 TXD3_3COL3 TCLK3 VSS VSS VSS VSS VSS VSS VSS SA10 SA11 SA12 SA13 SA14

TXD0_4RXD1_4TXD1_4CRS4 TXEN4 VSS VSS VSS VSS VSS VSS SA15 SA16 SA17 SA9 SA8

TXD3_4RXD0_4RXDV4 COL4 RCLK4 VSS VSS VSS VSS VSS VSS VSS SD0 SD3 SD2 SD1

RXD2_4RXD3_4TXD2_4TCLK4 VCC VSS VSS VSS VSS VSS VSS VSS SD4 SD7 SD6 SD5

RXD1_5RXD0_5TXD0_5TXEN5 VCC VSS VSS VSS VSS VSS VSS SD11 SD12 SD10 SD9 SD8

RXD2_5TXD1_5CRS5 TCLK5 VCC VCC SADS# SD15 SD14 SD13

TXD3_5TXD2_5RXD3_5COL5 VCC VCC SOE# SCS1# SCS0# SWE#

TXD0_6RXDV5 RXD0_6TXEN6 RCLK5 VSS VSS SCS3# SCS2# HA0 HCS# SCS4#

CRS6 RXD1_6TXD1_6TCLK6 VSS GND GND HCLK HD15 INTRQ#HA1 HA2

RXD3_6RXD2_6TXD2_6RCLK6 GND VDD VCC VCC VSS VSS VSS GND HD1 HD0 IOW# IOR#

RXDV6 COL6 TXD3_6TCLK7 VDD VCC VCC NC VCC VCC TCLK9 RXD3_10VSS VSS CRS10 RCLK11VCC VCC VCC TEST12 VDD VSS HD3 HD13 HD2 HD14

RXD1_7CRS7 TXD1_7RCLK7 EEC RCLK8 TCLK8 RXD3_9RXD2_9RCLK9 TXD2_9RXD2_10RCLK10TCLK10RXD3_11RXDV11TCLK11CRS11 TEST7 TEST11 TEST16 TEST17 HD5 HD11 HD4 HD12

RXD0_7TXD0_7RXD3_7COL7 EEIO RXD0_8TXD0_8TXD3_8RXD1_9TXEN9 TXD3_9RXD1_10TXEN10TXD2_10RXD2_11TXEN11TXD2_11TEST3 TEST6 TEST10 TEST15 TEST20 TEST23 HD9 HD6 HD10

TXEN7 RXDV7 TXD2_7MDC RXD2_8RXDV8 TXD1_8COL8 RXD0_9TXD0_9COL9 RXD0_10TXD0_10TXD3_10RXD1_11TXD0_11TXD3_11TEST2 TEST5 TEST9 TEST14 TEST19 TEST22 TEST25 HD8 HD7

TXD3_7RXD2_7MDIO RXD3_8RXD1_8TXEN8 TXD2_8CRS8 RXDV9 TXD1_9CRS9 RXDV10TXD1_10COL10 RXD0_11TXD1_11COL11 TEST1 TEST4 TEST8 TEST13 TEST18 TEST21 TEST24 TEST26 RESET

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VIA Technologies, Inc. Preliminary VT6516 Datarsheet

LOGIC SYMBOL

HA[2:0]

HD[15:0]

HCS

IOR

IOW

INTRQ

TCLK[11:0]

TXD0[11:0] TXD1[11:0] TXD2[11:0] TXD3[11:0]

TXEN[11:0]

COL[11:0]

CRS[11:0] RXD0[11:0] RXD1[11:0] RXD2[11:0] RXD3[11:0] RCLK[11:0]

RXDV[11:0]

CRS_DV[15:0]

RXD0[15:0] RXD1[15:0]

TXEN[15:0] TXD0[15:0]

TXD1[15:0]

16 16

12 12 12 12 12 12 12 12 12 12 12 12 12 12

HOST

Interface

MII

Interface

RMII

Interface

VT6516

Miscellaneous

Interface

SDRAM

Interface

SRAM

Interface

64 12

32 18

2 2 2 2 4

MD[63:0] MA[11:0]

BA[1:0] RAS[1:0] CAS[1:0] DWE[1:0] DCS[3:0]

SD[31:0]

SA[17:0] SCS[4:0] SADS SOE SWE

EEC EEIO MDC MDIO RCLK50 DCLK SCLK HCLK RESET

TEST[26:1]

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VIA Technologies, Inc. Preliminary VT6516 Datarsheet

RAS

CAS

DWE

DCS

SCS

SADS

SOE

SWE

PIN DESCRIPTIONS

No. Name Type Description

SDRAM Interface

See Ball

Table

See Ball

Table

See Ball

Table

MD[63:0] I/O

MA[11:0] O

BA[1:0] O

SDRAM Data:

64-bit SDRAM data bus. These signals connect directly to the data input/output pins of the SDRAM devices.

SDRAM Address Bus:

12-bit SDRAM data bus. These signals connect directly to the address input of the SDRAM devices.

Bank Identifier for Bank 0 and 1:

See Ball

Table

See Ball

Table

See Ball

Table

See Ball

Table

See Ball

Table

See Ball

Table

See Ball

Table

See Ball

Table

[1:0]

[3:0]

SD[31:0] I/O

SA[17:0] O

[4:0]

[1:0]

Row Address Strobes for Bank 0 and 1:

DRAM row address strobes. for Bank 1.

Column Address Strobes for Bank 0 and 1:

DRAM column address strobes. used for Bank 1.

DRAM Write Enable for Bank 0 and 1:

DRAM Chip Select:

VT-3061A supports at most 4 SDRAM DIMM modules.

SRAM Interface

SRAM Data:

32-bit SRAM data bus. These signals connect directly to the data input/output pins of the SRAM devices.

SRAM Address Bus:

18-bit SDRAM data bus. These signals connect directly to the address input of the SDRAM devices.

SRAM Chip Select:

SRAM Type Chip Select Pins Address Pins

---------------- ---------------------- -----------------32KBx32 SCS[0] & SA[15] SA[14:0] 64KBx32 SCS[0] & SA[16] SA[15:0] 128KBx32 SCS[0] & SA[17] SA[16:0] 256KBx32 SCS[0] SA[17:0]

Synchronous Processor Address Status

[0] is used for Bank 0.

[1] is used

[1] is

See Ball

Table

See Ball

Table

[1:0]

Output Enable

SRAM Write Enable:

Miscellaneous Interface

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VIA Technologies, Inc. Preliminary VT6516 Datarsheet

RESET

See Ball

Table

See Ball

Table

See Ball

Table

See Ball

Table

See Ball

Table

See Ball

Table

See Ball

Table

EEC O

EEIO I/O

MDC O

MDIO I/O

RCLK50 I

DCLK I

SCLK I

Serial EEPROM Interface Clock Output:

EEPROM Device Addressing in the demo board: PAGE 0 (EEPROM): Device Address = 1010 000 XXXXXXXX PAGE 1 (EEPROM): Device Address = 1010 001 XXXXXXXX PAGE 2 (EEPROM): Device Address = 1010 010 XXXXXXXX PAGE 3 (EEPROM): Device Address = 1010 011 XXXXXXXX PAGE 4 (SDRAM BANK-0): Device Address = 1010 100 XXXXXXXX PAGE 5 (SDRAM BANK-1): Device Address = 1010 101 XXXXXXXX

Serial EEPROM Interface Data I/O

Management Interface (MI) Clock Output

Management Interface (MI) Data I/O

Main Reference Clock:

SDRAM Reference Clock:

SRAM Reference Clock

See Ball

Table

See Ball

Table

See Ball

Table

HCLK O

SYSLED[26:0 ]

HOST Reference Clock

HCLK is determined by the strapping pins in SYSLED[3:1], i.e. the jump selection of J1[5-6, 3-4, 1-2]:

J1[OFF,OFF,OFF] => 8MHz J1[ OFF,OFF, ON] => 16MHz J1[OFF, ON, OFF] => 25MHz J1[OFF, ON, ON] => 4MHz J1[ ON,OFF,OFF] => 33MHz

SYSTEM RESET

SYSTEM Output Pins for LED:

SYSLED[8:0] are connected to pull-up IO PADs for strapping. SYSLED[25:9] are connected to IO PADs without pull up/down. All SYSLED[25:0] are

HOST Interface

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VIA Technologies, Inc. Preliminary VT6516 Datarsheet

HCS

IOR

IOW

See Ball

Table

See Ball

Table

See Ball

Table

See Ball

Table

See Ball

Table

See Ball

Table

HA[2:0] I

HD[15:0] I/O

INTRQ O

HOST IDE-Interface Address Bus:

3’b000: command the switch that the whole 16-bit data in the HOST data

bus HD[15:0] is valid for packet-data read/write.

3’b001: command the switch that only the 8-bit data in the HOST data bus

HD[15:0] is valid for internal registers read/write.

3’b010: command the switch to write the low byte in the HOST data bus

HD[15:0] into the low byte of the 16-bit switch address register for internal registers reference.

3’b011: command the switch to write the low byte in the HOST data bus

HD[15:0] into the high byte of the 16-bit switch address register for internal registers reference.

3’b1xx: bus-idle command. Keep this address bus to be 3’b111 as the

HOST has no access to VT-3061A.

HOST IDE-Interface Data Bus:

The whole 16-bit data bus is valid for packet data read/write. However, only the 8-bit data bus is valid for internal registers read/write.

HOST Chip Select:

Active LOW.

must be asserted during the access of HOST IDE

interface.

IO READ:

High-to-Low Edge Trigger.

must be asserted from high to low to

begin the read cycle of HOST IDE interface.

IO READ:

High-to-Low Edge Trigger.

must be asserted from high to low to

begin the write cycle of HOST IDE interface.

Interrupt Request:

Connected to the HOST external interrupt pin. It is asserted as the following four interrupt events happen:

(1) MII Management Registers read/write command done (2) EEPROM read/write command done (3) Receiving a packet destined to HOST (4) Finishing transmission of a packet issued by HOST The interrupt cause is recorded in register IRQSTS[3:0] in address 2000H.

To clear the individual interrupt, The corresponding register has to be written:

(1) register CLR_PHY_INT in 1806H for PHY interrupt. (2) register CLR_EE_INT in 1C04H for EEPROM interrupt. (3) register CLR_RCV_INT in 6403H for packet-receiving interrupt.

l register CLR_SENT_INT in 6411H for packet-sent interrupt.

MII Interface

See Ball

Table

TCLK[11:0] I

Transmit Clock for Port 0-11:

TCLK is driven by the PHY device. TCLK is a continuous clock that provides the timing reference for the transfer of the TXEN and TXD signals to the PHY. A PHY operating at 100Mbps must provide a TCLK frequency of 25MHz and a PHY operating at 10Mbps must provide a TCLK frequency of 2.5MHz.

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VIA Technologies, Inc. Preliminary VT6516 Datarsheet

See Ball

Table

See Ball

Table

See Ball

Table

See Ball

Table

See Ball

Table

See Ball

Table

See Ball

Table

Note: Some flat MII input pin when the VT6516 under the RMII application, please use 22 ohm resister pull down, refer to Table XXXX

TXD<3:0>[11:0]O

TXEN[11:0] O

COL[11:0] I

CRS[11:0] I

RXD<3:0>[11 :0]

RCLK[11:0] I

RXDV[11:0] I

Transmit Data for Port 0-11:

TXD is a bundle of 4 data signals (TXD<3:0>) that shall transition to the TCLK. For each TCLK period in which TXEN is asserted, TXD<3:0> are accepted for transmission by the PHY. TXD<0> is the least significant bit. While TXEN is de-asserted, TXD<3:0> shall have no effect upon the PHY, and the value of TXD<3:0> is unspecified.

Transmit Enable for Port 0-11:

TXEN shall transition synchronous to the TCLK. TXEN indicates the nibbles presenting on the MII for transmission. It shall be asserted synchronously with the first nibble of the preamble and shall remain asserted while all nibbles to be transmitted are presented to the MII.

Collision Detected for Port 0-11:

COL shall be asserted by the PHY asynchronously upon detection of a collision on the medium, and shall remain asserted while the collision condition persists.

Carrier Sense for Port 0-11:

CRS shall be asserted by the PHY asynchronously upon detection of a non-idle medium or while TX_EN is asserted. CRS shall be de-asserted by the PHY asynchronously upon detection of idle conditions on both transmit and receive media. The PHY shall ensure that CRS remains asserted throughout the duration of a collision condition.

Receive Data for Port 0-11:

RXD is a bundle of 4 data signals (RXD<3:0>) that shall transition to the RCLK. For each RCLK period in which RXDV is asserted, RXD<3:0> from the PHY are accepted by the switch’s MAC. RXD<0> is the least significant bit. While RXDV is de-asserted, RXD<3:0> shall have no effect upon the switch’s MAC, and the value of RXD<3:0> is unspecified.

Receive Clock for Port 0-11:

RCLK is sourced from the PHY. RCLK is a continuous clock that provides the timing reference for the transfer of the RXDV and RXD signals from the PHY. A PHY operating at 100Mbps must provide a RCLK frequency of 25MHz and a PHY operating at 10Mbps must provide a RCLK frequency of 2.5MHz.

Receive Data Valid for Port 0-11:

RXDV is driven by the PHY to indicate the nibbles presenting on the MII for receiving. RXDV shall transition synchronous to the RCLK. It shall be asserted synchronously with the first nibble of the preamble and shall remain asserted while all nibbles to be received are presented to the MII.

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VIA Technologies, Inc. Preliminary VT6516 Datarsheet

RMII interface

See Ball

Table

See Ball

Table

See Ball

Table

See Ball

Table

See Ball

Table

See Ball

Table

Power Supply & Ground

See Ball

Table

See Ball

Table

CRS_DV[15:0]I Carries sense and data valid from port 15 to port 0 :

RXD0[15:0] I Receive data zero from port 15 to port 0 :

RXD1[15:0] I Receive data one from port 15 to port 0 :

TXEN[15:0] O Transmit enable from port 15 to port 0 :

TXD0[15:0] O Transmit data zero from port 15 to port 0 :

TXD1[15:0] O Transmit data one from port 15 to port 0 :

VDD, VDDA P Positive 3.3V Supply: Supply power to Internal digital logic, Digital I/O

VSS, VSSA G Negative Supply: digital ground. Multiple bonding pads are required to

pads, and TD, TX pads. Double bonding may be required.

separate core and I/O pads ground.

JUMPER STRAPPING

Jumper Pin Description HOST Clock J1 [5-6], [3-4], [1-2]SYSLED[3:1]HOST Clock (HCLK) Rate Selection:

J1[OFF,OFF,OFF] (SYSLED[3:1]==3’b111) => 8MHz J1[ OFF,OFF, ON] (SYSLED[3:1]==3’b110) => 16MHz J1[OFF, ON, OFF] (SYSLED[3:1]==3’b101) => 25MHz J1[OFF, ON, ON] (SYSLED[3:1]==3’b100) => 4MHz

J1[ ON,OFF,OFF] (SYSLED[3:1]==3’b011) => 33MHz PHY Mode J1 [7-8] SYSLED[4] PHY Device Selection:

J1[OFF] (SYSLED[4]==1’b1) => RMII PHY

J1[ ON] (SYSLED[3:1]==1’b0) => MII PHY SRAM Type J1 [11-12,9-10] SYSLED[6:5]SRAM Device Type Selection:

J1[OFF,OFF] (SYSLED[6:5]==2’b11) => 64K x 32 SRAM

J1[OFF,ON] (SYSLED[6:5]==2’b10) => 128K x 32 SRAM

J1[ON,OFF] (SYSLED[6:5]==2’b01) => 32K x 32 SRAM

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VIA Technologies, Inc. Preliminary VT6516 Datarsheet

SECTION I FUNCTIONAL DESCRIPTIONS

1. GENERAL DESCRIPTION

The VT6516 is a switch engine chip implementation of a 16 ports 10/100M Ethernet switch system for IEEE

802.3 and IEEE 802.3u network. Each of individual port can be either auto-sensing or manually selected to run at 10Mbps or 100Mbps speed rate and under full or half duplex mode.

There are sixteen independent MACs within the VT6516 chip. The MAC controller controls the receiving, transmitting, and deferring of each individual port, and the MAC controller also provides framing, FCS checking, error handling, status indication and flow control function.

The VT6516 10/100M N-way switch port IC is wire-speed performance and low-cost packet switch; it can forward up to 148,810 packets/sec on each Ethernet port. The VT6516 support 12 ports MII or 16 ports RMII (reduce MII) interface for network interface,

The VT6516 used the simple 8/16 bits ISA-like interface to support initiation, expansion and management. The system CPU can access various registers inside VT6516 through a simple ISA-like CPU interface. The CPU can configure the switch by writing into the appropriate registers, or retrieve the status of the switch by reading the corresponding registers. The CPU can also access the register of external transceiver (PHY) device through the CPU interface.

The VT6516 supports new features including port based VLAN , 802.3X flow control, and the VT6516 also support the sniffer function to monitor network traffic in special ports.

2. THE VIA ETHER SWITCH ARCHITECTURE

The VT6516 switch engine uses the shared memory architecture. In order to improve the packet latency, VT6516 provides two methods for packet switching, one is cut-through, another is store-and-forwarding. A typical packet flow for Ethernet switch is described as follows in 4.5.

2.1 Switch initialization procedures

1. Test all of the on board components except the switch chip or access VIA the switch chip, including UART,

LED, etc.

2. Switch SDRAM test --- switch chip SDRAM control hardware initialization, configuration, SDRAM size

determination (VIA embedded EEPROM in SDRAM module) and read write test.

3. Switch SRAM test --- switch chip SDRAM control hardware initialization and read write test. Note that the

SRAM size determination is VIA strapping.

4. Switch IO registers read write test.

5. Ethernet PHY registers read write test ---- the CPU read/write to PHY devices will go through PHY

control in switch chip. Although they are outside components, but we test them as part of the switch chip.

6. Determine link table size; reset free buffer list pointers of bank 0 and 1; initialize free memory block counter.

Note that permanent buffer management is controlled by allocating bit mask. They will be cleared

automatically in the hardware reset or software reset.

2.2 Packet Switching Flow

1. After the switch microprocessor activates a port during initialization, the input control of that port pre-

allocates one packet buffer from buffer pool. In the beginning, the buffer allocated will be from private buffer

pool, but subsequent buffers may come from either private or public buffer pools.

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VIA Technologies, Inc. Preliminary VT6516 Datarsheet

2. When receive MAC (RMAC) receives a packet data from the network interface – either through MII or

reduced MII (RMII) – it packs the data into 16-bit word then passes it to input control. If RMAC detects any

error, it also notifies input control to stop forwarding process.

3. Input control extracts the destination MAC address from incoming data, passes it along to forwarding table

control for forwarding decision. In the mean while, it packs 16-bit words into 64-bit quad-words, and saves

it to an input FIFO before storing the packet data to SDRAM.

4. If the switch is configured to “store and forward” mode, input control queues the packet to the output queue

of the destination port after input control is informed by RMAC that this is a good packet and it stores all

packet data to SDRAM. If the switch is configured to “cut-through” mode, the input control queues the

packet to the output queue of the destination port after enough amount of packet is stored in SDRAM to

prevent output FIFO under-run.

5. After the whole packet is received and FCS is correct, input control pass the source MAC address of the

packet to forwarding table control for address learning.

6. Output control of the outbound port de-queue the packet from output queue, and fetch packet data from

SDRAM and save it into output FIFO. Then it notifies the transmit MAC (TMAC) of the new packet to

transmit.

7. TMAC grabs 16-bit at a time from output control, adds preamble and SFD to the beginning of the packet,

then send them out. Proper deferring is done if necessary to conform to 802.3 standard.

8. After the packet is successfully transmitted, TMAC notifies output control of the successful transmission.

Output control then returns the packet to buffer pool.

3. INTERFACE DESCRIPTIONS

BUFFER MEMORY (SDRAM) INTERFACE AND TABLE (SSRAM) INTERFACE

VT6516 provides a 64-bit SDRAM/SGRAM interface for packet buffering and a 32-bit synchronous SRAM (SSRAM) interface for maintaining address table and various link lists. VT6516 uses SDRAM as packet buffers. Each packet buffer is a 1536-byte contiguous memory block in SDRAM, and corresponds to a 12-byte link node data structure in SSRAM. Except the first 128 link nodes, each link node can be part of an output queue, a free buffer link list, or held in input or output control. The first 128 link nodes are divided into 16 groups, each pre-assigned to a specific input control, and bit-mapped inside buffer control for faster allocate/free operation and reduce SSRAM usage.

Initially, each input port control would request one packet buffer from its private buffer pool. Each time when a packet buffer is consumed by an incoming packet, the input port control will request another packet buffer to prepare for next packet. The common shared packet memory will be allocated only when there’s no free permanent packet memory for that port. See Figure 3-4.

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VIA Technologies, Inc. Preliminary VT6516 Datarsheet

128 entries

SRAM

12 bytes/entry

Permanent Buffer

Table

12 bytes/entry

Free List

Link Table

Address Table

Entriers

DRAM

1.5 K/Packet

...

1.5 K/Packet

128 blocks

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VIA Technologies, Inc. Preliminary VT6516 Datarsheet

List 0 List 1

Link/ Frame

128/0

129/0

130/1

131/0

132/1

133/1

134/0

135/1

136/0

16MBits SDRAM

Memory Bank

Bank 0 Bank 1

List 0 List 1

Links/ List

128/0

129/0

130/0

131/1

132/1

133/1

134/0

135/0

136/1

137/1

Memory Bank

64MBits SDRAM

Bank 0 Bank 1

Figure 3-3

Following as the listing and figure 3-6 is the algorithm of initialization procedures for 2 bank free list of

SDRAM.

For 16 Mbit SDRAM as following,

-- Bank0 free link list:

128, 129, 131, 134, 136, 137, 139, 142, 144, 145, 147, 150, 152, 153, 155, 158, 160,...

-- Bank1 free link list:

130, 132, 133, 135, 138, 140, 141, 143, 146, 148, 149, 151, 154, 156, 157, 159, 162, 164, ...

For 64 Mbit SDRAM as following,

-- Bank0 free link list:

128 , 129 , 130 , 134 , 135 , 139 , 140 , 141 , 144 , 145 , 146 , 150 , 151 , 155 , 156 , 157 , 160 , ...

--Bank1 free link list:

131 , 132 , 133 , 136 , 137 , 138 , 142 , 143 , 147 , 148 , 149 , 152 , 153 , 154 , 158 , 159 , 163 , …

Figure 3-6: Algorithm of Initialization of Free Link Lists.

#define SRAM_ADDR_REG0 0x2001 #define SRAM_ADDR_REG1 0x2002 #define SRAM_ADDR_REG2 0x2003 #define SRAM_DATA_REG0 0x2004 #define SRAM_DATA_REG1 0x2005 #define SRAM_DATA_REG2 0x2006 #define SRAM_DATA_REG3 0x2007 #define SRAM_CMD_REG 0x2008 #define SRAM_STATUS_REG 0x2009 #define SRAM_ACCESS_IDLE 0x01 #define NULL_PTR 0x7FFFF

void writeLinkEntry(int entryID, int nextID) { reg_byte_write (SRAM_ADDR_REG0, entryID*3 & 0x0FF); reg_byte_cont_write (((entryID*3) >> 8) & 0x0FF); reg_byte_cont_write (((entryID*3) >> 16) & 0x0FF);

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VIA VT6516 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual