Via PLE133 User Manual

Data Sheet

Apollo PLE133 North Bridge

Revision 1.86 April 22, 2005

VIA TECHNOLOGIES, INC.

Copyright ©1998-2005 VIA Technologies Incorporated. All Rights Reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise without the prior written permission of VIA Technologies Incorporated. The material in this document is for information only and is subject to change without notice. VIA Technologies Incorporated reserves the right to make changes in the product design without reservation and without notice to its users.

Trademark Notices:

VT82C586B, VT82C596B, VT82C686A, VT82C686B, VT82C598, VT82C598MVP, VT8501, VT82C691, VT82C692, VT82C693, VT82C693A, VT82C694, VT82C694A, VT82C694X, VT8601, VT8601A, VT8602, Mobile South, Super South, Apollo MVP3, Apollo MVP4, Apollo Pro, Apollo ProPlus, Apollo Pro133, Apollo Pro133A, Apollo PM601, and Apollo PLE133 may only be used to identify products of VIA Technologies.

VIA C3 PS/2 Celeron, Pentium AMD6 Windows 95 PCI All trademarks are the properties of their respective owners.

is a registered trademark of VIA Technologies, Inc.

is a registered trademark of International Business Machines Corporation.

86TM, AMD-K6TM, and AMD-K6-2TM are registered trademarks of Advanced Micro Devices Corporation.

is a registered trademark of the PCI Special Interest Group.

, Pentium-IITM, Pentium-IIITM, MMXTM, and Intel are registered trademarks of Intel Corporation.

, Windows 98TM, and Plug and PlayTM are registered trademarks of Microsoft Corporation.

Disclaimer Notice:

No license is granted, implied or otherwise, under any patent or patent rights of VIA Technologies, Inc. VIA Technologies makes no warranties, implied or otherwise, in regard to this document and to the products described in this document. The information provided by this document is believed to be accurate and reliable as of the publication date of this document. However, VIA Technologies assumes no responsibility for any errors in this document. Furthermore, VIA Technologies assumes no responsibility for the use or misuse of the information in this document and for any patent infringements that may arise from the use of this document. The information and product specifications within this document are subject to change at any time, without notice and without obligation to notify any person of such change.

Offices:

VIA Technologies Incorporated Taiwan Office:

Floor, No. 531

1 Chung-Cheng Road, Hsin-Tien Taipei, Taiwan ROC Tel : (886-2) 2218-5452 Fax : (886-2) 2218-5453

Home page :

http ://www.via.com.tw

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Home Page :

http ://www.viatech.com

Apollo PLE133 Data Sheet

REVISION HISTORY

Document Release Date Revision Initials

0.92 12/9/98 Initial internal release DH

0.93 12/16/98 Updated pinouts to match engineering rev 0.5 document dated 12/1/98 DH

0.94 1/20/99 Updated pinouts to match engineering rev 0.8 document dated 12/22/98 DH

1.0 6/4/99 Added 133 MHz Support to Feature Bullets Updated / Fixed Pin Descriptions: Fixed description of strap options on MA2, MA8,

and MA11-14; Removed Auxiliary Memory Port; Added REQ/GNT[4-7]#; Added GND & VCC3 pins to increase pin count to 510 (updated mech spec); Fixed definitions of RESET# & CRSTI# and changed CRSTI# to CPURSTD#; Removed PWRGD function from SERR#; Fixed definitions of SRAS#, SCAS#, and SWE#; Added note to PLLTST description

Updated Device 0 Rx50-53, 68[4], 69, 6B[5-1], 6C[7-4], 70[3,0, 72[0], 76[7], 79[1-

0], 7A (added); Device 1 Rx41[0], 42[0]

1.1 6/23/99 Updated feature bullets & overview and fixed misc formatting problems Fixed REQ/GNT4# pinouts and CKE & DQM naming polarity Device 0 Bus 0 updated Rx2-3 Device ID, 69[7-6], 6D[6-5], 76[6] Device 0 Bus 0 added Rx2C-D, 2E-F, 50[1], 51[5], 53[2], removed 6E-6F Device 0 Bus 1 updated Rx0-3 Vendor & Device ID, Rx7-6[7] Removed AC timing specs

1.11 7/8/99 Fixed pin descriptions of CPURSTD# and SUSP DH

1.2 8/23/99 Fixed typo in device 0 Rx50[7] description; added comment about default state Fixed system freq divider settings (MA pin descriptions, Dev 0 Rx68[1-0])

1.3 9/8/99 Fixed strap options on MA2-6 and MA13 pin descriptions Fixed Device 0 Rx52[7] strap option and removed (reserved) Device 0 Rx52[5] Removed “VIA Confidential” watermark

1.4 2/2/00 Added DSTN modes to intro/overview panel interface section Removed incorrect notes under CPU interface pin descriptions Fixed MA11 strapping and VCC3/VSUS3 pin descriptions Fixed Device 0 Bus 0 Rx50[1] and Rx51[1] defaults Fixed Electrical Specs absolute max temp ratings

1.5 10/24/00 Changed product name to Apollo PLE133; Fixed typos in pinout table Changed temp specs to be based on case instead of ambient; added power table Changed orientation of pin 1 in mech diagram to match part marking

1.6 11/1/00 Fixed product name on cover page; Fixed strap descriptions Fixed Rx50[7], Rx68[1-0], 6B[4], 6C[4], D0Bus1 Rx4[9], Graphics CR39[0]

1.7 12/1/00 Removed EDO, FP, VCM and PC66 DRAM support (no longer fully tested) Added VIA Cyrix III CPU to supported CPUs list and changed 686A to 686B Added PLLTST pin I/O type Fixed table formatting errors introduced as a result of Word 2000 upgrade Fixed Rx6B[4] and 6C[4]; Fixed spelling errors in Functional Description

1.71 4/26/01 Fixed various typographical and formatting errors DH

1.8 7/3/01 Updated company address; updated processors list Removed LVDS and direct panel drive support; removed MA3-6 straps Fixed SUSP pin description; Fixed Device 0 Rx6A; moved VGA regs intro

1.81 10/8/01 Clarified the difference between chipset name and north bridge part number Changed “VIA Cyrix III” to “VIA C3”; Fixed max memory to be 1.5GB Updated Device 0 Rx68[4], 69[7-6, 1], 6B[1]; Updated chip marking specs

1.82 10/22/01 Fixed strap pin definitions for MA14,12,11 & updated Rx50[7], 68[1-0] to match DH

1.83 4/22/02 Updated cover and page header logos; updated legal page addresses and phone #’s DH

1.84 7/22/02 Fixed Device 0 Rx50[7] DH

1.85 12/10/04 Added lead-free package in Mechanical Specifications VL

1.86 4/22/05 Revised top marking of Mechanical Specifications SV

Revision 1.86, April 22, 2005 -i- Revision History

Apollo PLE133 Data Sheet

TABLE OF CONTENTS

REVISION HISTORY .......................................................................................................................................................................I

TABLE OF CONTENTS.................................................................................................................................................................. II

LIST OF FIGURES .........................................................................................................................................................................IV

LIST OF TABLES ...........................................................................................................................................................................IV

PRODUCT FEATURES.................................................................................................................................................................... 1

SYSTEM OVERVIEW...................................................................................................................................................................... 6

APOLLO PLE133 CORE LOGIC OVERVIEW ................................................................................................................................. 7

APOLLO PLE133 GRAPHICS CONTROLLER OVERVIEW ............................................................................................................. 8

Capability Overview............................................................................................................................................................... 8

System Capabilities................................................................................................................................................................. 9

High Performance 64-bit 2D GUI ......................................................................................................................................... 9

Highly Integrated RAMDACTM & Clock Synthesizer......................................................................................................... 9

Full Feature High Performance 3D Engine.......................................................................................................................... 9

Video Processor..................................................................................................................................................................... 10

Video Capture and DVD...................................................................................................................................................... 10

Versatile Frame Buffer Interface........................................................................................................................................ 10

Hi-Res and Hi-Ref Display Support.................................................................................................................................... 10

CRT Power Management (VESA DPMS).......................................................................................................................... 11

Flat Panel Monitor Interface............................................................................................................................................... 11

Video Capture Interface....................................................................................................................................................... 11

Complete Hardware Compatibility..................................................................................................................................... 11

PINOUTS.......................................................................................................................................................................................... 12

PIN DESCRIPTIONS....................................................................................................................................................................... 15

REGISTERS..................................................................................................................................................................................... 23

REGISTER OVERVIEW ................................................................................................................................................................. 23

REGISTER SUMMARY TABLES..................................................................................................................................................... 23

MISCELLANEOUS I/O................................................................................................................................................................... 33

CONFIGURATION SPACE I/O ....................................................................................................................................................... 33

REGISTER DESCRIPTIONS ........................................................................................................................................................... 34

Device 0 Bus 0 Header Registers - Host Bridge ................................................................................................................. 34

Device 0 Bus 0 Host Bridge Registers ................................................................................................................................. 36

CPU Interface Control........................................................................................................................................................................... 36

DRAM Control...................................................................................................................................................................................... 39

PCI Bus Control ....................................................................................................................................................................................44

GART / Graphics Aperture Control ......................................................................................................................................................48

AGP Control.......................................................................................................................................................................................... 50

Device 1 Bus 0 Header Registers - PCI-to-AGP Bridge .................................................................................................... 52

Device 1 Bus 0 PCI-to-AGP Bridge Registers.................................................................................................................... 54

AGP Bus Control................................................................................................................................................................................... 54

Device 0 Bus 1 Header Registers - Graphics Accelerator ................................................................................................. 55

Device 0 Bus 1 Graphics Accelerator Registers ................................................................................................................. 58

Graphics Accelerator PCI Bus Master Registers ................................................................................................................................... 59

Capture / ZV Port Registers...................................................................................................................................................................64

DVD Registers ......................................................................................................................................................................................65

VGA Registers ...................................................................................................................................................................... 68

VGA Standard Registers - Introduction................................................................................................................................................. 68

Revision 1.86, April 22, 2005 -ii- Table of Contents

Apollo PLE133 Data Sheet

Attribute Controller Registers (AR) ......................................................................................................................................................69

VGA Status / Enable Registers.............................................................................................................................................................. 69

VGA Sequencer Registers (SR)............................................................................................................................................................. 70

VGA RAMDAC Registers .................................................................................................................................................................... 70

VGA Graphics Controller Registers (GR)............................................................................................................................................. 71

VGA CRT Controller Registers (CR)................................................................................................................................................... 72

VGA Extended Registers ..................................................................................................................................................... 73

VGA Extended Registers – Non-Indexed I/O Ports ..............................................................................................................................73

VGA Extended Registers – Sequencer Indexed ....................................................................................................................................74

VGA Extended Registers – Graphics Controller Indexed .....................................................................................................................84

VGA Extended Registers – CRT Controller Indexed............................................................................................................................ 90

VGA Extended Registers – CRTC Shadow......................................................................................................................................... 104

3D Graphics Engine Registers........................................................................................................................................... 105

Operational Concept............................................................................................................................................................................ 105

Drawing............................................................................................................................................................................................... 106

Geometry Primitives............................................................................................................................................................................ 107

Synchronization................................................................................................................................................................................... 111

Functional Blocks................................................................................................................................................................................ 111

Bus Interface ....................................................................................................................................................................................... 111

Span Engine ........................................................................................................................................................................ 112

Graphics Engine Core........................................................................................................................................................ 113

Graphics Engine Organization.............................................................................................................................................................116

Setup Engine Registers........................................................................................................................................................................ 117

Vertex Registers .................................................................................................................................................................................. 118

Rasterization Engine Registers............................................................................................................................................................ 119

Pixel Engine Registers......................................................................................................................................................................... 126

Texture Engine Registers.....................................................................................................................................................................132

Memory Interface Registers ................................................................................................................................................................134

Data Port Area..................................................................................................................................................................................... 134

FUNCTIONAL DESCRIPTIONS................................................................................................................................................ 135

GRAPHICS CONTROLLER POWER MANAGEMENT.................................................................................................................... 135

Power Management States................................................................................................................................................. 135

Power Management Clock Control................................................................................................................................... 135

Power Management Registers ........................................................................................................................................... 135

ELECTRICAL SPECIFICATIONS ............................................................................................................................................ 136

ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................... 136

DC CHARACTERISTICS.............................................................................................................................................................. 136

POWER CHARACTERISTICS ....................................................................................................................................................... 137

AC TIMING SPECIFICATIONS.................................................................................................................................................... 137

MECHANICAL SPECIFICATIONS........................................................................................................................................... 138

Revision 1.86, April 22, 2005 -iii- Table of Contents

Apollo PLE133 Data Sheet

LIST OF FIGURES

FIGURE 1. VT8601A BALL DIAGRAM (TOP VIEW) ............................................................................................................. 12

FIGURE 2. VT8601A PIN LIST (NUMERICAL ORDER)........................................................................................................ 13

FIGURE 3. VT8601A PIN LIST (ALPHABETICAL ORDER)................................................................................................. 14

FIGURE 4. GRAPHICS APERTURE ADDRESS TRANSLATION......................................................................................... 48

FIGURE 5. PHYSICAL REGION DESCRIPTOR TABLE FORMAT .................................................................................... 60

FIGURE 6. PCI BUS MASTER ADDRESS TRANSLATION................................................................................................... 60

FIGURE 7. FRAME BUFFER PARAMETERS.......................................................................................................................... 97

FIGURE 8. LIVE VIDEO DISPLAY PARAMETERS............................................................................................................... 97

FIGURE 9. MECHANICAL SPECIFICATIONS - 510-PIN BALL GRID ARRAY PACKAGE......................................... 138

FIGURE 10. LEAD-FREE MECHANICAL SPECIFICATIONS - 510-PIN BALL GRID ARRAY PACKAGE............... 139

LIST OF TABLES

TABLE 1. VT8601A PIN DESCRIPTIONS ................................................................................................................................. 15

TABLE 2. REGISTER SUMMARY ............................................................................................................................................. 23

TABLE 3. SYSTEM MEMORY MAP.......................................................................................................................................... 39

TABLE 4. MEMORY ADDRESS MAPPING TABLE ............................................................................................................... 39

TABLE 5. VGA/MDA MEMORY/IO REDIRECTION ............................................................................................................. 54

TABLE 6. SUPPORTED PCI COMMAND CODES .................................................................................................................. 55

TABLE 7. INTERRUPT SOURCES AND CONTROLS............................................................................................................ 57

TABLE 8. GRAPHICS CLOCK FREQUENCIES – 14.31818 MHZ REFERENCE............................................................... 76

TABLE 9. DPMS SEQUENCE - HARDWARE TIMER MODE............................................................................................... 87

TABLE 10. DPMS SEQUENCE - HARDWARE MODE IN SIMULTANEOUS DISPLAY MODE..................................... 87

TABLE 11. HARDWARE CURSOR PIXEL OPERATION ...................................................................................................... 94

TABLE 12. PCI POWER MANAGEMENT STATES.............................................................................................................. 135

TABLE 13. ABSOLUTE MAXIMUM RATINGS..................................................................................................................... 136

TABLE 14. DC CHARACTERISTICS....................................................................................................................................... 136

TABLE 15. DC CHARACTERISTICS....................................................................................................................................... 137

TABLE 16. AC TIMING MIN / MAX CONDITIONS.............................................................................................................. 137

Revision 1.86, April 22, 2005 -iv- Table of Contents

Apollo PLE133 Data Sheet

APOLLO PLE133 NORTH BRIDGE

133 / 100 / 66 MHz

Single-Chip Socket-370 PCI North Bridge,

With Integrated AGP 2D / 3D Graphics Accelerator

and Advanced Memory Controller

supporting PC133 / PC100 SDRAM

For Desktop PC Systems

PRODUCT FEATURES

• General

− 510 BGA Package (35mm x 35mm )

− 2.5 Volt core with 3.3V CMOS I/O

− Supports GTL+ I/O buffer Host interface

− Supports separately powered 5.0V tolerant interface to PCI bus and Video interface

− 2.5V, 0.25um, high speed / low power CMOS process

− PC98 / 99 compatible using VIA VT82C686B (352-pin BGA) south bridge chip for Desktop and Mobile

applications

− 133 / 100 / 66 MHz CPU Front Side Bus (FSB) Operation

• High Integration

− Single chip implementation for 64-bit Slot-1 and Socket-370 CPUs, 64-bit system memory, 32-bit PCI with

integrated 2D / 3D GUI accelerator

− Apollo PLE133 Chipset: VT8601A system controller and VT82C686B PCI to ISA bridge

− Chipset includes dual UltraDMA-100 / 66 / 33 EIDE, AC-97 link, 4 USB ports, integrated Super-I/O, hardware

monitoring, keyboard / mouse interfaces, and RTC / CMOS

• High Performance CPU Interface

− Supports VIA C3 and Intel Celeron

− 133 / 100 / 66 MHz CPU Front Side Bus (FSB)

− Built-in PLL (Phase Lock Loop) circuitry for optimal skew control within and between clocking regions

− Five outstanding transactions (four In-Order Queue (IOQ) plus one input latch)

− Supports WC (Write Combining) cycles

− Dynamic deferred transaction support

− Sleep mode support

− System management interrupt, memory remap and STPCLK mechanism

CPU DRAM GUI Core Internal AGP PCI Comments 133 MHz 133 MHz 100 MHz 66 MHz 33 MHz Synchronous (DRAM uses CPU clock) 133 MHz 100 MHz 100 MHz 66 MHz 33 MHz Pseudo-synchronous (DRAM uses GUI clock) 100 MHz 133 MHz 100 MHz 66 MHz 33 MHz Pseudo-synchronous (DRAM uses GUI clock) 100 MHz 100 MHz 100 MHz 66 MHz 33 MHz Synchronous (DRAM uses CPU clock) 100 MHz 66 MHz 66 MHz 66 MHz 33 MHz Pseudo-synchronous (DRAM uses GUI clock)

66 MHz 100 MHz 100 MHz 66 MHz 33 MHz Pseudo-synchronous (DRAM uses GUI clock) 66 MHz 66 MHz 66 MHz 66 MHz 33 MHz Synchronous (DRAM uses CPU clock)

and Pentium IIITM processors

Revision 1.86, April 22, 2005 -1- Product Features

Apollo PLE133 Data Sheet

• Internal Accelerated Graphics Port (AGP) Controller

− AGP v1.0 compliant

− Pipelined split-transaction long-burst transfers up to 533 MB/sec

− Eight level read request queue

− Four level posted-write request queue

− Thirty-two level (quadwords) read data FIFO (128 bytes)

− Sixteen level (quadwords) write data FIFO (64 bytes)

− Intelligent request reordering for maximum AGP bus utilization

− Supports Flush/Fence commands

− Graphics Address Relocation Table (GART)

− One level TLB structure

− Sixteen entry fully associative page table

− LRU replacement scheme

− Independent GART lookup control for host / AGP / PCI master accesses

− Windows 95 OSR-2 VXD and integrated Windows 98 / NT5 miniport driver support

• Concurrent PCI Bus Controller

− PCI bus is synchronous / pseudo-synchronous to host CPU bus

− 33 MHz operation on the primary PCI bus

− Supports up to five PCI masters

− Peer concurrency

− Concurrent multiple PCI master transactions; i.e., allow PCI masters from both PCI buses active at the same time

− Zero wait state PCI master and slave burst transfer rate

− PCI to system memory data streaming up to 132Mbyte/sec

− PCI master snoop ahead and snoop filtering

− Six levels (double-words) of CPU to PCI posted write buffers

− Byte merging in the write buffers to reduce the number of PCI cycles and to create further PCI bursting possibilities

− Enhanced PCI command optimization (MRL, MRM, MWI, etc.)

− Forty-eight levels (double-words) of post write buffers from PCI masters to DRAM

− Sixteen levels (double-words) of prefetch buffers from DRAM for access by PCI masters

− Supports L1/L2 write-back forward to PCI master read to minimize PCI read latency

− Supports L1/L2 write-back merged with PCI master post-write to minimize DRAM utilization

− Delay transaction from PCI master reading DRAM

− Read caching for PCI master reading DRAM

− Transaction timer for fair arbitration between PCI masters (granularity of two PCI clocks)

− Symmetric arbitration between Host/PCI bus for optimized system performance

− Complete steerable PCI interrupts

− PCI-2.2 compliant, 32 bit 3.3V PCI interface with 5V tolerant inputs

Revision 1.86, April 22, 2005 -2- Product Features

Apollo PLE133 Data Sheet

• Advanced High-Performance DRAM Controller

− DRAM interface synchronous or pseudosynchronous with CPU FSB speed of 133 / 100 / 66 MHz

− DRAM interface may be faster than CPU by 33 MHz to allow use of PC100 with 66 MHz Celeron CPU or use of

PC133 with 100 MHz VIA C3 or Intel Pentium II or Pentium III CPU

− DRAM interface may be slower than CPU by 33 MHz to allow use of older memory modules with a newer CPU

− Concurrent CPU, AGP, and PCI access

− Different DRAM timing for each bank

− Dynamic Clock Enable (CKE) control for SDRAM power reduction in high speed systems

− Mixed 1M / 2M / 4M / 8M / 16M / 32MxN DRAMs

− 6 banks DRAMs supported up to 1.5GB (256Mb DRAM technology)

− Flexible row and column addresses

− 64-bit data width only

− 3.3V DRAM interface with 5V-tolerant inputs

− Programmable I/O drive capability for MA, command, and MD signals

− Two-bank interleaving for 16Mbit SDRAM support

− Two-bank and four bank interleaving for 64Mbit SDRAM support

− Supports maximum 8-bank interleave (i.e., 8 pages open simultaneously); banks are allocated based on LRU

− Independent SDRAM control for each bank

− Seamless DRAM command scheduling for maximum DRAM bus utilization

(e.g., precharge other banks while accessing the current bank)

− Four cache lines (16 quadwords) of CPU to DRAM write buffers

− Four cache lines of CPU to DRAM read prefetch buffers

− Read around write capability for non-stalled CPU read

− Speculative DRAM read before snoop result

− Burst read and write operation

− x-1-1-1-1-1-1-1 back-to-back accesses for SDRAM from CPU or from DRAM controller

− BIOS shadow at 16KB increment

− Decoupled and burst DRAM refresh with staggered RAS timing

− CAS before RAS or self refresh

Revision 1.86, April 22, 2005 -3- Product Features

Apollo PLE133 Data Sheet

• General Graphic Capabilities

− 64-bit Single Cycle 2D/3D Graphics Engine

− Supports 2 to 8 Mbytes of Frame Buffer

− Real Time DVD MPEG-2 and AC-3 Playback

− Video Processor

− I

C Serial Interface

− Integrated 24-bit 230MHz True Color DAC

− Extended Screen Resolutions up to 1600x1200

− Extended Text Modes 80 or 132 columns by 25/30/43/60 rows

− DirectX 6 and OpenGL ICD API

• Graphics Performance

− Sustained 1M polygons/second and 100M pixels/second

− 30fps DVD playback of 9.8Mbps MPEG-2 video with 30% headroom

− Host Based AC-3 decode at only 8% utilization

• High Performance rCADE3D™ Accelerator

− 32 entry command queue, 32 entry data queue

− 4Kbyte texture cache with over 90% hit rates

− Pipelined Single Cycle Setup/Texturing/Rendering Engines

− DirectDraw™ acceleration

− Multiple buffering and page flipping

Setup Engine

− 32-bit IEEE floating point input data

− Slope and vertex calculations

− Back facing triangle culling

− 1/16 sub-pixel positioning

Rendering Engine

− High performance single pass execution

− Diffused and specula lighting

− Gouraud and flat shading

− Anti-aliasing including edge, scene, and super-sampling

− OpenGL compliant blending for fog and depth-cueing

− 16-bit Z-buffer

− 8/16/32 bit per pixel color formats

Texturing Engine

− 1/2/4/8-bits per pixel compact palletized textures

− 16/32-bits per pixel quality non-palletized textures

− Pallet formats in ARGB 565, 1555, or 444

− Tri-linear, bi-linear, and point-sampled filtering

− Mip-mapping with multiple Level-Of-Detail (LOD) calculations and perspective correction

− Color keying for translucency

2D GUI Engine

− 8/15/16/24/32-bits per pixel color formats

− 256 Raster Operations (ROPs)

− Accelerated drawing: BitBLTs, lines, polygons, fills, patterns, clipping, bit masking

− Panning, scrolling, clipping, color expansion, sprites

− 32x32 and 64x64 Hardware Cursor

− DOS graphics and text modes

Revision 1.86, April 22, 2005 -4- Product Features

Apollo PLE133 Data Sheet

• DVD

− Hardware-Assisted MPEG-2 Architecture for DVD with AC-3

− Simultaneous motion compensation and front-end processing (parsing, decryption and decode)

− Supports full DVD 1.0, VCD 2.0 and CD-Karaoke

− Microsoft DirectShow 3.0 native support, backward compatible to MCI

− No additional frame buffer requirements

− Sub-picture hardware eliminates Run-Length-Decoder and Alpha Blending overhead

− Dynamic frame and field de-interlace filtering for high quality playback on VGA monitors (Bob and Weave)

− Tamper-proof software CSS implementation

− Freeze, Fast-Forward, Slow Motion, Reverse

− Pan-and-Scan support for 16:9 sequence

• Video Processor

− On-chip Color Space Converter (CSC)

− Anti-tearing via two frame buffer based capture surfaces

− Minifier for video stream compression and filtering

− Horizontal/vertical interpolation with edge recovery

− Dual frame buffer apertures for independent memory access for graphics and video

− YUV 4:2:2/4:1:1/4:2:0 and RGB formats

− Video Module Interface (VMI) to MPEG and video decoder

− Vertical Blank Interval for Intercast™

− Overlay differing video and graphic color depths

− Minifier Video Module Interface (VMI) to MPEG and video decode

− Display two simultaneous video streams from both internal AGP and VMI

− Two scalers and Color Space Converters (CSC) for independent windows

• Digital Flat Panel (DFP) Interface

− 85 MHz Flat Panel Monitor interface supports 1024x768 panels

− Uses external TMDS transmitters for advanced panel interfaces

• Power Management Support

− Dynamic power down of SDRAM (CKE)

− Independent clock stop controls for CPU / SDRAM, AGP, and PCI bus

− PCI and AGP bus clock run and clock generator control

− VTT suspend power plane preserves memory data

− Suspend-to-DRAM and Self-Refresh operation

− EDO self-refresh and SDRAM self-refresh power down

− 8 bytes of BIOS scratch registers

− Low-leakage I/O pads

• Testability

− Build-in NAND-tree pin scan test capability

Revision 1.86, April 22, 2005 -5- Product Features

Apollo PLE133 Data Sheet

SYSTEM OVERVIEW

The Apollo PLE133 chipset consists of the VT8601A North Bridg e (described by this document) and the VT82C686B South Bridge (described in a separate data sheet). The VT8601A is a PC system logic North Bridge for Socket-370 CPUs with

integrated 2D/3D Graphics accelerator. The core logic portion of the chip is based on the VIA Apollo Pro133 with integrated graphics accelerator provided by an industry leading Graphics supplier. The combination of the two leading edge technologies provides a stable, cost-effective, and high performance solution to both the Desktop and Mobile personal computer markets. As shown in Figure 1 below, the Apollo PLE133 will interface to:

• Socket-370 Front-Side Bus (133, 100 and 66 MHz)

• PC133 / PC100 SDRAM Memory Interface

• PCI Bus (33 MHz)

• Analog RGB Monitor with DDC

• Digital Monitor Transmitters (TMDS)

• Video Capture / Playback CODECs

TV Signal

TV Encoder

PCI SLOTS

Dual-IDE

TMDS

VMI

4x USB

VIA C3 or Intel

Celeron /

Pentium III

Processor

VT8601A

North Bridge

510 BGA

PCI BUS

VT82C686B

South

Bridge

352 BGA

SMBUS

AC-Link

ISA Bus

Floppy Disk

CNTLs

MD[63:0]

MA[13:0]

AC-97

BIOS ROM

D R A M

ISA SLOTS

Serial Ports

Parallel Port

Figure 1: Apollo PLE133 High Level System Diagram

Revision 1.86, April 22, 2005 -6- System Overview

Apollo PLE133 Data Sheet

Apollo PLE133 Core Logic Overview

The Apollo PLE133 chipset is a high performance, cost-effective and energy efficient solution for the implementation of Integrated 2D / 3D Graphics - PCI - ISA desktop and notebook personal computer systems from 66 MHz to 133 MHz based on 64bit Socket-370 VIA C3 / Intel Celeron and Pentium III processors. The complete solution consists of the VT8601A “System Media Accelerator” (SMA) north bridge (510 BGA) and either the VT82C596B (324 BGA) or the VT82C686B (352 BGA) PCIto-ISA south bridge. Both south bridges are PC98 / PC99 compliant with integrated UltraDMA-66 / 33 IDE, 4 USB ports, and a complete power management feature set. The VT82C686B also integrates HW monitoring, Super-I/O functions (floppy disk drive interface and serial / parallel ports), and AC-97 link supporting digital audio and HSP modem functions.

Apollo PLE133 supports six banks of DRAMs up to 1.5GB. The DRAM controller supports PC133 and PC100 Synchronous DRAM (SDRAM). The Synchronous DRAM interface allows zero wait state bursting between the DRAM and the data buffers at 100 or 133 MHz. The six banks of DRAM can be composed of an arbitrary mixture of 1M / 2M / 4M / 8M / 16M / 32MxN DRAMs. The DRAM Controller is optimized to run synchronous with the CPU Front Side Bus (FSB) frequency of 100 or 133 MHz or pseudosynchronous to the Front Side Bus with the SDRAM and FSB frequencies differing by 33 MHz.

Apollo PLE133 also supports full AGP v1.0 capability with the internal 2D/3D Graphics Engine for maximum software compatibility. An eight level request queue plus a four level post-write request queue with thirty-two and sixteen quadwords of read and write data FIFO’s respectively are included for deep pipelined and split AGP transactio ns. A single-level GART TLB with 16 full associative entries and flexible CPU/AGP/PCI remapping control is also provided for operation under protected mode operating environments. Both Windows-95 VXD and Windows-98 / NT5 miniport drivers are supported.

Apollo PLE133 supports one 32-bit 3.3 / 5V system bus (PCI) that is synchronous to the CPU bus. The chip also contains a builtin AGP bus-to-PCI bus bridge to allow simultaneous con current operations on each bus. Five levels (doublewords) of post write buffers are included to allow for concurrent CPU and PCI operation. For PCI master operation, forty-eight levels (doublewords) of post write buffers and sixteen levels (doublewords) of prefetch buffers are included for concurrent PCI bus and DRAM/cache accesses. The chip also supports enhanced PCI bus commands such as Memory-Read-Line, Memory-Read-Multiple and MemoryWrite-Invalid commands to minimize snoop overhead. In addition, advanced features are supported such as snoop ahead, snoop filtering, L1 / L2 write-back forward to PCI master, and L1 / L2 write-back merged with PCI post write buffers to minimize PCI master read latency and DRAM utilization. Delay transaction and read caching mechanisms are also implemented for further improvement of overall system performance.

For sophisticated notebook implementations, the Apollo PLE133 north bridge provides independent clock stop control for the CPU / SDRAM, PCI, and AGP buses and Dynamic CKE control for powering down of the SDRAM. A separate suspend-well plane is implemented for the SDRAM control signals for Suspend -to-DRAM operation. Coupled with the 324-pin Ball Grid Array VIA VT82C596B south bridge chip, a complete notebook PC main board can be implemented with no external TTLs.

Revision 1.86, April 22, 2005 -7- System Overview

Apollo PLE133 Data Sheet

Apollo PLE133 Graphics Controller Overview

The Apollo PLE133 Graphics Controller is a highly integrated display control device that incorporates a 64-bit 3D/2D graphic engine and video accelerator with advanced DVD video and optional TV output capability. It provides a flexible and high performance solution for graphics and video playback acceleration for various color depth and resolution modes.

The Apollo PLE133 Graphics Controller supports a video capture port to import captured live MPEG 1 or MPEG 2 video streams, or DVD decompressed video streams to be overlaid with a graphics stream of mixed color depth displays. In supporting dual live videos, the Apollo PLE133 Graphics Controller offers independent dual video windows ready for videoconferencing and with linear scaling capability.

Integrating the programmable phase lock loop with high speed LUT DACs, the Apollo PLE133 Graphics Controller is a true price/performance solution for the modern multimedia based entertainment PC.

Capability Overview

The Apollo PLE133 Graphics Controller is a fully integrated CRT and TV 64-bit 2D/3D Accelerator. The high performance graphics engine offers high speed 3D image processing in full compliance and compatibility with IBM® VGA and VESA™ extended VGA. As an integrated controller, it allows unprecedented cost and performance advantages by eliminating the need for an external frame buffer while at the same time gaining local access to a larger amount of memory. Many functions can now be eliminated that previously consumed large amounts of bandwidth.

The Apollo PLE133 Graphics Controller, equipped with a single-cycle 3D GUI Engine, pipelines 3D rendering process architecture in hardware, providing real-time interactions with solid 3D models in CAD/CAM, 3D modeling, and 3D games. It supports all key 3D rendering operations, including: Gouraud shading for smooth object surfaces, texture mapping for realistic object textures, 16-bit hardware Z-buffering for fast 3D depth calculations, and Alpha Blending for transparency effects.

The Apollo PLE133 Graphics Controller’s highly innovative design, a full 64-bit memory interface with a high performance graphics engine which can support a RAMDAC™ running up to 230MHz, dramatically improves GUI functions and significantly promotes overall system operation.

The Apollo PLE133 Graphics Controller supports a full AGP implementation internally to remain compatible with existing software and programming models. However, since the engine is integrated it enjoys a higher bandwidth and lower latency than is possible with discrete solutions. AGP operations can include direct access of the system memory by the 2D/3D engine to provide increased texture memory.

To meet the requirements of a PC99 graphics adapter in a multimedia PC, the Apollo PLE133 Graphics Controller supports planar video format for MPEG-1, MPEG-2, and DVD-video playback. The dual video playback is capable of overlaying windows for videoconferencing and multimedia displays. Advanced features of the Apollo PLE133 Graphics Controller, su ch as color space conversion, video scaling, dual video windows, dual-view display, V ideo Module Interface (VMI), Vertical Blanking Interleave (VBI), a 24-bit True Color DAC, and triple clock synthesizers allow performance at peak levels.

By using an extended 16-bit VMI port the Apollo PLE133 Graphics Controller can support DTV resolution . This port can op erate as either an input for Video Capture or as an output for Video display. The Apollo PLE133 Graphics Controller is capable of supporting three simultaneous displays: CRT, Flat Panel Monitor & Video, each with a different “window” or desktop.

The Apollo PLE133 integrated Graphics Controller supports a rich featured flat panel monitor interface that can be used with external TMDS transmitters to support the latest DVI displays.

Revision 1.86, April 22, 2005 -8- System Overview

Apollo PLE133 Data Sheet

System Capabilities

The Apollo PLE133 Graphics Controller’s main system features include:

• High Performance single cycle GUI

• Highly Integrated RAMDAC™ and Triple Clock Synthesizer

• Full Feature High Performance 3D Graphics Engine

• High speed internal AGP Bus Mastering data bus supporting DVD video playback & 3D

• Hardware implementation of motion compensation

• Dual Video Windows for Videoconferencing

• TrueVideo

• DirectDraw

• Versatile Motion Video Capture/Overlay/Playback Support

• Flexible Frame Buffer Memory Interface

• Advanced Mobile Power Management

• CRT Power Management (VESA™ DPMS)

• PC99 Hardware Support



Processor

and DirectVideoTM Hardware Support

High Performance 64-bit 2D GUI

The 64-bit graphics engine of the Apollo PLE133 Graphics Controller significantly improves graphics performance through specialized hardware that accelerates the most frequently used GUI operations and matches the high-speed requirements of CPUs. Functions directly supported in hardware include: BitBLTs, image and text transfer, line draw, short stroke vector draw, rectangle fills, and clipping. The graphics engine supports 256 Raster Operations (ROPs) for up to 32-bit pack ed pix el graph ic modes. The ROP3 Processor in the Apollo PLE133 Graphics Controller is able to perform Boolean functions which allow many additional operations, including transparency, pattern masking, color expansion alignment, and pattern enhancement. Additionally, the graphics engine features linear display memory addressing (up to 4GB memory space), accelerated color expansion modes for graphics text procession, and memory-mapped I/O registers on the graphics engine for faster access time.

Graphic functions are optimized by a 64-bit internal data bus and a four-color hardware cursor/pop-up icon, operating up to a 128x128x2 pixel image, which offloads the CPU. The hardware cursor mechanism can also be used to display patterns stored in the system memory. This pop-up icon is very useful to display user friendly information instantly through simple hot key operations. This advanced function combination allows significant performance increases over standard Super VGA designs and provides outstanding graphics acceleration on GUIs, such as Microsoft

Highly Integrated RAMDAC

& Clock Synthesizer



Windows 98.

The highly integrated design of the Apollo PLE133 Graphics Controller offers a “no TTL” solution for cost-effective, highperformance multimedia subsystem designs for the PC and compatible notebooks. The 64-bit memory data bus supporting SDRAM and SGRAM memory provides faster data transfer rates for improved system throughput. The Apollo PLE133 Graphics Controller has a built-in, high speed RAMDAC

. The RAMDACTM is composed of one 256x24 and one 256x18 color lookup table and a triple loop frequency synthesizer, providing the read/write timing control for the Frame Buffer Memory and the refresh of the TV/CRT display.

The integrated frequency synthesizer provides a 125MHz memory clock for high speed DRAM access and a 230MHz video clock which supports various refresh rates up to 85Hz at 1280x1024.

Full Feature High Performance 3D Engine

The Apollo PLE133 Graphics Controller is equipped with an advanced Graphics Drawing, Single Cycle 3D Graphics Engine that performs premium 3D functions at a high level of more than 1M triangles per second. The 3D engine supports Microsoft



Direct3D. The 3D Engine is set up to off-load the CPU from major 3D tasks including slope calculation, sub-pixel positioning, and Tri-striping. By balancing the 3D pipeline and reducing parameter passing, the Apollo PLE133 Graphics Controller provides very high levels of performance. The 3D engine is integrated with a triangle set-up engine that sets up triangles according to vertex input data and accomplishes various functions for 3D rendering. Gouraud shading provides smooth shading for colors across surfaces, perspective correction texture mapping to correct texture data based on the perspective, bi-linear texture filtering for interpolating, alpha blending to compensate colors for the opacity of two colors blended, Z-buffering (16-bit/24-bit), video texturing to overlay 2D video play-back onto 3D images, fogging to simulate weather effects, palletized texture mapping (1-, 4-, or 8-bit) for memory and bandwidth reduction, and anti-aliasing to reduce or eliminate jaggies resulted from alias rendering. The 3D engine also works with the APM system, conserving power while 3D operations are suspended.

Revision 1.86, April 22, 2005 -9- System Overview

Apollo PLE133 Data Sheet

Video Processor

Video processor features include: on-chip hardware Color Space Conversion (CSC) for faster data conversion on the fly, Horizontal/Vertical (H/V) scaling with interpolation, edge recovery algorithm logic, gamma correction, and overlay control with different color depths from graphics. The Apollo PLE133 Graphics Controller also includes a fully integrated GUI accelerator, read cache, and command FIFO that optimize memory bandwidth and maximize graphics performance.

The Apollo PLE133 Graphics Controller, with an integrated Video Display and a Capture Engine, supports dual apertures on the PCI bus which enables independent graphic and video data to be transported simultaneously to and from different memory areas and greatly accelerates the performance of both DirectDraw provide dual video windows that display different images from different video sources (from the PCI bus and from the capture port) on the same screen. The video image is stored in off-screen memory and is retrieved by the Video Display Processing block for video processing. With the help of DirectDraw™ acceleration for sprites, page flipping, double buffering, and color keying, video processing is performed by utilizing a proprietary edge recovery algorithm for sharper line visibility , de-interlacing, antitearing, multitap horizontal filtering, dithering, and scaling operations with b ilinear interpolation in both horizontal and vertical directions. Linear scaling permits zoom in/out to any size without any restrictions. In addition, the on-chip hardware Color Space Conversion (CSC) accelerates conversion for 16 bit YUV pixels into linear true color 32 bit RGB pixels on the fly. The additional X and Y minifiers are capable of shrinking video images to any linear fractions, which saves bus bandwidth and memory space. The YUV planar logic of the Apollo PLE133 Graphics Controller supports a YUV 420 format that can eliminate redundant video stream decoding procedures. The load of the CPU is reduced while performing software MPEG or software video conferencing. The color and luminance control provided by the Apollo PLE133 Graphics Controller offers color compensations to prevent color distortion for display devices such as a CRT or TV with Gamma correction and hue adjustment control.

The Video Conferencing feature allows remote and local video images to be displayed simultaneously on the same screen.

and DirectVideoTM. The Apollo PLE133 Graphics Controller can

Video Capture and DVD

The Apollo PLE133 Graphics Controller has a Video Module Interface (VMI) and advanced hardware interface logic allowing it to be directly connected to many MPEG and video decoders such as the C-Cube CL450 /480, SGS 3400/3500, Philips 7110/1 and Brooktree BT819/817/827/829.

The Apollo PLE133 Graphics Controller, integrated with a DVD video hardware block for motion compensation, gives existing PCs the ability to play DVD video in MPEG-2 format at high bandwidths with very good video quality.

A new industry standard is being set for transmission of non-video data over a TV broadcast signal during vertical blanking dead time. This technology is referred to as Intercast. The Apollo PLE133 Graphics Controller has the ab ility to take the entire video stream over the video port, sending the visible video stream to the display memory for display in a window, stripping the VBI data from the stream, and then sending this data to the CPU for processing using PCI Bus Mastering.

Versatile Frame Buffer Interface

The Apollo PLE133 Graphics Controller features a versatile frame buffer interface aperture into main system memory. Optimized performance can be achieved with the single cycle memory bus interface using programmable DRAM timing. The display queue has been increased to reduce the frequency of memory bus requests, optimizing memory bus efficiency for the graphic controller.

With the support of the internal AGP aperture, the Apollo PLE133 Graphics Controller has access to system memory through the GART. In the execute mode, the Apollo PLE133 Graphics Controller is able to use both the dedicated graphics portion and the general portion of system memory for graphics operations. As a result, DVD and 3D rendering performance and quality are greatly enhanced.

Hi-Res and Hi-Ref Display Support

Apollo PLE133 Graphics Controller display enhancements dramatically improve CRT resolution. These enhancements include support of non-interlaced 1280x1024x64K, 1024x768x16M, 800x600x16M, and 640x480x16M colors for “full spectrum” color. Extended text modes of 80 or 132 columns by 25, 30, 43, or 60 rows provid e an extended graphics area frequently used in many spreadsheet and database applications. Extended graphics and text modes are supported by software drivers that provide a “readyto-go” solution, minimizing the need for additional driver development.

A virtual screen can be created with the Apollo PLE133 Graphics Controller . When this function is enabled, a selected portion of a large image can be shown on a smaller display. The image can also be moved across the whole screen, either up or down.

The Apollo PLE133 Graphics Controller is able to automatically detect DDC monitors with I

C signaling.

Revision 1.86, April 22, 2005 -10- System Overview

Apollo PLE133 Data Sheet

CRT Power Management (VESA DPMS)

The Apollo PLE133 Graphics Controller conforms to the standard power management schemes defined by VESA™ for CRTs. The Apollo PLE133 Graphics Controller supports four states of VESA™ Display Power Management Signaling (DPMS), which decrease monitor power consumption after timeout periods. VESA™ DPMS power down states (ready, standby, suspend, and off) specify HSYNC and VSYNC signals to control the monitor power down state.

Flat Panel Monitor Interface

The Apollo PLE133 Flat Panel Monitor interface is designed to support industry standard TFT panel based Flat Panel Monitors via external TMDS transmitters. The interface supports both 18-bit and 24-bit display modes. Optionally, an 18 +18 panel can be supported utilizing external latches.

PD[23] B0 S2 S2 used for external 18+18 PD[22] B1 S1 S1 used for external 18+18 PD[21] G0 PD[20] G1 PD[19] R0 PD[18] R1 PD[17] B2 B0 PD[16] B3 B1 PD[15] G2 G0 PD[14] G3 G1 PD[13] R2 R0 PD[12] R3 R1 PD[11] B4 B2 PD[10] B5 B3

PD[9] B6 B4 PD[8] B7 B5 PD[7] G4 G2 PD[6] G5 G3 PD[5] G6 G4 PD[4] G7 G5 PD[3] R4 R2 PD[2] R5 R3 PD[1] R6 R4 PD[0] R7 R5

24 Bit

TFT

18 Bit

TFT Notes

Video Capture Interface

The Video Module Interface (VMI) is supported for video devices such as MPEG1 and MPEG2. Additionally, the zero-wait state host write buffer, read cache, and memory mapped I/O increase operating speeds and contribute to peak performance levels. All I/O interfaces are 5V tolerant, capable of interfacing with external devices operating at 5V, even though the Apollo PLE133 Graphics Controller runs at 2.5V. Graphics system throughput is further enhanced by a command FIFO, allowing maximum bus transfer speed for applications such as Windows™ or AutoCAD™ that directly access video memory.

Complete Hardware Compatibility

The Apollo PLE133 Graphics Controller is fully compliant with the VESA™ DDC and VAFC standards. Th e Apollo PLE133 Graphics Controller is 100% VGA compatible at both the BIOS and Driver level, allowing full compatib ility with virtually any VGA application software. The Apollo PLE133 Graphics Controller provides hardware support to DirectDraw™, offering high speed game graphics on Windows 98 supporting a unique ID for each customer and a unique ID for each model.

Revision 1.86, April 22, 2005 -11- System Overview



. The Apollo PLE133 Graphics Controller meets the requirements of PC99 as well,

Apollo PLE133 Data Sheet

6 7 8

910

516

81920

526

PINOUTS

Figure 1. VT8601A Ball Diagram (Top View)

1 2 3 4 5

GND

RGB

GND

VCC

VSYNC HSYNC IRSET COMP HD56 HD58 HD46 HD40 HD27 HD39 VTT

EVDD SDA SCL ETST# SUSP GND VCC3 HD52 VCCI VCC3 VCC3 GND GND GND VCC3 VCCI VTT VCC3 GND HA15

EBLT PD0 FLM SCLK LP VCC3 G7 8 9 10 11 12 13 14 15 16 17 18 19 G20 VCC3 HCLK

PD12 PD10 PD13 PD20 PD16 PD6 K

PD17 PD15 PD18 VCC3 PD9 PD14 L

PD23 IMIO IMIIN PD21 PD22 PD19 M

NC NC NC NC HD62 HD57 HD63 GND HD45 HD38 HD34 HD31 HD16 HD13 HD3 HD12 GND

GND NC NC NC HD50 HD59 HD48 HD51 HD44 HD22 HD32 HD33 HD19 HD24 HD2 HD10 HD1 HA26 HA29 HA23 HA25 HA21 HA13 HA5 HA6

RED NC NC NC HD60 HD55 GND HD41 HD49 HD43 HD28 HD26 GND HD20 HD9 HD5 HD4 GND HA27 HA31 HA19 HA16 HA9 HA11 HA8

BLUE GRN GND HD61 HD53 HD54 HD47 HD42 HD37 HD36 HD29 HD25 HD23 HD7 HD11 HD8 HD6 HD15 HA30 HA17 HA12 GND HA4 HA14 BNR#

PD2 PD1 DE PD5 EVEE VCC3 H

PD4 PD3 PD8 PD7 PD11 VCCI J

CRT CPU Pins

Pins

Panel

Pins

11 12 1

GTL REF

K10 11 12

L GND VCC3

M VCC3 GND

14 1

HD35 HD21 HD30 HD14 HD18 HD17 HD0 HA24

13 14 15 16 K17

GND GND VCC3 GND L

GND GND GND VCC3 M

171

CPU

HA18 HA20 HA22 HA10 HA28 HA3 GND

RST#

H VCCA VCCA RS0# GND RS2# DBSY#

J VCCI

K VCC3

L GNDA GNDA MD33 MD35 MD3 MD2

M GND MD34 MD0 MD5 MD36 MD4

21 22 2

GTL

CPU

REF

RSTD#

MCLK

24 2

HREQ

HA7

HREQ

LOCK#

DRDY# ADS#

RS1# PLLTST MD1 MD32

HREQ

HIT#

HREQ

TRDY#

BREQ

BPRI#

DE-

FER#

HITM#

GND

VD14 VD13 GND VD15 VD12 GND N

GND VD9 VD10 VD11 VD8 GND P

VD6 VD4 VD7 VD5 VD3 VD0 R

VD2 VD1 VHS VCC3 TVD4 TVD6 T

VVS TVD7 VCLK TVD5 TVD2 VCC5 U

TVD0 TVD1 TVD3 TVCK TVHS VCCI V

VCC D VCC

GND

NC NC NC NC

REQ

GNT

GND

TVVS XTLO INTA# VCC3 W

VCC

VLF1 XTLI NC VCC3 Y7 8 9 10 11 12 13 14 15 16 17 18 19 Y20 VCC3 CS4# CS3# CS2# CS1# CS0#

VLF2 NC NC NC GND VCC3 AD16 VCCI VCC3 GND GND GND VCC3 VCCI MD58 VCC3 GND VSUS2 MA0

GNT

REQ

GNT

REQ

GNT

REQ

GND

REQ

GNT

REQ

LOCK# AD27 AD20 AD19 FRM# STOP# AD13 AD8 AD2 AD1

AD31 AD26 AD22 AD18 GND SERR# AD12 CBE0# AD3 AD0

Video

Pins

TVout Pins

Pins PCI Pins

AD30 AD25 AD21

AD29 AD24 AD23 AD17 IRDY# AD15 AD11 AD6 AD4 PREQ# MD31 MD60 MD25 MD23 MD52 MD49 SUST# GND MA7 MA6 MA5

AD28 CBE3# GND CBE2# TRDY# AD14 AD9 GND

DEV

SEL#

N GND GND GND GND GND GND N

P GND GND GND GND GND GND P

R VCC3 GND GND GND GND VCC3 R

T GND VCC3 GND GND VCC3 GND T

U10 11 12 13 14 15 16 U17

PAR CBE1# AD10 AD7 AD5 PCLK MD63 MD29 MD56 MD54 MD20 MD18 VSUS3 MA1 MA4 MA3 MA2

PWR

PGNT# MD61 MD27 MD57 GND MD21 MD50 MD16

PCI

MD30 MD59 MD26 MD55 MD22 MD19 MD48

RST#

PCK

MD62 MD28 GND MD24 MD53 MD51 MD17

RUN#

Mem

N GND MD39 MD37 MD7 MD38 MD6

P GND MD12 MD8 MD41 MD9 MD40

R MD44 MD10 MD43 MD11 MD42

T GND MD15 MD13 MD46 MD14 MD45

U VCC3

V VCCI VSUS3

W CS5# VSUS3

SCAS

MD47 SWEA#

DQM

DQM 7 DQM 2 MA14

SWEB#

SWEC#

CKE2

CKE0

SCASC#

SCASB#

CKE1

GND

SRASB#

SRAS

MA11 MA9 MA8

MA12

GND

CKE3

DQM 5 DQM

SRASC#

CKE5

CKE4

MA13

MA10

BA0

GND

BA1

Revision 1.86, April 22, 2005 -12- Pin Diagram

Apollo PLE133 Data Sheet

Figure 2. VT8601A Pin List (Numerical Order)

Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin # Pin Names Pin # Pin Name

A03 IO NC A04 IO NC D05 IO HD61 G22 I HCL A05 IO NC D06 IO HD53 G23 I HLOCK# P04 IO VD11 Y26 O CS0# AD04 I REQ3# A06 IO HD62 D07 IO HD54 G24 IO HIT# P05 IO VD08 A07 IO HD57 D08 IO HD47 G25 IO HTRDY# A08 IO HD63 D09 IO HD42 G26 I HITM#

A09 P GND

A10 IO HD45 D11 IO HD36 H02 O PD01 P23 IO MD08 AA05 IO NC AD09 IO CBE2# A11 IO HD38 D12 IO HD29 H03 O DE P24 IO MD41 A12 IO HD34 D13 IO HD25 H04 O PD05 P25 IO MD09 A13 IO HD31 D14 IO HD23 H05 O EVEE / P26 IO MD40 AA08 IO AD16 AD12 IO AD09 A14 IO HD16 D15 IO HD07 A15 IO HD13 D16 IO HD11 A16 IO HD03 D17 IO HD08 A17 IO HD12 D18 IO HD06 H23 IO RS0# R04 IO VD05

A18 P GND

A19 O CPURST# D20 IO HA30 H25 IO RS2# R06 IO VD00 A20 IO HA18 D21 IO HA17 H26 IO DBSY# R22 IO MD44 A21 IO HA20 D22 IO HA12 J01 O PD04 R23 IO MD10 AA19 IO MD58 AD20 IO MD21 A22 IO HA22 A23 IO HA10 D24 IO HA04 J03 O PD08 R25 IO MD11 A24 IO HA28 D25 IO HA14 J04 O PD07 R26 IO MD42 A25 IO HA03 D26 IO BNR# J05 O PD11 T01 IO VD02 AA23 O MA00 / strap AD24 O MA11 / stra

A26 P GND B01 P GNDS B02 P GND

B03 IO NC E04 A COMP J23 IO DRDY# T05 O TVD4 AB01 IO NC AE02 O GNT4# B04 IO NC E05 IO HD56 J24 IO ADS# T06 O TVD6 AB02 IO NC AE03 O GNT3# B05 IO NC E06 IO HD58 J25 O BREQ0# B06 IO HD50 E07 IO HD46 B07 IO HD59 E08 IO HD40 K01 O PD12 T23 IO MD13 AB05 O GNT0# AE06 IO AD27 B08 IO HD48 E09 IO HD27 K02 O PD10 T24 IO MD46 AB06 IO AD30 AE07 IO AD20 B09 IO HD51 E10 IO HD39 K03 O PD13 T25 IO MD14 AB07 IO AD25 AE08 IO AD19 B10 IO HD44 B11 IO HD22 B12 IO HD32 E13 IO HD35 K06 O PD06 U02 O TVD7 AB10 IO PAR AE11 IO AD13 B13 IO HD33 E14 IO HD21 B14 IO HD19 E15 IO HD30 K22 I MCLKI U04 O TVD5 AB12 IO AD10 AE13 IO AD02 B15 IO HD24 E16 IO HD14 K23 IO RS1# U05 O TVD2 AB13 IO AD07 AE14 IO AD01 B16 IO HD02 E17 IO HD18 K24 I PLLTST B17 IO HD10 E18 IO HD17 K25 IO MD01 B18 IO HD01 E19 IO HD00 K26 IO MD32 U22 O SCASA# AB16 IO MD63 AE17 IO MD59 B19 IO HA26 E20 IO HA24 L01 O PD17 U23 IO MD47 AB17 IO MD29 AE18 IO MD26 B20 IO HA29 B21 IO HA23 E22 O CPURSTD# L03 O PD18 U25 O SWEB#/ / CKE2 AB19 IO MD54 AE20 IO MD22 B22 IO HA25 E23 IO HA07 B23 IO HA21 E24 IO HREQ0# L05 O PD09 V01 O TVD0 AB21 IO MD18 AE22 IO MD48 B24 IO HA13 E25 IO HREQ4# L06 O PD14 V02 O TVD1 B25 IO HA05 E26 IO BPRI# B26 IO HA06 F01 O EVDD

C01 P VCCS

C02 A RED F03 IO SCL L24 IO MD35 C03 IO NC F04 I ETST# L25 IO MD03 C04 IO NC F05 I SUSP L26 IO MD02 C05 IO NC C06 IO HD60 C07 IO HD55 F08 IO HD52 M03 I IMIIN V25 O SCASB# / CKE3 AC05 I REQ0# AF06 IO AD26

C08 P GND F09 P VCCI

C09 IO HD41 C10 IO HD49 C11 IO HD43 C12 IO HD28 C13 IO HD26

C14 P GND F17 P VCC3

C15 IO HD20 C16 IO HD09 C17 IO HD05 C18 IO HD04

C19 P GND

C20 IO HA27 F23 IO HREQ1# N04 IO VD15 W26 O DQM4 AC18 IO MD25 AF19 IO MD24 C21 IO HA31 F24 IO HREQ2# N05 IO VD12 C22 IO HA19 F25 IO HREQ3# C23 IO HA16 F26 IO DEFER# C24 IO HA09 G01 O EBLT N22 IO MD39 Y04 I XLTI AC22 I SUST# AF23 O DQM7 C25 IO HA11 G02 O PD00 N23 IO MD37 Y05 IO NC C26 IO HA08 G03 O FLM N24 IO MD07

D01 P VCCR

Center GND Pins (28 pins): L11, L13-14, L16, M12-15, N11-16, P11-16, R12-15, T11, T13-14, T16 Center VCC3 Pins (8 pins): L12, L15, M11, M16, R11, R16, T12, T15

D04 P GND G21 P VCC3

D10 IO HD37 H01 O PD02 P22 IO MD12 AA04 IO NC

H06 P VCC3 H21 P VCCA H22 P VCCA

D19 IO HD15

D23 P GND

E01 O VSYNC E02 O HSYNC E03 A IRSET J22 O MCLKO

E11 P VTT E12 P GTLREF

E21 P GTLREF

F02 IO SDA L23 IO MD33 V05 O TVHS AB25 O MA03 AE26 O MA10 / stra

F06 P GND F07 P VCC3

F10 P VCC3 F12 P VCC3 F13 P GND M21 P GND F14 P GND F16 P GND

F18 P VCCI F19 P VTT F20 P VCC3 F21 P GND

F22 IO HA15

G04 O SCL

N25 IO MD38

H24 P GND

J02 O PD03 R24 IO MD43

J06 P VCCI J21 P VCCI

J26 P GND

K04 O PD20 T26 IO MD45 AB08 IO AD21 AE09 IO FRAME# K05 O PD16 U01 IO VVS AB09 IO DEVSEL# AE10 IO STOP#

K21 P VCC3

L02 O PD15 U24 O SWEA#/ AB18 IO MD56 AE19 IO MD55

L04 P VCC3

L21 P GNDA L22 P GNDA

M01 O PD23 V23 O DQM0 AC03 IO REQ6# AF04 O GNT1# M02 O IMIO V24 O SCASC# / CKE1

M04 O PD21 M05 O PD22 M06 O PD19

M22 IO MD34 W04 O XLTO AC10 IO IRDY# AF11 IO AD12 M23 IO MD00 W05 O INTA# AC11 IO AD15 AF12 IO CBE0# M24 IO MD05 M25 IO MD36 W21 O CS5# AC13 IO AD06 AF14 IO AD00 M26 IO MD04 N01 IO VD14 W23 O DQM1 AC15 I PREQ# AF16 IO MD62 N02 IO VD13

N03 P GND

N06 P GND Y02 P VCCV2 N21 P GND

P02 IO VD09 Y24 O CS2# AD02 IO GNT5# P03 IO VD10 Y25 O CS1# AD03 IO GNT6#

AA01 P GNDV2 P06 P GND P21 P GND

R01 IO VD06 R02 IO VD04 R03 IO VD07

R05 IO VD03

T02 IO VD01 AA24 O SRASA# AD25 O MA09 / stra T03 IO VHS AA25 O SRASB# / CKE5 AD26 O MA08 / stra

T04 P VCC3

T21 P GND

T22 IO MD15 AB04 IO NC AE05 IO LOCK#

U03 IO VCL

U06 P VCC5 U21 P VCC3

U26 O SWEC#/ / CKE0 AB20 IO MD20 AE21 IO MD19

V03 O TVD3 AB23 O MA01 / strap AE24 O MA12 / stra V04 O TVCL

V06 P VCCI V21 P VCCI V22 P VSUS3

V26 P GND

W01 P VCCD W02 P VCCV1

W03 O TVVS AC09 IO AD17 AF10 IO SERR#

W06 P VCC3

W22 P VSUS3

W24 P GND

W25 O D

Y01 P GNDV1

Y03 A VLF1 AC21 IO MD49 AF22 IO MD17

Y06 P VCC3 Y21 P VCC3

M5 AC17 IO MD60

AA02 A VLF2 AD06 IO AD28

AA03 IO NC AD07 IO CBE3#

AA06 P GND

AA07 P VCC3

AA09 P VCCI AD13 P GND

AA10 P VCC3

AA13 P GND

AA14 P GND

AA15 P GND

AA17 P VCC3

AA18 P VCCI AD19 P GND

AA20 P VCC3

AA21 P GND

AA22 P VSUS2

AA26 O SRASC# / CKE4 AE01 IO GNT7#

AB03 IO NC AE04 I REQ2#

AB11 IO CBE1# AE12 IO AD08

AB14 IO AD05 AE15 I RESET#

AB15 I PCLK AE16 IO MD30

AB22 P VSUS3

AB24 O MA04 AE25 O MA13 / stra

AB26 O MA02 / strap

AC01 IO NC AF02 I REQ4#

AC02 IO REQ5# AF03 O GNT2#

AC04 P GND

AC06 IO AD29 AF07 IO AD22

AC07 IO AD24 AF08 IO AD18

AC08 IO AD23

AC12 IO AD11 AF13 IO AD03

AC14 IO AD04 AF15 IO PCKRUN#

AC16 IO MD31 AF17 IO MD28

AC19 IO MD23 AF20 IO MD53

AC20 IO MD52 AF21 IO MD51

AC23 P GND

AC24 O MA07 / strap AF25 O MA14 / stra

AC25 O MA06

AD05 I REQ1#

AD08 P GND

AD10 IO TRDY# AD11 IO AD14

AD14 I PWRO AD15 O PGNT# AD16 IO MD61 AD17 IO MD27 AD18 IO MD57

AD21 IO MD50 AD22 IO MD16 AD23 O DQM6

AE23 O DQM3

AF01 P GND

AF05 IO AD31

AF09 P GND

AF18 P GND

AF24 O DQM2

AF26 P GND

Revision 1.86, April 22, 2005 -13- Pin Lists

Apollo PLE133 Data Sheet

Figure 3. VT8601A Pin List (Alphabetical Order)

Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin # Pin Names Pin # Pin Name

AE14 IO AD01 AE13 IO AD02

AF13 IO AD03 AC14 IO AD04 AB14 IO AD05 AC13 IO AD06 AB13 IO AD07 AE12 IO AD08 AD12 IO AD09 AB12 IO AD10 AC12 IO AD11

AF11 IO AD12 AE11 IO AD13 AD11 IO AD14 AC11 IO AD15 AA08 IO AD16 AC09 IO AD17

AF08 IO AD18 AE08 IO AD19 AE07 IO AD20 AB08 IO AD21

AF07 IO AD22 AC08 IO AD23 AC07 IO AD24 AB07 IO AD25

AF06 IO AD26 AE06 IO AD27 AD06 IO AD28 AC06 IO AD29 AB06 IO AD30

AF05 IO AD31

J24 IO ADS# D02 A BLUE D26 IO BNR# E26 IO BPRI#

J25 O BREQ0# AB05 O GNT0# A11 IO HD38 AE21 IO MD19 K01 O PD12

AF12 IO CBE0# AF04 O GNT1# E10 IO HD39 AB20 IO MD20 K03 O PD13 AB11 IO CBE1# AF03 O GNT2# E08 IO HD40 AD20 IO MD21 L06 O PD14 AD09 IO CBE2# AE03 O GNT3# C09 IO HD41 AE20 IO MD22 L02 O PD15 AD07 IO CBE3# AE02 O GNT4# D09 IO HD42 AC19 IO MD23 K05 O PD16

E04 A COMP AD02 O GNT5# C11 IO HD43 AF19 IO MD24 L01 O PD17 A19 O CPURST# AD03 O GNT6# B10 IO HD44 AC18 IO MD25 L03 O PD18 E22 O CPURSTD# AE01 O GNT7# A10 IO HD45 AE18 IO MD26 M06 O PD19 Y26 O CS0# D03 A GRN E07 IO HD46 AD17 IO MD27 K04 O PD20 Y25 O CS1# Y24 O CS2# Y23 O CS3# A25 IO HA03 C10 IO HD49 AE16 IO MD30 M01 O PD23 Y22 O CS4# D24 IO HA04 B06 IO HD50 AC16 IO MD31 AD15 O PGNT#

W21 O CS5# B25 IO HA05 B09 IO HD51 K26 IO MD32 K24 I PLLTST U03 IO VCL

H26 IO DBSY# B26 IO HA06 F08 IO HD52 L23 IO MD33 AC15 I PREQ# R06 IO VD00 H03 O DE E23 IO HA07 D06 IO HD53 M22 IO MD34 AD14 I PWRO F26 IO DEFER# C26 IO HA08 D07 IO HD54 L24 IO MD35 C02 A RED T01 IO VD02

AB09 IO DEVSEL# C24 IO HA09 C07 IO HD55 M25 IO MD36 AC05 I REQ0# R05 IO VD03

V23 O DQM0 A23 IO HA10 E05 IO HD56 N23 IO MD37 AD05 I REQ1# R02 IO VD04

W23 O DQM1 C25 IO HA11 A07 IO HD57 N25 IO MD38 AE04 I REQ2# R04 IO VD05

AF24 O DQM2 D22 IO HA12 E06 IO HD58 N22 IO MD39 AD04 I REQ3# R01 IO VD06 AE23 O DQM3 B24 IO HA13 B07 IO HD59 P26 IO MD40 AF02 I REQ4# R03 IO VD07

W26 O DQM4 D25 IO HA14 C06 IO HD60 P24 IO MD41 AC02 I REQ5# P05 IO VD08 W25 O DQM5 F22 IO HA15 D05 IO HD61 R26 IO MD42 AC03 I REQ6# P02 IO VD09

AD23 O DQM6 C23 IO HA16 A06 IO HD62 R24 IO MD43 AD01 I REQ7# P03 IO VD10

AF23 O DQM7 D21 IO HA17 A08 IO HD63 R22 IO MD44 AE15 I RESET# P04 IO VD11

J23 IO DRDY# A20 IO HA18 G24 IO HIT# T26 IO MD45 H23 IO RS0# N05 IO VD12 G01 O EBLT C22 IO HA19 G26 I HITM# T24 IO MD46 K23 IO RS1# N02 IO VD13 F04 I ETST# A21 IO HA20 G23 I HLOCK# U23 IO MD47 H25 IO RS2# N01 IO VD14 F01 O EVDD B23 IO HA21 E24 IO HREQ0# AE22 IO MD48 U22 O SCASA# N04 IO VD15 H05 O EVEE A22 IO HA22 F23 IO HREQ1# AC21 IO MD49 V25 O SCASB# / CKE3 T03 IO VHS G03 O FLM B21 IO HA23 F24 IO HREQ2# AD21 IO MD50 V24 O SCASC# / CKE1 Y03 A VLF1

AE09 IO FRAME# E20 IO HA24 F25 IO HREQ3# AF21 IO MD51 G04 O SCL

A09 P GND A18 P GND A26 P GND B02 P GND C08 P GND C14 P GND C19 P GND D04 P GND D23 P GND F06 P GND

Center GND Pins (28 pins): L11, L13-14, L16, M12-15, N11-16, P11-16, R12-15, T11, T13-14, T16 Center VCC3 Pins (8 pins): L12, L15, M11, M16, R11, R16, T12, T15

F14 P GND F16 P GND F21 P GND H24 P GND J26 P GND

M21 P GND

N03 P GND N06 P GND N21 P GND P01 P GND P06 P GND P21 P GND T21 P GND V26 P GND

W24 P GND AA06 P GND AA13 P GND AA14 P GND AA15 P GND AA21 P GND AC04 P GND AC23 P GND AD08 P GND AD13 P GND AD19 P GND AF01 P GND AF09 P GND AF18 P GND AF26 P GND

L21 P GNDA L22 P GNDA A01 P GNDRGB B01 P GNDS Y01 P GNDV1

AA01 P GNDV2

E12 P GTLREF E21 P GTLREF

B22 IO HA25 E25 IO HRE B19 IO HA26 E02 O HSYNC AF20 IO MD53 F02 IO SDA C20 IO HA27 G25 IO HTRDY# AB19 IO MD54 AF10 IO SERR# A24 IO HA28 M02 O IMIO AE19 IO MD55 AA24 O SRASA# B20 IO HA29 M03 I IMIIN AB18 IO MD56 AA25 O SRASB# / CKE5 E01 O VSYNC D20 IO HA30 W05 O INTA# AD18 IO MD57 AA26 O SRASC# / CKE4 C21 IO HA31 AC10 IO IRDY# AA19 IO MD58 AE10 IO STOP# G22 I HCL E19 IO HD00 AE05 IO LOCK# AC17 IO MD60 AC22 I SUST# Y04 I XLTI B18 IO HD01 G05 O LP AD16 IO MD61 U24 O SWEA# W04 O XLTO

A16 IO HD03 AB23 O MA01 / strapAB16 IO MD63 U26 O SWEC#/ / CKE0 C18 IO HD04 AB26 O MA02 / strapA02 - NC AD10 IO TRDY# C17 IO HD05 AB25 O MA03 A03 - NC V04 O TVCL D18 IO HD06 AB24 O MA04 A04 - NC V01 O TVD0 D15 IO HD07 AC26 O MA05 A05 - NC V02 O TVD1 D17 IO HD08 AC25 O MA06 B03 - NC U05 O TVD2 C16 IO HD09 AC24 O MA07 / strapB04 - NC V03 O TVD3 B17 IO HD10 AD26 O MA08 / strapB05 - NC T05 O TVD4 D16 IO HD11 AD25 O MA09 / strapC03 - NC U04 O TVD5 A17 IO HD12 AE26 O MA10 / strapC04 - NC T06 O TVD6 A15 IO HD13 AD24 O MA11 / strapC05 - NC U02 O TVD7

E16 IO HD14 AE24 O MA12 / strapY05 - NC V05 O TVHS D19 IO HD15 AE25 O MA13 / strapAA03 - NC W03 O TVVS A14 IO HD16 AF25 O MA14 / strapAA04 - NC

E18 IO HD17 K22 I MCLKI AA05 - NC

E17 IO HD18 J22 O MCLKO AB01 - NC B14 IO HD19 M23 IO MD00 AB02 - NC C15 IO HD20 K25 IO MD01 AB03 - NC

E14 IO HD21 L26 IO MD02 AB04 - NC B11 IO HD22 L25 IO MD03 AC01 - NC D14 IO HD23 M26 IO MD04 AB10 IO PAR B15 IO HD24 M24 IO MD05 AF15 IO PCKRUN# D13 IO HD25 N26 IO MD06 AB15 I PCL C13 IO HD26 N24 IO MD07 G02 O PD00

E09 IO HD27 P23 IO MD08 H02 O PD01 C12 IO HD28 P25 IO MD09 H01 O PD02 D12 IO HD29 R23 IO MD10 J02 O PD03

E15 IO HD30 R25 IO MD11 J01 O PD04 A13 IO HD31 P22 IO MD12 H04 O PD05 B12 IO HD32 T23 IO MD13 K06 O PD06 B13 IO HD33 T25 IO MD14 J04 O PD07 A12 IO HD34 T22 IO MD15 J03 O PD08

E13 IO HD35 AD22 IO MD16 L05 O PD09 D11 IO HD36 AF22 IO MD17 D10 IO HD37 AB21 IO MD18 J05 O PD11

D08 IO HD47 AF17 IO MD28 M04 O PD21 B08 IO HD48 AB17 IO MD29 M05 O PD22

4# AC20 IO MD52 F03 IO SCL

E03 A IRSET AE17 IO MD59 F05 I SUSP U01 IO VVS

02 O PD10

F07 P VCC3 F10 P VCC3 F12 P VCC3 F17 P VCC3

F20 P VCC3 G06 P VCC3 G21 P VCC3 H06 P VCC3 K21 P VCC3 L04 P VCC3 T04 P VCC3 U21 P VCC3

W06 P VCC3

Y06 P VCC3 Y21 P VCC3

AA07 P VCC3 AA10 P VCC3 AA17 P VCC3 AA20 P VCC3

U06 P VCC5 H21 P VCCA H22 P VCCA

W01 P VCCD

F09 P VCCI F18 P VCCI

J06 P VCCI

J21 P VCCI V06 P VCCI V21 P VCCI

AA09 P VCCI AA18 P VCCI

D01 P VCC C01 P VCCS

W02 P VCCV1

Y02 P VCCV2

T02 IO VD01

AA02 A VLF2

AA22 P VSUS2

V22 P VSUS3

W22 P VSUS3

AB22 P VSUS3

E11 P VTT F19 P VTT

Revision 1.86, April 22, 2005 -14- Pin Lists

Apollo PLE133 Data Sheet

Pin Descriptions

Table 1. VT8601A Pin Descriptions

CPU Interface

Signal Name Pin # I/O Signal Description

HA[31:3]#

HD[63:0]# ADS# BNR#

BPRI#

DBSY#

DEFER#

DRDY# HIT#

HITM#

HLOCK#

BREQ0# HREQ[4:0]#

HTRDY#

RS[2:0]#

CPURST# CPURSTD#

see pin list IO Host Address Bus. Connect to the address bus of the host CPU. These pins are inputs

during CPU cycles, but are driven by the VT8601A during cache snooping operations.

see pin list IO Host CPU Data. These signals are connected to the CPU data bus.

J24 IO Address Strobe. The CPU asserts ADS# in T1 of the CPU bus cycle.

D26 IO Block Next Request. Used to block the current request bus owner from issuing new

requests. This signal is used to dynamically control the processor bus pipeline depth.

E26 IO Priority Agent Bus Request. The owner of this signal will always be the next bus owner.

This signal has priority over symmetric bus requests and causes the current symmetric owner to stop issuing new transactions unless the HLOCK# signal is asserted. The VT82C693 drives this signal to gain control of the processor bus.

H26 IO Data Bus Busy. Used by the data bus owner to hold the data bus for transfers requiring

more than one cycle.

F26 IO Defer. The VT8601A uses a dynamic deferring policy to optimize system performance.

The VT8601A also uses the DEFER# signal to indicate a processor retry response.

J23 IO Data Ready. Asserted for each cycle that data is transferred.

G24 IO Hit. Indicates that a cacheing agent holds an unmodified version of the requested line.

Also driven in conjunction with HITM# by the target to extend the snoop window.

G26 I Hit Modified. Asserted by the CPU to indicate that the address presented with the last

assertion of EADS# is modified in the L1 cache and needs to be written back.

G23 I Host Lock. All CPU cycles sampled with the assertion of HLOCK# and ADS# until the

negation of HLOCK# must be atomic.

J25 O Bus Request 0. Bus request output to CPU. E25, F25, F24, F23,

E24

G25 IO Host Target Ready. Indicates that the target of the processor transaction is able to enter

H25, K23,

H23

A19 O CPU Reset. Reset output to CPU E22 O CPU Reset Delayed. CPU Reset output delayed by 2T.

IO Request Command. Asserted during both clocks of the request phase. In the first clock,

the signals define the transaction type to a level of detail that is sufficient to begin a snoop request. In the second clock, the signals carry additional information to define the complete transaction type.

the data transfer phase.

IO Response Signals. Indicates the type of response per the table below:

RS[2:0]#

000 Idle State 001 Retry Response 010 Defer Response 011 Reserved 100 Hard Failure 101 Normal Without Data 110 Implicit Writeback 111 Normal With Data

Response type

Revision 1.86, April 22, 2005 -15- Pin Descriptions

Apollo PLE133 Data Sheet

DRAM Interface

Signal Name Pin # I/O Signal Description

MD[63:0] MA[14:0] / Strap Options

CKE5# / SRASB#, CKE4# / SRASC#, CKE3# / SCASB#, CKE2# / SWEB#, CKE1# / SCASC#, CKE0# / SWEC# CS[5-0]#

DQM[7:0]

SRASA#, SRASB# / CKE5, SRASC# / CKE4

SCASA#, SCASB# / CKE3 SCASC# / CKE1

SWEA#, SWEB# / CKE2, SWEC# / CKE0

Note: Clocking of the memory subsystem uses memory clock (MCLK); see the clock pin group at the end of the pin descriptions

section for descriptions of the clock pins.

Note: Connect all memory interface pins except MD to the DRAM modules through 22Ω series resistors (see the Apollo PLE133

Design Guide” for more specific connection details and PCB layout recommendations).

see pin list IO

AF25, AE25, AE24, AD24, AE26, AD25, AD26, AC24, AC25,

AC26, AB24, AB25,

AB26, AB23, AA23

AA25, AA26,

V25, U25, V24,

U26

W21, Y22, Y23,

Y24, Y25, Y26 AF23, AD23, W25, W26, AE23, AF24,

W23, V23

AA24, AA25,

AA26

U22, V25,

V24

U24, U25,

U26

Memory Data.

O / I Memory Address. DRAM address lines. These pins are also used for

power-up strapping options (sampled on the rising edge of RESET#): MA14,12 Rx68[1-0] CPU FSB Freq (0=66, 1=100, 2=rsvd, 3=133) MA13 Rx52[7] GTL I/O Buffer Pullup (L=Enable, H=Disable) MA11 Rx50[7] In-Order Queue Depth (L=4-level, H=1-level) MA10-9 North Bridge Clock Delay (0-3 Clocks) MA8, 2 Graphics Clock Select (0=Normal, 1-3=Test) MA7 Graphics Test Mode (L=Normal, H=Test) MA1-0 Graphics Clock Delay (0-3 Clocks) All pins have internal pull-downs for default low (L). Strap high (H) using 4.7KΩ TO VCC3.

IO SDRAM Clock Enable. Clock enables 5-0 may be connected to the

DRAM modules in any order. Each DRAM module requires 2 clock enables. Note: These pins are powered by VSUS

O Chip Select. One per bank (powered by VSUS

O Data Mask. One per byte lane (powered by VSUS

O Row Address Command Indicator. For support of up to three

Synchronous DRAM DIMM slots (these are copies of the same logical signal). “A” controls banks 0-1 (module 0), “B” controls banks 2-3 (module 1), and “C” controls banks 4-5 (module 2).

O Column Address Command Indicator. For support of up to three

Synchronous DRAM DIMM slots (these are copies of the same logical signal). “A” controls banks 0-1 (module 0), “B” controls banks 2-3 (module 1), and “C” controls banks 4-5 (module 2).

O Write Enable Command Indicator. For support of up to three

Synchronous DRAM DIMM slots (these are copies of the same logical signal). “A” controls banks 0-1 (module 0), “B” controls banks 2-3 (module 1), and “C” controls banks 4-5 (module 2). Note: These pins are powered by VSUS.

)

Revision 1.86, April 22, 2005 -16- Pin Descriptions

Apollo PLE133 Data Sheet

PCI Bus Interface

Signal Name Pin # I/O Signal Description

AD[31:0]

CBE[3:0]#

PAR FRAME#

IRDY#

TRDY#

STOP#

DEVSEL#

LOCK#

SERR#

PREQ#

PGNT#

REQ[7:0]#

GNT[7:0]#

INTA#

Note: Clocking of the PCI interface is performed with PCLK; see the clock pin group at the end of the pin descriptions section for

descriptions of the clock input pins.

see pin list IO Address/Data Bus. The standard PCI address and data lines. The address is

driven with FRAME# assertion and data is driven or received in following cycles.

AD7, AD9, AB11,

AF12

AB10 IO Parity. A single parity bit is provided over AD[31:0] and C/BE[3:0].

AE9 IO Frame. Assertion indicates the address phase of a PCI transfer. Negation

AC10 IO

AD10 IO

AE10 IO Stop. Asserted by the target to request the master to stop the current

AB9 IO Device Select. This signal is driven by the PLE133 when a PCI initiator is

AE5 IO

AF10 IO System Error. The PLE133 will pulse this signal when it detects a system

AC15 I South Bridge Request. This signal comes from the South Bridge. PREQ# is

AD15 O South Bridge Grant. This signal driven by the PLE133 to grant PCI access to

AD1, AC3, AC2, AF2, AD4, AE4, AD5, AC5

AE1, AD3, AD2,

AE2, AE3, AF3, AF4,

AB5

W5 O PCI Interrupt Out. INTA# is an asynchronous active low output used to

IO Command/Byte Enables. Commands are driven with FRAME# assertion.

Byte enables corresponding to supplied or requested data are driven on following clocks.

indicates that one more data transfer is desired by the cycle initiator. 10KΩ pullup to VCC3.

Initiator Ready. Asserted when initiator is ready for data transfer. 10KΩ pullup to VCC3.

Target Ready. Asserted when target is ready for data transfer. 10KΩ pullup to VCC3.

transaction. 10KΩ pullup to VCC3.

attempting to access main memory. It is an input when the PLE133 is acting as a PCI initiator. 10KΩ pullup to VCC3. Lock. Used to establish, maintain, and release resource lock. 10KΩ pullup to VCC3.

error condition (10KΩ pullup to VCC3).

the South Bridge request for the PCI bus. 10KΩ pullup to VCC3.

the South Bridge. 10KΩ pullup to VCC3.

PCI Master Request. PCI master requests for use of the PCI bus. 2.2KΩ pullup to VCC5.

O PCI Master Grant. Permission is given to the master to use the PCI bus.

2.2KΩ pullup to VCC3.

signal an event that requires handling. It is driven by the integrated graphics controller.

Revision 1.86, April 22, 2005 -17- Pin Descriptions

Apollo PLE133 Data Sheet

Clock / Reset Control

Signal Name Pin # I/O Signal Description

HCLK

MCLKI

MCLKO

PCLK

PCKRUN#

XLTI

XLTO

RESET#

CPURST# CPURSTD# PWROK SUST#

SUSP

G22 I Host Clock. This pin receives the host CPU clock. This clock is used by all logic in

the host CPU domain. It is driven by the external clock synthesizer.

K22 I Memory Clock In. This clock is used by internal clock logic to maintain the proper

phase relationship with MCLKO. It is driven by the external clock synthesizer.

J22 O Memory Clock Out. Created on-chip from MCLKI and used by the memory

controller as a timing reference for creation of all memory timing sequences. It is connected to the external clock chip for use in maintaining proper phase relationships.

AB15 I PCI Clock. This clock is used by all on-chip logic in the PCI clock domain. This input

must be 33 MHz maximum to comply with PCI specification requirements and must be synchronous with the host CPU clock (HCLK) with an HCLK:PCLK frequency ratio of 2:1 (66MHz CPU clock) or 3:1 (100 MHz CPU clock). The PCI clock needs to be controlled to within 1.5 ± 0.5 nsec relative to the host CPU clock (CPU leads).

AF15 IO PCI Clock Run. For implementation of PCI bus clock control for low-power PCI bus

operation. Refer to the “PCI Mobile Design Guidelines” and “Apollo PLE133 Design Guide” documents for additional information.

Y4 I Crystal Input. 14.31818 MHz for the video clock synthesizer reference. Connect to a

14.31818 MHz clock source if a crystal not used. Connect to main ground plane GND with 10Pf if using a crystal.

W4 O Crystal Output. 14.31818 MHz for the video clock synthesizer reference. Leave open

if a clock source is used instead of a crystal. Connect to main ground plane GND with 10Pf if using a crystal.

AE15 I Reset. Driven from the South Bridge PCIRST# signal. When asserted (low), this

signal resets the PLE133 and sets all register bits to the default value. This signal also connects to the PCI bus (South Bridge RESET drives the ISA bus if implemented). The rising edge of this signal is used to sample all power-up strap options (see memory

interface MA pins). A19 O CPU Reset. CPU Reset output to the host CPU. E22 O CPU Reset Delayed 2T. Alternate CPU Reset output to the host CPU

AD14 I Power OK. Connect to South Bridge and Power Good circuitry. AC22 I Suspend Status. For implementation of the Suspend-to-DRAM feature. Input logic for

this pin is powered by VSUS. Connect to the South Bridge SUST# pin or to a 10KΩ

pullup to VSUS if not used.

F5 I Suspend. Used to put the integrated graphics controller into suspend state. Input logic

for this pin is powered by VCC3. Connect to South Bridge GPO pin or to a 10KΩ

pullup to VCC3 if not used.

Miscellaneous

Signal Name Pin # I/O Signal Description

ETST#

IMIO IMIIN

Revision 1.86, April 22, 2005 -18- Pin Descriptions

F4 I M2 O IMI Out. Leave open. M3 I

Test Mode Enable. 4.7KΩ pullup to VCC3 for normal operation.

IMI In. 4.7KΩ pullup to VCC3.

Apollo PLE133 Data Sheet

CRT Interface

Signal Name Pin # I/O Signal Description

RED

GRN BLUE HSYNC

VSYNC

SDA

SCL

C2 A

D3 A Green. Green analog output to the CRT. Connect same as RED. D2 A Blue. Blue analog output to the CRT. Connect same as RED.

E2 O Horizontal Sync. Digital horizontal sync output to the CRT. Also used (with VSYNC)

E1 O Vertical Sync. Digital vertical sync output to the CRT. Also used (with HSYNC) to

F2 IO DDC Data/Address. Serial I

F3 IO DDC Clock. Serial I

Red. Red analog output to the CRT. Connect 75Ω load resistor to GNDR (RGB Return) and connect to VGA connector through a series ferrite bead and 10pF capacitors to GNDR on both input and output sides of the bead (see “Apollo PLE133 Design Guide”).

to signal power management state information to the CRT per the VESA™ DPMS™ standard. Connect to VGA connector through a series 47Ω resistor and 120pF capacitor to ground (see “Apollo PLE133 Design Guide”).

signal power management state information to the CRT per the VESA™ DPMS™ standard. Connect to VGA connector through a series 47Ω resistor and 120pF capacitor to ground (see “Apollo PLE133 Design Guide”).

Connect this pin to VCC5 through a 4.7KΩ pullup. Connect to the VGA connector only (pin 12 of the connector). Connect through a ferrite bead and 120pF capacitor to ground (on the output side of the bead). Refer to the “Apollo PLE133 Design Guide” for additional information.

pin to VCC5 through a 4.7KΩ pullup. Connect to the VGA connector only (pin 15 of the VGA connector). Connect through a ferrite bead and 120pF capacitor to ground (on the output side of the bead). Refer to the “Apollo PLE133 Design Guide” for additional information.

C protocol for VESA™ DDC2B signaling to the CRT. Connect this

C protocol for VESA™ DDC2B signaling to the CRT.

DFP Interface

Signal Name Pin # I/O Signal Description

PD[23-0] SCLK DE LP FLM EVDD EVEE EBLT

Note: Connect SHFCLK, DE, LP, and FLM to external TMDS transmitters through series 22Ω resistors. See the “Apollo PLE133 Design Guide” for DFP interface design examples and additional information.

(see pin list) O Panel Data. Digital pixel data outputs to the panel.

G4 O Shift Clock. Clock for transferring digital pixel data. H3 O Data Enable. Indicates valid data on PD[23-0]. G5 O Line Pulse. Digital monitor equivalent of HSYNC. G3 O First Line Marker. Digital monitor equivalent of VSYNC.

F1 O H5 O G1 O

Enable Panel VDD Power. Enable Panel VEE Power. Enable Panel Backlight.

Revision 1.86, April 22, 2005 -19- Pin Descriptions

Apollo PLE133 Data Sheet

TV Input / Video Interface

Signal Name Pin # I/O Signal Description

VD[15-0]

VHS VVS VCLK

Note: Refer to the “Apollo PLE133 Design Guide” for video interface design examples.

N4, N1, N2, N5, P4, P3, P2, P5,

R3, R1, R4, R2, R5, T1, T2, R6

T3 IO Video Horizontal Sync. Connect to TV decoder if used. U1 IO Video Vertical Sync. Connect to TV decoder if used. U3 IO

Video Capture / Playback Data.

Video Clock. Connect to TV decoder through a series 22Ω resistor.

TV Output Interface

Signal Name Pin # I/O Signal Description

TVD[7-0] TVHS TVVS TVCLK

Note: Refer to the “Apollo PLE133 Design Guide” for TV interface design examples.

U2, T6, U4, T5, V3, U5, V2, V1 O TV Output Data. Connect to TV encoder if used.

V5 O TV Horizontal Sync. Connect to TV encoder if used.

W3 O TV Vertical Sync. Connect to TV encoder if used.

V4 O

TV Clock. Connect to TV encoder through a series 22Ω resistor.

Revision 1.86, April 22, 2005 -20- Pin Descriptions

Apollo PLE133 Data Sheet

Clock Power / Ground and Filtering

Signal Name Pin # I/O Signal Description

VCCA

GNDA

VCCV1

GNDV1

VLF1

VCCV2

GNDV2

VLF2

PLLTST

H21, H22 P Power for North Bridge Clock Circuitry (2.5V ±5%). Connect to VCCI through a

ferrite bead and decouple to GNDA with 0.001Uf and 0.1Uf ceramic and 10Uf tantalum capacitors (see “Apollo PLE133 Design Guide”).

L21, L22 P Ground for North Bridge Clock Circuitry. Connect to main ground plane GND

through a ferrite bead. (see “Apollo PLE133 Design Guide”).

W2 P Power for Video Clock Synthesizer 1 Analog Circuitry (2.5V ±5%). Connect to

VCCI through a ferrite bead and decouple to GNDV1 with 0.001Uf and 0.1Uf ceramic and 10Uf tantalum capacitors (see “Apollo PLE133 Design Guide”).

Y1 P Ground for Video Clock Synthesizer 1. Connect to main ground plane through a

ferrite bead.

Y3 A Low Pass Filter Capacitor for Video Clock Synthesizer 1. Connect to GNDV1

through a 560Pf capacitor.

Y2 P Power for Video Clock Synthesizer 2 Analog Circuitry (2.5V ±5%). Connect to

VCCI through a ferrite bead and decouple to GNDV2 with 0.001Uf and 0.1Uf ceramic and 10Uf tantalum capacitors (see “Apollo PLE133 Design Guide”).

AA1 P Ground for Video Clock Synthesizer 2. Connect to main ground plane through a

ferrite bead.

AA2 A Low Pass Filter Capacitor for Video Clock Synthesizer 2. Connect to GNDV2

through a 560Pf capacitor.

K24 I PLL Test. Pull down with 4.7K resistor for normal operation.

RAMDAC Output Power / Ground and Analog Control

Signal Name Pin # I/O Signal Description

VCCS

GNDS

COMP

IRSET

GNDRGB

Commonly Used Prefix / Suffix Letters in Signal Names: I = Internal Logic A = North Bridge Clock Synthesizer M = Memory (SDRAM) Interface V1 = Video Clock Synthesizer PLL1 H = Host CPU Interface V2 = Video Clock Synthesizer PLL2 P = PCI Bus Interface D = Video Clocks Digital Data Path G = AGP Bus (internal in PLE133) R = RAMDAC Digital Data Path GM = Graphics Memory Interface S = RAMDAC Current Source U (or USB) = USB (Universal Serial Bus) RGB = Analog Video Out Return H (or HWM) = Hardware Monitoring TV = TV Out SUS = Suspend Power V = TV In / Video Capture

C1 P Power for RAMDAC Current Source Circuitry (2.5V ±5%). Connect to VCCI

through a ferrite bead and decouple to GNDS with 0.001uF and 0.1uF ceramic and 10uF tantalum capacitors (see “Apollo PLE133 Design Guide”).

B1 P Ground for RAMDAC Current Source Circuitry. Connect to main ground plane

through a ferrite bead.

E4 A Compensation Capacitor. RAMDAC analog control. Connect to VCCS using a 0.1

uF capacitor.

E3 A RAMDAC Current Set Point Resistor. RAMDAC analog control. Connect to

GNDS through a 360Ω 1% resistor.

A1 P RGB Video Output Return. Connection point for the RGB load resistors. Also used

as a shield for the RGB video output traces to the VGA display connector. Connects to RGB return pins 6, 7, and 8 of the VGA connector. Connect to main ground plane through a ferrite bead. Refer to the “Apollo PLE133 Design Guide” for more specific connection and PCB layout details.

Revision 1.86, April 22, 2005 -21- Pin Descriptions

Apollo PLE133 Data Sheet

Digital Power and Ground

Signal Name Pin # I/O Signal Description

VCC5

VCC3

VSUS3

VSUS2

VCCI

VCCD

VCCR

VTT GTLREF

GND

U6 P Power for Display / Video Interfaces (5V ±5%). Power for CRT

H/VSYNC, DFP interface, video interface, and TV interface. Used to provide adequate output voltage swing for driving external video devices. Also used to provide 5V input tolerance from those interfaces.

F7, F10, F12, F17, F20, G6,

G21, H6, K21, L4, L12, L15,

M11, M16, R11, R16, T4, T12,

T15, U21, W6, Y6, Y21, AA7,

AA10, AA17, AA20

V22, W22, AB22 P Suspend Power (3.3V ±5%). Power for memory interface signals

AA22 P Suspend Power (2.5V ±5%). Connect to VCCI if suspend functions

F9, F18, J6, J21, V6, V21,

AA9, AA18

W1 P Power for Video Clock Synthesizer Digital Logic (2.5V ±5%).

D1 P Power for RAMDAC Video Output Digital Logic (2.5V ±5%).

E11, F19 P CPU Interface Termination Voltage (1.5V ±10%). E12, E21 P CPU Interface GTL+ Voltage Reference. 2/3 VTT ±2%. Derived

A9, A18, A26, B2, C8, C14, C19, D4, D23, F6, F13-F14,

F16, F21, H24, J26, L11, L13,

L14, L16, M12-M15, M21,

N3, N6, N11-N16, N21, P1, P6,

P11-P16, P21, R12-R15, T11,

T13, T14, T16, T21, V26,

W24, AA6, AA13-AA15,

AA21, AC4, AC23, AD8,

AD13, AD19, AF1, AF9,

AF18, AF26 A2-A5, B3-B5, C3-C5, Y5, AA3-AA5, AB1-AB4, AC1

P Power for On-Board Interfaces (3.3V ±5%). Power for host CPU /

L2 Cache interface, PCI bus interface, and memory interface (except pins listed below under VSUS).

SRASC#, SCASC#, SWEC#, SWEB#, RAS[5-0]#, CAS[7-0]#, and SUST#. Connect to VCC3 if suspend functions are not implemented.

are not implemented.

P Power for On-Chip Internal Logic (2.5V ±5%).

Connect to VCCI through a ferrite bead and decouple to main ground plane GND with 0.001uF and 0.1uF ceramic and 10uF tantalum capacitors (see “Apollo PLE133 Design Guide”).

from the termination voltage to the pullup resistors. Determines the noise margin for the host CPU interface signals. Internally connects to

the GTL

P Ground. Connect to primary PCB ground plane.

No Connect.

sense amp on each GTL+ input or I/O pin.

Revision 1.86, April 22, 2005 -22- Pin Descriptions

Apollo PLE133 Data Sheet

REGISTERS

The following tables summarize the configuration and I/O registers of the PLE133. These tables also document the power-on default value (“Default”) and access type (“Acc”) for each register. Access type definitions used are RW (Read/Write), RO (Read/Only), “—” for reserved / used (essentially the same as RO), and RWC (or just WC) (Read / Write 1’s to Clear individual bits). Registers indicated as RW may have some read/only bits that always read back a fixed value (usually 0 if unused); registers designated as RWC or WC may have some read-only or read write bits (see individual register descriptions following these tables for details). All offset and default values are shown in hexadecimal unless otherwise indicated.

Table 2. Register Summary

I/O Ports

Port # I/O Port Default Acc

Revision 1.86, April 22, 2005 -23- Register Summary Tables

Apollo PLE133 Data Sheet

Device 0 Bus 0 Registers - Host Bridge

PCI Configuration Registers

Offset Confi

uration Header Default Acc

Device-Specific Configuration Registers

Offset CPU Interface Control Default Acc

Offset DRAM Control Default Acc

Device-Specific Configuration Registers (continued)

Offset PCI Bus Control Default Acc

Offset GART/TLB Control Default Acc

Offset AGP Control Default Acc

Offset BIOS Scratch Default Acc

F0-F7 BIOS Scratch 00 RW

Offset Miscellaneous Control Default Acc

F8 DRAM Arbitration Timer 1 00 RW F9 DRAM Arbitration Timer 9 00 RW

FA CPU Direct Access FB Base Address 00 RW

FB Frame Buffer Conrol 00 RW

Offset Back Door Control Default Acc

FC Back Door Control 1 00 RW

FD BackDoor Control 2 00 RW

Revision 1.86, April 22, 2005 -24- Register Summary Tables

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Specifications and Main Features

Frequently Asked Questions

User Manual