Via CN333 User Manual

Data Sheet

CN333 North Bridge

with Integrated UniChrome Pro 3D / 2D Graphics Controller

Revision 1.0 January 5, 2005

VIA TECHNOLOGIES, INC.

Copyright © 2004-2005, VIA Technologies Incorporated. All Rights Reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise without the prior written permission of VIA Technologies Incorporated. The material in this document is for information only and is subject to change without notice. VIA Technologies Incorporated reserves the right to make changes in the product design without reservation and without notice to its users.

Copyright © 2004-2005, S3 Graphics Incorporated. All rights reserved. If you have received this document from S3 Graphics Incorporated in electronic form, you are permitted to make the following copies for business use related to products of S3 Graphics Incorporated: one copy onto your computer for the purpose of on-line viewing, and one printed copy. With respect to all documents, whether received in hard copy or electronic form, other use, copying or storage, in whole or in part, by any means electronic, mechanical, photocopying or otherwise, is not permitted without the prior written consent of S3 Graphics Incorporated. The material in this document is for information only and is subject to change without notice. S3 Graphics Incorporated reserves the right to make changes in the product design without reservation and without notice to its users.

Trademark Notices:

VT8237R and CN333 may only be used to identify products of VIA Technologies.

C3™ and PowerSaver™ are registered trademarks of VIA Technologies. Windows XP™, Windows 2000™, Windows ME™, Windows 98™ and Plug and Play™ are registered trademarks of Microsoft Corporation. PCI™ is a registered trademark of the PCI Special Interest Group. VESA™ is a trademark of the Video Electronics Standards Association. All trademarks are the properties of their respective owners.

Disclaimer Notice:

No license is granted, implied or otherwise, under any patent or patent rights of VIA Technologies or S3 Graphics. VIA Technologies and S3 Graphics make no warranties, implied or otherwise, in regard to this document and to the products described in this document. The information provided by this document is believed to be accurate and reliable as of the publication date of this document. However, VIA Technologies and S3 Graphics assume no responsibility for any errors in this document. Furthermore, VIA Technologies and S3 Graphics assume no responsibility for the use or misuse of the information in this document and for any patent infringements that may arise from the use of this document. The information and product specifications within this document are subject to change at any time, without notice and without obligation to notify any person of such change.

Offices:

VIA Technologies Incorporated Taiwan Office:

Floor, No. 531

1 Chung-Cheng Road, Hsin-Tien Taipei, Taiwan ROC Tel: (886-2) 2218-5452 Fax: (886-2) 2218-5453

Home page:

http://www.via.com.tw

VIA Technologies Incorporated USA Office: 940 Mission Court Fremont, CA 94539 USA Tel: (510) 683-3300 Fax: (510) 683-3301 or (510) 687-4654

Home Page:

http://www.viatech.com

S3 Graphics Incorporated USA Office: 1045 Mission Court Fremont, CA 94539 USA Tel: (510) 687-4900 Fax: (510) 687-4901

Home Page:

http://www.s3graphics.com

CN333 Data Sheet

REVISION HISTORY

Document Release Date Revision Initials

1.0 1/5/05 Initial external release SV

Revision 1.0, January 5, 2005 -i- Revision History

CN333 Data Sheet

TABLE OF CONTENTS

REVISION HISTORY .......................................................................................................................................................................I

TABLE OF CONTENTS.................................................................................................................................................................. II

LIST OF FIGURES .........................................................................................................................................................................IV

LIST OF TABLES ...........................................................................................................................................................................IV

PRODUCT FEATURES.................................................................................................................................................................... 1

CN333 SYSTEM OVERVIEW......................................................................................................................................................... 5

VIA C3 PROCESSOR INTERFACE.................................................................................................................................................. 5

MEMORY CONTROLLER................................................................................................................................................................ 5

ULTRA V-LINK .............................................................................................................................................................................. 6

SYSTEM POWER MANAGEMENT ................................................................................................................................................... 6

3D GRAPHICS ENGINE................................................................................................................................................................... 6

128-BIT 2D GRAPHICS ENGINE ..................................................................................................................................................... 6

MPEG VIDEO PLAYBACK............................................................................................................................................................. 6

LCD AND DVI MONITOR SUPPORT.............................................................................................................................................. 7

DESKTOP MODES FOR SINGLE DISPLAY....................................................................................................................................... 8

PINOUTS............................................................................................................................................................................................ 9

PIN DIAGRAMS............................................................................................................................................................................... 9

PIN LISTS ..................................................................................................................................................................................... 10

PIN DESCRIPTIONS....................................................................................................................................................................... 13

CPU Interface Pin Descriptions .......................................................................................................................................... 13

DDR SDRAM Memory Controller Pin Descriptions......................................................................................................... 14

Ultra V-Link Pin Descriptions............................................................................................................................................. 15

CRT and Serial Bus Pin Descriptions................................................................................................................................. 16

Flat Panel Display Port (FPDP) Pin Descriptions.............................................................................................................. 17

Digital Video Port 1 (GDVP1) Pin Descriptions ................................................................................................................ 18

Clock, Reset, Power Control, GPIO, Interrupt and Test Pin Descriptions..................................................................... 19

Compensation and Reference Voltage Pin Descriptions ................................................................................................... 20

Power Pin Descriptions ........................................................................................................................................................ 21

Strap Pin Descriptions.......................................................................................................................................................... 22

REGISTERS..................................................................................................................................................................................... 23

REGISTER OVERVIEW ................................................................................................................................................................. 23

MISCELLANEOUS I/O................................................................................................................................................................... 30

CONFIGURATION SPACE I/O ....................................................................................................................................................... 30

DEVICE 0 FUNCTION 0 REGISTERS – AGP................................................................................................................................. 31

Device 0 Function 0 Header Registers ................................................................................................................................ 31

AGP GART / Graphics Aperture...........................................................................................................................................................34

DEVICE 0 FUNCTION 1 REGISTERS – ERROR REPORTING......................................................................................................... 35

Device 0 Function 1 Header Registers ................................................................................................................................ 35

Device 0 Function 1 Device-Specific Registers ................................................................................................................... 36

V-Link Error Reporting......................................................................................................................................................................... 36

AGP Error Reporting............................................................................................................................................................................. 36

Revision 1.0, January 5, 2005 -ii- Table of Contents

CN333 Data Sheet

DEVICE 0 FUNCTION 2 REGISTERS – HOST CPU....................................................................................................................... 37

Device 0 Function 2 Header Registers ................................................................................................................................ 37

Device 0 Function 2 Device-Specific Registers ................................................................................................................... 38

Host CPU Control .................................................................................................................................................................................38

Host CPU AGTL+ I/O Control .............................................................................................................................................................42

DEVICE 0 FUNCTION 3 REGISTERS – DRAM............................................................................................................................. 43

Device 0 Function 3 Header Registers ................................................................................................................................ 43

Device 0 Function 3 Device-Specific Registers ................................................................................................................... 44

DRAM Control...................................................................................................................................................................................... 44

ROM Shadow Control........................................................................................................................................................................... 52

DRAM Above 4G Control ....................................................................................................................................................................53

UMA Control ........................................................................................................................................................................................54

Graphics Control ................................................................................................................................................................................... 55

AGP Controller Interface Control .........................................................................................................................................................55

DRAM Drive Control............................................................................................................................................................................ 56

DEVICE 0 FUNCTION 4 REGISTERS – POWER MANAGEMENT ................................................................................................... 57

Device 0 Function 4 Header Registers ................................................................................................................................ 57

Device 0 Function 4 Device-Specific Registers ................................................................................................................... 58

Power Management Control.................................................................................................................................................................. 58

BIOS Scratch......................................................................................................................................................................................... 58

DEVICE 0 FUNCTION 7 REGISTERS – V-LINK ............................................................................................................................ 59

Device 0 Function 7 Header Registers ................................................................................................................................ 59

Device 0 Function 7 Device-Specific Registers ................................................................................................................... 60

V-Link Control...................................................................................................................................................................................... 60

PCI Bus Control ....................................................................................................................................................................................63

Graphics Aperture Control .................................................................................................................................................................... 65

V-Link CKG Control............................................................................................................................................................................. 65

V-Link Compensation / Drive Control.................................................................................................................................................. 66

DRAM Above 4G Support.................................................................................................................................................................... 66

DEVICE 1 REGISTERS – PCI-TO-PCI BRIDGE............................................................................................................................ 67

Device 1 Header Registers.................................................................................................................................................... 67

Device 1 Device-Specific Registers ...................................................................................................................................... 69

AGP Bus Control................................................................................................................................................................................... 69

ELECTRICAL SPECIFICATIONS .............................................................................................................................................. 71

ABSOLUTE MAXIMUM RATINGS ................................................................................................................................................. 71

DC CHARACTERISTICS ............................................................................................................................................................... 71

MECHANICAL SPECIFICATIONS............................................................................................................................................. 72

Revision 1.0, January 5, 2005 -iii- Table of Contents

CN333 Data Sheet

LIST OF FIGURES

FIGURE 1. SYSTEM BLOCK DIAGRAM.................................................................................................................................... 5

FIGURE 2. INTEGRATED UNICHROME PRO GRAPHICS CONTROLLER INTERNAL BLOCK DIAGRAM ............ 7

FIGURE 3. BALL DIAGRAM (TOP VIEW) – FLAT PANEL / DIGITAL VIDEO OUTPUT................................................ 9

FIGURE 4. GRAPHICS APERTURE ADDRESS TRANSLATION......................................................................................... 34

FIGURE 5. MECHANICAL SPECIFICATIONS – 681-PIN HSBGA BALL GRID ARRAY PACKAGE WITH HEAT

SPREADER................................................................................................................................................................. 72

FIGURE 6. LEAD-FREE MECHANICAL SPECIFICATIONS – 681-PIN HSBGA BALL GRID ARRAY PACKAGE

WITH HEAT SPREADER........................................................................................................................................ 73

LIST OF TABLES

TABLE 1. SUPPORTED CRT AND PANEL SCREEN RESOLUTIONS.................................................................................. 8

TABLE 2. PIN LIST (LISTED BY PIN NUMBER).................................................................................................................... 10

TABLE 3. PIN LIST (LISTED BY PIN NAME) ......................................................................................................................... 11

TABLE 4. POWER, GROUND AND VOLTAGE REFERENCE PIN LIST............................................................................ 12

Revision 1.0, January 5, 2005 -iv- Lists of Figures and Tables

CN333 Data Sheet

CN333 NORTH BRIDGE

133 / 100 MHz VIA C3 Front Side Bus

Integrated UniChrome Pro 3D / 2D Graphics and Video Controllers

Advanced DDR333 SDRAM Controller

1 GB / Sec Ultra V-Link Interface

PRODUCT FEATURES

• Defines Highly Integrated Solutions for Full Featured, Power Efficient PC Designs

– High Performance UMA North Bridge: Integrated VIA C3 North Bridge with 133 / 100 MHz FSB support and

UniChrome Pro 3D / 2D Graphics and Video Controllers in a single chip – Advanced memory controller supporting DDR 333 / 266 / 200 SDRAM – Combines with VIA VT8235M-CE / VT8237R South Bridge for integrated 10/100 LAN, Audio, ATA133 IDE, LPC,

USB 2.0 and Serial ATA (VT8237R) – “Lead-Free” 31 x 31mm HSBGA (Ball Grid Array with Heat Spreader) package with 681 balls and 1mm ball pitch

• High Performance CPU Interface

– Supports 133 / 100 MHz FSB VIA C3 processors – Eight outstanding transactions (eight-level In-Order Queue (IOQ)) – Built-in Phase Lock Loop circuitry for optimal skew control within and between clocking regions

• Advanced High-Performance 64-Bit DDR SDRAM Controller

– Supports DDR333 / 266 memory types with 2.5V SSTL-2 DRAM interface – Supports mixed 64 / 128 / 256 / 512 / 1024Mb DDR SDRAMs in x8 and x16 configurations – Supports CL 2 / 2.5 for DDR266 / 333 – Supports 2 unbuffered double-sided DIMMs and up to 4 GBytes of physical memory – Programmable timing / drive for memory address, data and control signals – DRAM interface pseudo-synchronous with host CPU for optimal memory performance – Concurrent CPU, internal graphics controller and V-Link access for minimum memory access latency – Rank interleave and up to 16-bank page interleave (i.e., 16 pages open simultaneously) based on LRU to effectively

reduce memory access latency – Seamless DRAM command scheduling for maximum DRAM bus utilization

– (e.g., precharge other banks while accessing the current bank) – CPU Read-Around-Write capability for non-stalled operation – Speculative DRAM read before snoop result to reduce PCI master memory read latency – Supports Burst Read and Write operations with burst length of 4 or 8 – Eight cache lines (64 quadwords) of integrated CPU-to-DRAM write buffers and eight separate cache lines of CPU-

to-DRAM read prefetch buffers – Optional dynamic Clock Enable (CKE) control for DRAM power reduction during normal system state (S0) – Supports self-refresh and CAS-before-RAS DRAM refresh with staggered RAS timing

• High Bandwidth 1 GB / Sec 16-Bit “Ultra V-Link” Host Controller

– Supports 66 MHz, 4x and 8x transfer modes, Ultra V-Link Host interface with 1 GB / Sec total bandwidth – Full duplex transfers with separate command / strobe for 4x and 8x modes – Request / Data split transaction – Transaction assurance for V-Link Host-to-Client access eliminates V-Link Host-Client Retry cycles – Intelligent V-Link transaction protocol to minimize data wait-states, throttle transfer latency and avoid data overflow – Highly efficient V-Link arbitration with minimum overhead

Revision 1.0, January 5, 2005 -1- Product Features

CN333 Data Sheet

• Advanced System Power Management Support

– ACPI 2.0 and PCI Bus Power Management 1.1 compliant – Supports Suspend-to-DRAM (STR) and DRAM self-refresh – Supports dynamic Clock Enable (CKE) control for DRAM power reduction during normal system state (S0) – Supports SMI, SMM and STPCLK mechanisms – Supports VIA PowerSaver™ Technology – Low-leakage I/O pads

• Integrated Graphics with 2D / 3D / Video Controllers

– Optimized Unified Memory Architecture (UMA) – Supports 16 / 32 / 64 MB Frame Buffer sizes – 200 MHz Graphics Engine Clock – Two independent 128-bit data paths between North Bridge and graphics core to improve video performance, one for

frame buffer access and one for texture / command access – PCI v2.2 Host Bus compliant – AGP v3.0 compliant

2D Acceleration

– 128-bit 2D graphics engine – Hardware 2D rotation – Supports ROP3, 256 operations – Supports 8bpp, 15/16bpp and 32bpp color depth modes – BitBLT (Bit BLock Transfer) functions including alpha BLTs – True-color hardware cursor (64x64x32bpp) with 256-level blending effect – Color expansion, source Color Key and destination Color Key – Bresenham line drawing / style line function – Transparency mode – Window clipping – Text function

3D Acceleration

3D Graphics Processor

– 128-bit 3D graphics engine

– Dual pixel rendering pipes and dual texture units

– Floating-point setup engine

– Internal full 32-bit ARGB format for high rendering quality

– 8K Texture Cache

Capability

– Supports ROP2

– Supports various texture formats including 16/32bpp ARGB, 8bpp Palletized (ARGB), YUV 422/420 and

– Texture sizes up to 2048x2048 with Microsoft DirectX texture compression

– High quality texture filter for Nearest, Linear, Bi-linear, Tri-linear and Anisotropic modes

– Flat and Gouraud shading

– Vertex Fog and Fog Table

– Z-Bias, LOD-Bias, Polygon offset, Edge Anti-aliasing and Alpha Blending

– Bump mapping and cubic mapping

– Hardware back-face culling

– Specular lighting

Performance

– Two textures per pass

– Triangle rate up to 4.5 million triangles per second

– Pixel rate up to 200 million pixels per second for 2 textures each

– Texel bilinear fill rate up to 400 million texels per second

– High quality dithering

compressed texture (DXTC)

Revision 1.0, January 5, 2005 -2- Product Features

CN333 Data Sheet

Video Acceleration

High Quality Video Processor

– RGB555, RGB565, RGB8888 and YUV422 video playback formats

– High quality 5-tap horizontal and 5-tap vertical scaler (up or down) for both horizontal and vertical scaling

(linear interpolation for horizontal and vertical p-scaling and filtering for horizontal and vertical down-scaling) – Independent graphics and video gamma tables – 2 sets of Color and Chroma Key support – Color enhancement for contrast, hue, saturation and brightness – Display rotation in clockwise and counter-clockwise directions – Bob, Weave, Median-filter and Adaptive de-interlacing modes – 3:2 / 2:2 pull-down detection – De-blocking mode support – Combining of many special effects such as filter, scaling up or down, sub-picture blending, de-interlacing and

deblocking to one pass process – Tear-free double / triple buffer flipping – Input video vertical blanking or line interrupt – Video gamma correction

Video Overlay Engine

– Simultaneous graphics video playback overlay – Supports video window overlays – Supports 16 operations for Color and Chroma Key – Hardware sub-picture blending

MPEG Video Playback

– MPEG-2 hardware VLD (Various Length Decode), iDCT, and motion compensation for full speed DVD and

MPEG-2 playback at full D1 resolution – High quality DVD and streaming video playback – Video auto-flipping – Hardware DVD sub-picture blending

DuoView+™ Dual Image Capability

– WinXP, WinME and Win98 multi-monitor, extended desktop support – Two independent display engines, each of which can display completely different information at different

resolutions, pixel depths and refresh rates (supports different images on different displays simultaneously)

– CRT, FPD and DVI monitor refresh rates are independently programmable for optimum image quality – Improved display flexibility with simultaneous FPD / CRT, FPD, FPD / DVI and other combined operations

Full Software Support

– Microsoft DirectX 7.0, 8.0 and 9.0 compatible – Microsoft DirectX Texture Compression (DXTC / S3TC) – Supports OpenGL – Drivers for major operating systems and APIs: Windows

DirectDraw, DirectShow and OpenGL ICD for Windows 9x / ME and XP

– Windows NT 4.0 Standard VGA driver



9x / ME, Windows 2000, Windows XP, Direct3D,

Revision 1.0, January 5, 2005 -3- Product Features

CN333 Data Sheet

• Extensive Display Support for External Video Output

– CRT display interface – 12-bit Digital Video Port with support for external DVI transmitter – 24-bit / Dual 12-Bit FPD interface to external LVDS transmitter

CRT Display

– CRT display interface with 24-bit true-color RAMDAC up to 300 MHz pixel rate with gamma correction capability – Supports CRT resolutions up to 1920 x 1440

12-Bit DVI Transmitter Interface

– 1.5V low-swing interface supports external DVI transmitter for a driving a DVI monitor – Double-data-rate data transfer with clock rates up to 165 MHz – Built-in digital phase adjuster to fine-tune signal timing between clock and data bus

24-Bit Flat Panel Display (FPD) Interface

– Supports 18/24-bit FPD interface with external LVDS transmitter chip using single or double-data rate data transfer – Supports panel resolutions up to 1600x1200

Dual 12-Bit Flat Panel Display (FPD) Interface

– Alternate operating mode of FPD interface with external LVDS transmitters – Single or separate sets of clock and sync signals – Supports panel resolutions up to 1600x1200

• Advanced Graphics Power Management Support

– Built-in reference voltage generator and monitor sense circuits – Automatic panel power sequencing and VESA DPMS (Display Power Management Signaling) CRT power-down – External I/O signal controls enabling of graphics accelerator into standby / suspend-off state – Dynamic clock gating for inactive functions to achieve maximum power saving

– I

C Serial Bus and DDC / E-DDC Monitor Communications for Plug-and-Play configuration

Revision 1.0, January 5, 2005 -4- Product Features

CN333 Data Sheet

CN333 SYSTEM OVERVIEW

The CN333 is a high performance, cost-effective and energy efficient UMA North Bridge with integrated UniChrome Pro graphics / video controller used for the implementation of mobile and desktop personal computer systems with 133 / 100 MHz CPU host bus (“Front Side Bus”) based on VIA C3 processors.

VIA C3

CPU

CRT

TFT Flat Panel

133 / 100 MHz

Front Side Bus

RGB, HV, DDC

FPDP Flat Panel Display Port

24-Bit / Du al 12-Bit

Flat Pa nel Display In terface

VT1631 LVDS Transmitter

DVI Monitor

64-Bit DDR333 / 266 DIMMs

CN333

DDR North Bridge with UniChrome Pro Graphics Controller

GDVP1 Digital Video Port 1

12-Bit DVI Interface

VT1632A DVI Transmitter

Figure 1. System Block Diagram

66 MHz 8x / 4x V-Link

PCI Slots

USB 2.0

33MHz,

32-bit

PCI

AC'97 Audio Codec

System

Management

Bus

VT8237R

V-Link

South Bridge

AC-Link

VT1616

MC-97

Modem Codec

Integrated AC'97 Aud io

Network

Interface PHY

VT6103

MII

Pri

Sec

LPC

VT1211

Super

10/100 Ethernet

133 / 100 / 66 / 33

EPROM

Serial / IR

Parallel

LPC

Floppy Disk

I/O

Keyboard

Mouse

UDMA / ATA

The complete chipset consists of the CN333 North Bridge and the VT8237R V-Link South Bridge. The CN333 integrates VIA’s most advanced system controller with a high-performance UniChrome Pro 3D / 2D graphics / video controller plus flat panel and DVI monitor. The CN333 provides superior performance between the CPU, DRAM, V-Link and integrated graphics controller with pipelined, burst and concurrent operation. The VT8237R is a highly integrated peripheral controller which includes V-Linkto-PCI / V-Link-to-LPC controllers, Ultra DMA IDE controller, USB2.0 host controller, 10/100Mb networking MAC, AC97 and system power management controllers.

VIA C3 Processor Interface

The CN333 supports 133 / 100 MHz FSB VIA C3 processors and implements an eight-d eep In-Order-Queue. VIA PowerSaver technology is supported for VIA Antaur processors to reduce system power consumption while sustaining high processing power.

Memory Controller

The CN333 SDRAM controller supports up to two double-sided DDR333 / 266 DIMMs for 4 GB maximum physical memory. The DDR DRAM interface allows zero-wait-state data transfer bursting between the DRAM and the memory controller’s data buffers. The different banks of DRAM can be composed of an arbitrary mixture of 64 / 128 / 256 / 512 / 1024Mb DRAMs in x8 or x16 configurations. The DRAM controller can run either synchronous or pseudo-synchronous with the host CPU bus.

Revision 1.0, January 5, 2005 -5- Overview

CN333 Data Sheet

Ultra V-Link

The CN333 North Bridge interfaces to the South Bridge through a high speed (up to 1 GB / Sec) 8x, 66 MHz Data Transfer interconnect bus called “Ultra V-Link”. Deep pre-fetch an d post-write buffers are included to allow for concurrent CPU and VLink operation. The combined CN333 North Bridge and VT8237R South Bridge system supports enhanced PCI bus commands such as “Memory-Read-Line”, “Memory-Read-Multiple” and “Memory-Write-Invalid” commands to minimize snoo p overhead. In addition, advanced features are supported such as CPU write-back forward to PCI master and CPU write-back merg ed with PCI post write buffers to minimize PCI master read latency and DRAM utilization. Delay transaction and read caching mechanisms are also implemented for further improvement of overall system performance.

System Power Management

For sophisticated power management, the CN333 supports dynamic CKE control to minimize DDR SDRAM power consumption

during normal system state (S0). A separate suspend-well plane is implemented for the memory control logic for the Suspend-toDRAM state. VIA PowerSaver™ Technology is supported to minimize CPU power consumption while sustaining processing power. The CN333 graphics accelerator implements automatic clock gating for each graphics engine to achieve power saving, moving to standby or suspend states to further reduce power consumption when idle. Automatic panel power sequencing and VESA DPMS (Display Power Management Signaling) CRT power-down are supported. Coupled with the VT8237R South Bridge chip, a complete power conscious PC main board can be implemented with no external glue logic.

3D Graphics Engine

Featuring an integrated 128-bit 3D graphics engine, the CN333 No rth Bridge utilizes a highly pipelined architecture that prov ides high performance along with superior image quality. Several new features enhance the 3D architecture, including two pixel rendering pipes, single-pass multitexturing, bump and cubic mapping, texture comp ression, edge anti-aliasing, vertex fog and fog table, hardware back-face culling, specular lighting, anisotropic filtering and an 8-bit stencil buffer. The chip also offers the industry’s only simultaneous usage of single-pass multitexturing and single-cycle trilinear filtering – enabling stunning image quality without performance loss. Image quality is further enhanced with true 32-bit color rendering throughout the 3D pipeline to produce more vivid and realistic images. The advanced triangle setup engine provides industry leading 3D performance for a realistic user experience in games and other interactive 3D applications. The 3D engine is optimized for AGP texturing from system memory.

128-bit 2D Graphics Engine

The CN333 North Bridge's advanced 128-bit 2D graphics engine delivers high-speed 2D acceleration for productivity applications. The enhanced 2D architecture with direct access frame buffer capability optimizes UMA performance and provides acceleration of all color depths.

MPEG Video Playback

The CN333 North Bridge provides the ideal architecture for high quality MPEG-2 based video applications. For MPEG playback, the integrated video accelerator offloads the CPU by performing planar-to-packed format conversion and motion video compensation tasks, while the enhanced scaling algorithm delivers incredible full-screen video playback.

Revision 1.0, January 5, 2005 -6- Overview

CN333 Data Sheet

North Bridge Host Bus

66 MHz PCI Host Bus Inte rface

VGA GFX Controller

Command Engine

Display

128-bit 2D Engine

Engine

MPEG En g i n e

Video Processor

Vertex

Cache

Setup

En gi n e

Te x tu re

En gi n e

Te x tu re

Cache

3D Engine

AGP-lik e Interface

No rth B ridg e M e mory Controlle r

Figure 2. Integrated UniChrome Pro Graphics Controller Internal Block Diagram

LCD and DVI Monitor Support

IGA 1

Pane l

Digital Vid eo

Port 1

Port

Digital Video

24-Bit FPD

Mux

plus 12-Bit DVP

IGA 2

DAC

CRT

Video Engine

HW S prite

0/1

(Scaler /

Pipelines

Rendering

HW Cu rs or

GFX St re am

YUV-to-RGB)

Video S tre am

Me mo r y I n te rf ace Uni t

The CN333 provides two “Digital Video Port” interfaces: FPDP and GDVP1. The Flat Panel Display Port (FPDP) implements a 24-bit / dual 12-bit interface which is designed to drive a Flat Panel Display via an external LVDS transmitter ch ip (such as the VIA VT1631 or NSC DS90C387R). The CN333 can b e connected to the external LVDS transmitter chip in eith er 24-bit or dual12-bit modes. A wide variety of LCD panels are supported including VGA, SVGA, XGA, SXGA+ and up to UXGA-resolution TFT color panels, in either SDR (1 pixel / clock) or DDR (2 pixels / clock) modes. UXGA and higher resolutions require dualedge data transfer (DDR) mode which is supported by the VIA VT1631 LVDS transmitter chip. Digital Video Port 1 (GDVP1 ) is used to drive a DVI monitor via an external DVI transmitter chip (such as the VIA VT1632A).

The flexible display configurations of the CN333 allow support of a flat panel (LVDS interface) or flat panel monitor (DVI interface) and CRT display at the same time. Internally the CN333 North Bridge provides two separate display engines, so if two display devices are connected, each can display completely different information at different resolutions, pixel depths and refresh rates. If more than two display devices are connected, the additional displays mu st have the same resolution, pixel depth and refresh rate as one of the first two. The maximum display resolutions supported for one display device are listed in the table below. If more than one display is implemented (i.e., if both display engines are functioning at the same time), then available memory bandwidth may limit the display resolutions supported on one or both displays. This will be dependent on many factors including primarily clock rates and memory speeds (contact VIA for additional information).

Revision 1.0, January 5, 2005 -7- Overview

CN333 Data Sheet

Desktop Modes for Single Display

Resolution BPP 60 75 85 100 120

CRT Maximum Refresh

640x480

800x600

1024x768

1280x1024

1400x1050

1600x1200

1920x1440

√ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √1 √2 √ √ √ √ √ √

Table 1. Supported CRT and Panel Screen Resolutions

Key for Desktop Mode

√ = Supported: Mode available and Overlay available

√1 = Supported, but DDR266: Mode available, overlay not available. √2 = Supported, but DDR266: Mode not available, overlay not available.

Note: LCD Single Display modes follow the 60Hz refresh column.

Revision 1.0, January 5, 2005 -8- Overview

CN333 Data Sheet

PINOUTS

Pin Diagrams

Key 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

43#

37#

E NC

42#

51#

63#

46#

53#

62#

V CCA 3 3

HCK1

V CCA 1 5

PLL3

28#

GND

34#

38#

22#

GND

27#

39#

36#

45#

GND

49#

57#

55#

NC NC

GND

54#

56#

61#

GNDA

V CCA 3 3

HCK1

GCK

GNDA

V CCA 1 5

PLL3

PLL1

DISP

CLKI

CLKO

V CCA 3 3

V CCA 1 5

V CCA 3 3

T AB AG AR

SYNC V SYNC

CLK2

V CCA 3 3

DAT2 R SET

NC NC NC

29#

HD 31#

GND

HD 44#

HD 41#

HD 59#

HD 52#

HD 58#

HCK2

GNDA

PLL1 H CLK+ H CLK– T CLK

PLL2

DAC1

GNDA

DAC2

25#

26#

GND

24#

NC NC

32#

HD 33#

47#

GND GND

48#

40#

GND

50#

60#

GNDA

HCK2

GCK

GNDA

PLL2 G CLK

GNDA

DAC1

GNDA

DAC3

INTA# NC

NC NC

Y NC NC NC NC

AA NC NC NC NC

AB NC NC NC NC

AC NC GND NC NC GND

SBDDC

AD NC NC

AGP

COMPP

GDVP1

CLK

GDVP1

AGP

COMPN

GND

GDVP1

CLK#

GND

GDVP1

DET

DAT

CLK#

GDVP1

SBDDC

CLK

ENA VDD

GDVP1

DET

D12

GDVP1

6 7 AC8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 AC23 24

ENA

AGP

VEE

VREF1

ENA

BLT

GND NC

NC NC

GDVP1

D10

D11

GND

D14

D15

D16

Figure 3. Ball Diagram (Top View) – Flat Panel / Digital Video Output

22 23 24 25 26 27 28 29

HD 13#

HD 20#

HD 30#

GND

11#

12#

14#

18#

NC NC

VREF0

16#

GND

19#

HD 21#

GND

23#

HD 35#

7 H8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 H23 24 25

VREF3

VREF2

XIN

VCC

VTT VTT VTT VTT VTT VTT VTT VTT

VCC

VTT GND GND GND GND GND GND GND GND GND GND

VCC

VTT GND GND GND GND GND GND GND GND GND GND

VCC

VTT GND GND GND GND GND GND GND GND GND GND

VCC

VTT GND GND GND GND GND GND GND GND GND GND

VCC

VCC33

GFX

VCC

VCC33

GFX

VCC

VCC33

GFX

VCC

VCC15

AGP

VCC

VCC15

AGP

VCC

VCC15

AGP

VCC

VCC15

AGP

VCC

CLK

D17

D18

FP VS

D19

D13

GND

FP1

SBPL

CLK

GND

FP1

CLK#

D23

SBPL

DAT

D21

D00

FP1

DET

D22

FP D1

FP1

15#

HD 17#

VCC

VCC15

AGP

VCC

D20

FP D7

FP1

CLK

FP D6

FP D5

FP D8

COMP

VREF1

VCC

VCC15

AGP

VCC

AGP

VREF0

FP D9 V PAR

NC GND

10#

GND

VCC

GND GND GND GND GND GND GND GND GND GND

VCC15

AGP

VCC

D10

GND

D11

FP D2

GND

FP D4

GND

HA 29#

GND

HA 26#

HA 18#

HCOMP

VREF

VCC

VCC15

VCC

COMPP

VD 8 VD 5 VD 0 UP

GND GND

23#

HA 30#

HA 27#

HA 20#

HA 24#

HA 17#

GTL

VREF

VCC

VCC15

VCC

VREF

VD 4 DN

VD 1 V

GND

19#

HA 15#

HA 10#

HA 28#

GND

13#

12#

NC GND

16#

VREF0

VCC

VCC25

MEM

VCC25

MEM

VCC

VCC25

MEM

VCC25

MEM

VCC

31#

HA 22#

CPU

GND

RST#

HA 21#

GND

25#

GND

VCC

VCC25

MEM

VCC

STB–

GND

STB+

STB–

VD 3 VD

CMD

VD 2 VD 6 VD

GND

STB+

BE#

HA 11#

VREF1

VCC

VCC25

MEM

VCC25

MEM

VCC

GND

BNR# NC GND

VCC

VCC25

MEM

VCC25

MEM

VCC25

MEM

VCC25

MEM

VCC25

MEM

VCC25

MEM

VCC25

MEM

VCC25

MEM

VCC25

MEM

VCC25

MEM

VCC

MEM25

VCC25

MEM

VCC

HREQ

HA 14#

VCC

GND

PRI#

HREQ

GND

AGP

MEM

BUSY#

VREF5

VSUS

PWR

SET#

SUS ST#

GND

HREQ

FER#

HREQ

HIT

NC RS1# RS0#

HREQ

RDY#

HIT# GND

LOCK#

GND

MEM

VREF1

GND

MEM

VREF2

GND

MEM

VREF3

MEM

VREF4

CS 3#

WE#

DQS

DQM 7 MD

GND

M# D BSY#

GND NC GND

MEM

VREF0

GND

CKE 0 CKE 2 DQM 1 DQS

MA 9 MA 7 MD

MA 4 MA 6 MD

MA 2 MA 3 MD

GND

MA 1 MD

BA 0 BA 1 MA

GND

2# S CAS# S RAS#

GND

ADS# GND

RDY#

RS2# NC

BREQ

TEST

DFT

IN#

IN# M CLKI M CLKO

GNDA

V CCA 3

MCK

MD 4 MD

MD 6 MD 2 DQS

CKE 3 CKE 1 MD 3 MD

MD 9 MD

MA 5 MA 8 DQM 2 DQS

DQM

DQS

GND

DQM

GND

DQS

DQM

GND

DQS

GND

DQS

GND

DQM 5 MD

GND

DQM 6 MD

Revision 1.0, January 5, 2005 -9- Pin Diagrams

CN333 Data Sheet

Pin Lists

Table 2. Pin List (Listed by Pin Number)

Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin # Pin Name

A03 IO HD28# D03 IO HD27# J01 IO HD46# V05 O INTA# AE10 O FP1VS AH13 – NC A04 IO HD29# D06 IO HD33# J02 – NC V06 – NC AE11 O FPD10 AH14 IO VD08 A05 IO HD25# D07 IO HD21# J03 – NC V26 O MA04 AE12 O FPD20 AH15 IO VD05 A06 IO HD26# D08 IO HD30# J04 IO HD52# V27 O MA06 AE14 AI VLCOMPP AH16 IO VD00 A07 IO HD16# D09 IO HD14# J05 – NC V28 IO MD28 AE21 O AGPBUSY# AH17 I UPSTB+ A08 IO HD13# D10 IO HD18# J27 IO MD06 V29 IO MD24 AE27 IO MD40 AH18 IO VD02 A12 IO HD05# D12 IO HD09# J28 IO MD02 V30 IO MD23 AE28 IO MD44 AH19 IO VD06 A13 IO HD15# D13 IO HD00# J29 IO DQS0# W02 IO SPCLK2 AF01 O GDVP1DE AH20 IO VD11 A15 IO HA23# D15 IO HA20# J30 O DQM0 W03 – NC AF03 O GDVP1VS AH21 I RESET# A16 IO HA19# D16 O CPURST# K01 IO HD53# W04 – NC AF04 O GDVP1D00 AH22 IO MD59 A20 IO HA11# D18 IO HA12# K03 IO HD54# W05 – NC AF06 – NC AH23 O MA13 A21 IO BNR# D19 IO HA05# K04 IO HD58# W26 O MA02 AF07 O FPDE AH24 IO MD57 A22 – NC D20 IO HA06# K06 IO HD50# W27 O MA03 AF09 O FP1CLK# AH25 O CS1# A24 IO DEFER# D21 – NC K27 O CKE3 W28 IO MD29 AF10 I FP1DET AH26 O CS0# A25 IO HREQ0# D22 IO HA07# K28 O CKE1 W29 IO DQS3# AF12 O FPD07 AH27 IO MD54 A27 IO DRDY# D24 IO HREQ3# K29 IO MD03 W30 IO MD25 AF13 O FPD09 AH28 IO MD48 A28 IO ADS# D25 IO HTRDY# K30 IO MD07 Y02 – NC AF14 IO VPAR AH29 IO MD43 B02 IO HD34# D27 – NC L01 IO HD62# Y03 – NC AF15 IO VD04 AH30 IO MD47 B04 IO HD31# E01 – NC L02 IO HD56# Y04 – NC AF16 O DNSTB+ AJ01 O GDVP1CLK B06 IO HD24# E02 IO HD39# L03 IO HD61# Y05 – NC AF17 O DNSTB– AJ03 O GDVP1D09 B07 IO HD19# E03 IO HD36# L04 – NC Y25 O MA00 AF18 IO VD03 AJ04 I FPDET B11 IO HD10# E06 – NC L06 IO HD60# Y27 IO MD30 AF19 IO VD07 AJ06 O FPD14 B12 IO HD17# E07 IO HD23# L27 IO MD09 Y28 IO MD26 AF25 O SWE# AJ07 O FPVS B13 IO HD04# E09 IO HD02# L28 IO MD12 Y30 O DQM3 AF27 IO MD45 AJ09 O FPD21 B14 – NC E11 – NC L30 IO MD08 AA02 – NC AF28 IO MD41 AJ10 O FPD03 B15 IO HA30# E12 – NC M26 O CKE0 AA03 – NC AF30 IO DQS5# AJ12 O FPD05 B16 IO HA31# E13 IO HD01# M27 O CKE2 AA04 – NC AG01 O GDVP1HS AJ13 IO VD12 B17 IO HA15# E14 IO HA26# M28 O DQM1 AA05 – NC AG02 O GDVP1D02 AJ14 IO VD09 B21 IO HA04# E15 IO HA24# M29 IO DQS1# AA26 O MA01 AG03 O GDVP1D01 AJ17 I UPSTB– B22 – NC E16 IO HA21# M30 IO MD13 AA27 IO MD33 AG04 O GDVP1D05 AJ21 I SUSST# B23 IO BPRI# E17 IO HA28# N05 I HCLK+ AA28 IO MD32 AG05 – NC AJ22 IO MD63 B24 IO HREQ2# E18 IO HA16# N06 I HCLK– AA29 IO MD31 AG06 – NC AJ24 IO DQS7# B25 I HITM# E19 – NC N07 I TCLK AA30 IO MD27 AG07 O FPD17/ AJ25 IO MD60 B26 IO DBSY# E22 IO HA14# N27 O MA12 AB02 – NC AG08 O FP1DE AJ27 IO MD50 B27 IO RS2# E24 I HLOCK# N28 O MA11 AB03 – NC AG09 O FPD23/ AJ28 IO MD52 B28 – NC E25 IO HIT# N29 IO MD15 AB04 – NC AG10 O FPD22/ AJ30 IO MD49 C01 IO HD43# F01 IO HD42# N30 IO MD14 AB05 – NC AG11 O FPD11 AK01 O GDVP1D08 C02 IO HD38# F02 – NC P02 I DISPCLKI AB26 O BA0 AG12 O FP1CLK AK02 I GDVP1DET C03 IO HD22# F03 IO HD45# P03 O DISPCLKO AB27 O BA1 AG13 – NC AK03 O GDVP1D04 C04 – NC F04 IO HD44# P06 I GCLK AB28 O MA10 AG15 IO VD01 AK04 O FPD12 C05 IO HD32# F05 IO HD47# P07 I XIN AB29 IO MD37 AG16 IO VBE# AK05 O FPD15 C06 – NC F07 IO HD35# P27 IO MD20 AB30 IO MD36 AG18 O DNCMD AK06 O FPD16 C07 – NC F08 IO HD07# P28 IO MD11 AC01 – NC AG19 I UPCMD AK07 O FPD19 C08 IO HD20# F09 IO HD03# P30 IO MD10 AC03 – NC AG20 IO VD14 AK08 – NC C09 IO HD11# F13 AI HRCOMP R26 O MA09 AC04 – NC AG21 I PWROK AK09 O FPD00 C10 IO HD12# F14 IO HA18# R27 O MA07 AC27 IO MD34 AG23 O CS3# AK10 O FP1HS C11 – NC F15 IO HA17# R28 IO MD21 AC28 O DQM4 AG24 IO MD61 AK11 O FPD04 C12 IO HD08# F16 IO HA25# R29 IO MD17 AC30 IO DQS4# AG25 O CS2# AK12 O FPD08 C13 IO HD06# F27 I TESTIN# R30 IO MD16 AD01 – NC AG26 O SCAS# AK13 IO VD13 C14 IO HA29# F28 I DFTIN# T01 AO AB AD02 – NC AG27 O SRAS# AK20 IO VD10 C15 IO HA27# F29 I MCLKI T02 AO AG AD03 IO SBDDCDAT AG28 IO MD46 AK21 IO VD15 C16 IO HA22# F30 O MCLKO T03 AO AR AD04 IO SBDDCCLK AG29 O DQM5 AK22 IO MD58 C17 IO HA10# G01 IO HD51# T27 O MA05 AD05 O ENAVEE AG30 IO MD42 AK23 IO MD62 C18 IO HA13# G03 IO HD49# T28 O MA08 AD27 IO MD35 AH01 O GDVP1D03 AK24 O DQM7 C19 IO HA03# G04 IO HD41# T29 O DQM2 AD28 IO MD39 AH02 O GDVP1CLK# AK25 IO MD56 C20 IO HA09# G30 IO MD00 T30 IO DQS2# AD29 IO MD38 AH03 O GDVP1D06 AK26 IO MD51 C21 IO HA08# H01 IO HD63# U06 – NC AE01 AI AGPPCMP AH04 O GDVP1D07 AK27 IO MD55 C22 IO HREQ1# H02 IO HD57# U07 – NC AE02 AI AGPNCMP AH05 O GDVP1D10 AK28 IO DQS6# C23 IO HREQ4# H03 IO HD55# U27 IO MD19 AE03 O FPCLK# AH06 O GDVP1D11 AK29 O DQM6 C24 – NC H04 IO HD59# U28 IO MD22 AE04 O ENAVDD AH07 O FPD18 AK30 IO MD53 C25 IO RS1# H05 IO HD48# U30 IO MD18 AE05 O ENABLT AH08 IO SBPLCLK C26 IO RS0# H06 IO HD40# V01 O HSYNC AE06 – NC AH09 IO SBPLDAT C27 O BREQ0# H27 IO MD04 V02 O VSYNC AE07 O FPCLK AH10 O FPD01 C28 – NC H28 IO MD05 V03 IO SPDAT2 AE08 O FPD13 AH11 O FPD02 D01 IO HD37# H30 IO MD01 V04 AI RSET AE09 O FPHS AH12 O FPD06

Revision 1.0, January 5, 2005 -10- Pin Lists

CN333 Data Sheet

Table 3. Pin List (Listed by Pin Name)

Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin # Pin Name

T01 AO AB AK12 O FPD08 C14 IO HA29# L06 IO HD60# AA27 IO MD33 AA04 – NC A28 IO ADS# AF13 O FPD09 B15 IO HA30# L03 IO HD61# AC27 IO MD34 AA05 – NC

T02 AO AG AE11 O FPD10 B16 IO HA31# L01 IO HD62# AD27 IO MD35 AB04 – NC AE21 O AGPBUSY# AG11 O FPD11 N05 I HCLK+ H01 IO HD63# AB30 IO MD36 AB05 – NC AE02 AI AGPCOMPN AK04 O FPD12 N06 I HCLK– E25 IO HIT# AB29 IO MD37 AC01 – NC AE01 AI AGPCOMPP AE08 O FPD13 D13 IO HD00# B25 I HITM# AD29 IO MD38 AC03 – NC

T03 AO AR AJ06 O FPD14 E13 IO HD01# E24 I HLOCK# AD28 IO MD39 AC04 – NC AB26 O BA0 AK05 O FPD15 E09 IO HD02# F13 AI HRCOMP AE27 IO MD40 AD01 – NC AB27 O BA1 AK06 O FPD16 F09 IO

A21 IO BNR# AG07 O FPD17 B13 IO HD04# C22 IO HREQ1# AG30 IO MD42 AE06 – NC

B23 IO BPRI# AH07 O FPD18 A12 IO HD05# B24 IO HREQ2# AH29 IO MD43 AF06 – NC

C27 O BREQ0# AK07 O FPD19 C13 IO HD06# D24 IO HREQ3# AE28 IO MD44 AG05 – NC

M26 O CKE0 AE12 O FPD20 F08 IO HD07# C23 IO HREQ4# AF27 IO MD45 AG06 – NC

K28 O CKE1 AJ09 O FPD21 C12 IO HD08# V01 O HSYNC AG28 IO MD46 AG13 – NC

M27 O CKE2 AG10 O FPD22 D12 IO HD09# D25 IO HTRDY# AH30 IO MD47 AH13 – NC

K27 O CKE3 AG09 O FPD23 B11 IO HD10# V05 O INTA# AH28 IO MD48 AK08 – NC

D16 O CPURST# AF07 O FPDE C09 IO HD11# Y25 O MA00 AJ30 IO MD49 AG21 I PWROK

AH26 O CS0# AJ04 I FPDET C10 IO HD12# AA26 O MA01 AJ27 IO MD50 AH21 I RESET# AH25 O CS1# AE09 O FPHS A08 IO HD13# W26 O MA02 AK26 IO MD51 C26 IO RS0# AG25 O CS2# AJ07 O FPVS D09 IO HD14# W27 O MA03 AJ28 IO MD52 C25 IO RS1# AG23 O CS3# P06 I GCLK A13 IO HD15# V26 O MA04 AK30 IO MD53 B27 IO RS2#

B26 IO DBSY# AJ01 O GDVP1CLK A07 IO HD16# T27 O MA05 AH27 IO MD54 V04 AI RSET

A24 IO DEFER# AH02 O GDVP1CLK# B12 IO HD17# V27 O MA06 AK27 IO MD55 AD03 IO SBDDCDAT

F28 I DFTIN# AF04 O GDVP1D00 D10 IO HD18# R27 O MA07 AK25 IO MD56 AD04 IO SBDDCCLK P02 I DISPCLKI AG03 O GDVP1D01 B07 IO HD19# T28 O MA08 AH24 IO MD57 AH08 IO SBPLCLK

P03 O DISPCLKO AG02 O GDVP1D02 C08 IO HD20# R26 O MA09 AK22 IO MD58 AH09 IO SBPLDAT AG18 O DNCMD AH01 O GDVP1D03 D07 IO HD21# AB28 O MA10 AH22 IO MD59 AG26 O SCAS# AF16 O DNSTB+ AK03 O GDVP1D04 C03 IO HD22# N28 O MA11 AJ25 IO MD60 AB02 – NC AF17 O DNSTB– AG04 O GDVP1D05 E07 IO HD23# N27 O MA12 AG24 IO MD61 W02 IO SPCLK2

J30 O DQM0 AH03 O GDVP1D06 B06 IO HD24# AH23 O MA13 AK23 IO MD62 AB03 – NC

M28 O DQM1 AH04 O GDVP1D07 A05 IO HD25# F29 I MCLKI AJ22 IO MD63 V03 IO SPDAT2

T29 O DQM2 AK01 O GDVP1D08 A06 IO HD26# F30 O MCLKO A22 – NC AG27 O SRAS#

Y30 O DQM3 AJ03 O GDVP1D09 D03 IO HD27# G30 IO MD00 B14 – NC AJ21 I SUSST# AC28 O DQM4 AH05 O GDVP1D10 A03 IO HD28# H30 IO MD01 B22 – NC AF25 O SWE# AG29 O DQM5 AH06 O GDVP1D11 A04 IO HD29# J28 IO MD02 B28 – NC N07 I TCLK AK29 O DQM6 AF01 O GDVP1DE D08 IO HD30# K29 IO MD03 C04 – NC F27 I TESTIN# AK24 O DQM7 AK02 I GDVP1DET B04 IO HD31# H27 IO MD04 C06 – NC AG19 I UPCMD

J29 IO DQS0# AG01 O GDVP1HS C05 IO HD32# H28 IO MD05 C07 – NC AH17 I UPSTB+

M29 IO DQS1# AF03 O GDVP1VS D06 IO HD33# J27 IO MD06 C11 – NC AJ17 I UPSTB–

T30 IO DQS2# C19 IO HA03# B02 IO HD34# K30 IO MD07 C24 – NC AG16 IO VBE#

W29 IO DQS3# B21 IO HA04# F07 IO HD35# L30 IO MD08 C28 – NC AH16 IO VD00 AC30 IO DQS4# D19 IO HA05# E03 IO HD36# L27 IO MD09 D21 – NC AG15 IO VD01 AF30 IO DQS5# D20 IO HA06# D01 IO HD37# P30 IO MD10 D27 – NC AH18 IO VD02 AK28 IO DQS6# D22 IO HA07# C02 IO HD38# P28 IO MD11 E01 – NC AF18 IO VD03

AJ24 IO DQS7# C21 IO HA08# E02 IO HD39# L28 IO MD12 E06 – NC AF15 IO VD04

A27 IO DRDY# C20 IO HA09# H06 IO HD40# M30 IO MD13 E11 – NC AH15 IO VD05 AE05 O ENABLT C17 IO HA10# G04 IO HD41# N30 IO MD14 E12 – NC AH19 IO VD06 AE04 O ENAVDD A20 IO HA11# F01 IO HD42# N29 IO MD15 E19 – NC AF19 IO VD07 AD05 O ENAVEE D18 IO HA12# C01 IO HD43# R30 IO MD16 F02 – NC AH14 IO VD08 AG12 O FP1CLK C18 IO HA13# F04 IO HD44# R29 IO MD17 J02 – NC AJ14 IO VD09 AF09 O FP1CLK# E22 IO HA14# F03 IO HD45# U30 IO MD18 J03 – NC AK20 IO VD10 AG08 O FP1DE B17 IO HA15# J01 IO HD46# U27 IO MD19 J05 – NC AH20 IO VD11 AF10 I FP1DET E18 IO HA16# F05 IO HD47# P27 IO MD20 L04 – NC AJ13 IO VD12 AK10 O FP1HS F15 IO HA17# H05 IO HD48# R28 IO MD21 U06 – NC AK13 IO VD13 AE10 O FP1VS F14 IO HA18# G03 IO HD49# U28 IO MD22 U07 – NC AG20 IO VD14 AE07 O FPCLK A16 IO HA19# K06 IO HD50# V30 IO MD23 V06 – NC AK21 IO VD15 AE03 O FPCLK# D15 IO HA20# G01 IO HD51# V29 IO MD24 W03 – NC AE14 AI VLCOMPP AK09 O FPD00 E16 IO HA21# J04 IO HD52# W30 IO MD25 W04 – NC AF14 IO VPAR AH10 O FPD01 C16 IO HA22# K01 IO HD53# Y28 IO MD26 W05 – NC V02 O VSYNC AH11 O FPD02 A15 IO HA23# K03 IO HD54# AA30 IO MD27 Y02 – NC P07 I XIN

AJ10 O FPD03 E15 IO HA24# H03 IO HD55# V28 IO MD28 Y03 – NC

AK11 O FPD04 F16 IO HA25# L02 IO HD56# W28 IO MD29 Y04 – NC

AJ12 O FPD05 E14 IO HA26# H02 IO HD57# Y27 IO MD30 Y05 – NC AH12 O FPD06 C15 IO HA27# K04 IO HD58# AA29 IO MD31 AA02 – NC AF12 O FPD07 E17 IO HA28# H04 IO HD59# AA28 IO MD32 AA03 – NC

HD03#

A25 IO HREQ0# AF28 IO MD41 AD02 – NC

Revision 1.0, January 5, 2005 -11- Pin Lists

CN333 Data Sheet

Table 4. Power, Ground and Voltage Reference Pin List

Outer Ring Pins (Intermixed with Signal Pins) AGPVREF[0:1] (2 pins): AE13, AD6 GTLVREF (1 pin): G15 HAVREF[0:1] (2 pins): F18,20 HDVREF[0:3] (4 pins): G10,13, K7, J7 HCOMPVREF (1 pin): G14 MEMVREF[0:5] (6 pins): H26, L25, R25, W25, AC25, AE22 VLVREF (1 pin): AE15

VCCA33HCK1 (1 pin): M1 GNDAHCK1 (1 pin): M2

VCCA33HCK2 (1 pin): M4 GNDAHCK2 (1 pin): M5

VCCA33GCK (1 pin): M3 GNDAGCK (1 pin): M6

VCCA33MCK (1 pin): G28 GNDAMCK (1 pin): G27

VCCA15PLL1 (1 pin): N3 GNDAPLL1 (1 pin): N4

VCCA15PLL2 (1 pin): P4 GNDAPLL2 (1 pin): P5

VCCA15PLL3 (1 pin): N1 GNDAPLL3 (1 pin): N2

VCCA33DAC[1:2] (2 pins): R4, U4 GNDADAC[1:3] (3 pins): R5, T4, U5

VSUS15 (1 pin): AF21

GND (63 pins): A11,14,17,23,26,29, B3,5,8,20, D2,5,11,14,17,23,26,29, E8,20,30, F17, G2,5,8,16,29, H29, J26, K2,5, L26,29, P26,29, U26,29, Y26,29,

AC2,5,26, 29, AF2,5,8,11,20,23,26,29, AG14,17, AJ2,5,8,11,20,23,26,29, AK14,17

Center Pins VCC15 (51 pins): J9-22, K9,22, L9,22, M9,22, N9,22, P9,22, R9,22, T9,22, U9,22, V9,22, W9,22, Y9,22, AA9,22, AB9-21

VCC25MEM (20 pins): K18-21, L21, M21, N21, P21, R21, T21, U21, V21, W21, Y21, AA16-21

VCC15AGP (7 pins): V10, W10, Y10, AA10-13

VCC15VL (2 pins): AA14-15

VCC33GFX (3 pins): R10, T10, U10

VTT (12 pins): K10-17, L10, M10, N10, P10

GND (101 pins): L11-20, M11-20, N11-20, P11-20, R11-20, T11-20, U11-20, V11-20, W11-20, Y11-20

Revision 1.0, January 5, 2005 -12- Pin Lists

CN333 Data Sheet

Pin Descriptions

CPU Interface Pin Descriptions

CPU Interface

Signal Name Pin # I/O Signal Description

HA[31:3]#

HD[63:0]# ADS# BNR#

BPRI#

DBSY#

DEFER#

DRDY# HIT#

HITM#

HLOCK#

HREQ[4:0]#

HTRDY#

RS[2:0]#

CPURST#

BREQ0#

Note: Clocking of the CPU interface is performed with HCLK+ and HCLK–. Note: Internal pullup resistors are provided on all GTL interface pins. If the CPU does not have internal pullups, the North

Bridge internal pullups may be enabled to allow the interface to meet GTL bus interface specifications (see strap descriptions).

Note: I/O pads for the above pins are powered by VTT. Input voltage levels are referenced to HAVREF, HDVREF and

GTLREF.

(see pin list) IO Host Address Bus. HA[31:3] connect to the address bus of the host CPU. During

CPU cycles HA[31:3] are inputs. These signals are driven by the North Bridge during cache snooping operations.

(see pin list) IO Host CPU Data. These signals are connected to the CPU data bus.

A28 IO Address Strobe. The CPU asserts ADS# in T1 of the CPU bus cycle. A21 IO Block Next Request. Used to block the current request bus owner from issuing new

requests. This signal is used to dynamically control the processor bus pipeline depth.

B23 IO Priority Agent Bus Request. The owner of this signal will always be the next bus

owner. This signal has priority over symmetric bus requests and causes the current symmetric owner to stop issuing new transactions unless the HLOCK# signal is asserted. The North Bridge drives this signal to gain control of the processor bus.

B26 IO Data Bus Busy. Used by the data bus owner to hold the data bus for transfers requiring

more than one cycle.

A24 IO Defer. A dynamic deferring policy is used to optimize system performance. The

DEFER# signal is also used to indicate a processor retry response. A27 IO Data Ready. Asserted for each cycle that data is transferred. E25 IO Hit. Indicates that a caching agent holds an unmodified version of the requested line.

Also driven in conjunction with HITM# by the target to extend the snoop window. B25 I Hit Modified. Asserted by the CPU to indicate that the address presented with the last

assertion of EADS# is modified in the L1 cache and needs to be written back. E24 I Host Lock. All CPU cycles sampled with the assertion of HLOCK# and ADS# until

the negation of HLOCK# must be atomic.

C23, D24, B24,

C22, A25

D25 IO Host Target Ready. Indicates that the target of the processor transaction is able to

B27, C25, C26 IO Response Signals. Indicates the type of response per the table below:

D16 O CPU Reset. Reset output to CPU. External pullup and filter capacitor to ground

C27 O Bus Request 0. Connect to CPU bus request 0.

IO Request Command. Asserted during both clocks of the request phase. In the first

clock, the signals define the transaction type to a level of detail that is sufficient to

begin a snoop request. In the second clock, the signals carry additional information to

define the complete transaction type.

enter the data transfer phase.

RS[2:0]# Response type

000 Idle State

001 Retry Response

010 Defer Response

011 Reserved

100 Hard Failure

101 Normal Without Data

110 Implicit Writeback

111 Normal With Data

should be provided per CPU manufacturer’s recommendations.

Revision 1.0, January 5, 2005 -13- Pin Descriptions

CN333 Data Sheet

The pinouts were defined assuming the ATX PCB layout model shown below (and general pin layout shown) as a guide for PCB component placement. Other PCB layouts (AT, LPX and NLX) were also considered and can typically follow the same general component placement.

PCI Slots

VT8237R

V-Link

South

Bridge

VIA C3

CPU

1 … 36

CPU

GFX

AGP

CN 333

SDRAM

…

DDR

SDRAM

Modules

IDE Connectors

Power

Supply

DDR SDRAM Memory Controller Pin Descriptions

DDR DRAM Interface

Signal Name Pin # I/O Signal Description

MA[13:0]

BA[1:0]

SRAS#, SCAS#, SWE# AG27, AG26, AF25 O

MD[63:0]

DQM[7:0]

DQS[7:0]# AJ24, AK28, AF30,

CS[3:0]#

CKE[3:0]

Note: I/O pads for all pins on this page are powered by VCC25MEM. MD / DQS input voltage levels are referenced to

MEMVREF.

(see pin lists) O Memory Address. Output drive strength may be set by Device 0

Function 3 RxE8.

AB27, AB26 O Bank Address. Output drive strength may be set by Device 0 Function

3 RxE8.

Row Address, Column Address and Write Enable Command Indicators. Output drive strength may be set by Device 0 Function 3

Rx E8.

(see pin lists) IO Memory Data. These signals are connected to the DRAM data bus.

Output drive strength may be set by Device 0 Function 3 RxE2.

AK24, AK29,

AG29, AC28, Y30,

O Data Mask. Data mask of each byte lane. Output drive strength may

be set by Device 0 Function 3 RxE2.

T29, M28, J30

IO DDR Data Strobe. Data strobe of each byte lane. Output drive

AC30, W29, T30,

strength may be set by Device 0 Function 3 RxE0.

M29, J29

AG23, AG25,

AH25, AH26

K27, M27, K28,

M26

O Chip Select. Chip select of each bank. Output drive strength may be

set by Device 0 Function 3 RxE4.

O Clock Enables. Clock enables for each DRAM bank for powering

down the SDRAM or clock control for reducing power usage and for reducing heat / temperature in high-speed memory systems.

Revision 1.0, January 5, 2005 -14- Pin Descriptions

CN333 Data Sheet

Ultra V-Link Pin Descriptions

Ultra V-Link Interface

Signal Name Pin # I/O Signal Description

V-Link Data Bus. During system initialization, VD[7:0] are used to

VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8 VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 VPAR VBE#

UPCMD

UPSTB+ UPSTB– DNCMD

DNSTB+ DNSTB–

Note: I/O pads for the pins in the above table are powered by VCC15VL. Input voltage levels are referenced to VLVREF.

AK21 AG20 AK13

AJ13 AH20 AK20

AJ14 AH14

AF19 AH19 AH15

AF15

AF18 AH18 AG15 AH16

AF14 IO AG16 IO AG19 I

AH17 I

AJ17 I

AG18 O

AF16 O

AF17 O

transmit strap information from the South Bridge (the straps are not on

the VD pins but are on the indicated pins of the South Bridge chip).

Check the strap pin table for details.

IO IO IO IO IO IO IO IO IO IO IO IO IO

V-Link Parity. V-Link Byte Enable. V-Link Command from Client (South Bridge) to Host (North Bridge). V-Link Strobe from Client to Host. V-Link Complement Strobe from Client to Host. V-Link Command from Host (North Bridge) to Client (South Bridge). V-Link Strobe from Host to Client. V-Link Complement Strobe from Host to Client.

Revision 1.0, January 5, 2005 -15- Pin Descriptions

CN333 Data Sheet

CRT and Serial Bus Pin Descriptions

CRT Interface

Signal Name Pin # I/O Signal Description AR AG AB HSYNC VSYNC RSET

I/O pads for the pins in the above table are powered by VCC33GFX (i.e., 3.3V I/O).

T3 AO Analog Red. Analog red output to the CRT monitor. T2 AO Analog Green. Analog green output to the CRT monitor. T1 AO Analog Blue. Analog blue output to the CRT monitor. V1 O Horizontal Sync. Output to CRT. V2 O Vertical Sync. Output to CRT. V4 AI Reference Resistor. Tie to GNDDAC through an external

82Ω 1% resistor to control the RAMDAC full-scale current value.

SMB / I2C Interface

Signal Name Pin # I/O Signal Description SBPLCLK SBPLDAT SBDDCCLK SBDDCDAT SPCLK2

SPCLK1 / CAPD12

SPDAT2, SPDAT1 / CAPD13

I/O pads for SPCLK[2:1] / SPDAT[2:1] above are powered by VCC33GFX (i.e., 3.3V I/O). All other pins in the above table are powered by VCC15AGP (i.e., 1.5V I/O).

AH8 IO AH9 IO AD4 IO AD3 IO

W2, AB2

V3, AB3

IO Serial Port (SMB/I2C) Clock and Data. The SPCLKn pins are the

I2C Serial Bus Clock for Panel I2C Serial Bus Data for Panel I2C Serial Bus Clock for CRT DDC I2C Serial Bus Data for CRT DDC

clocks for serial data transfer. The SPDATn pins are the data signals used for serial data transfer. SPxxx1 is typically used for DVI monitor communications and SPxxx2 is typically used for DDC for CRT monitor communications. These pins are programmed via “Sequencer” graphics registers (port 3C5) in the “Extended” VGA register space (see the UniChrome-II Graphics Registers document for additional details). The SPxxx1 registers are programmed via 3C5.31 (“IIC Serial Port Control 1”) and the SPxxx2 registers are programmed via 3C5.26 (“IIC Serial Port Control 0”). In both registers, the clock out state is programmed via bit-5 and the data out state via bit-4, clock in status may be read in bit-3 and data in status in bit-2 and the port may be enabled via bit-0.

Revision 1.0, January 5, 2005 -16- Pin Descriptions

CN333 Data Sheet

Flat Panel Display Port (FPDP) Pin Descriptions

The FPDP can be configured as either an LVDS transmitter interface port (see the LVDS Transmitter Interface)

24-Bit / Dual 12-Bit Flat Panel Display Interface

Signal Name Pin # I/O Signal Description FPD23 / FPD0D11

FPD22 / FPD0D10 FPD21 / FPD0D09 FPD20 / FPD0D08 FPD19 / FPD0D07 FPD18 / FPD0D06 FPD17 / FPD0D05 FPD16 / FPD0D04 FPD15 / FPD0D03 FPD14 / FPD0D02 FPD13 / FPD0D01 FPD12 / FPD0D00 FPD11 / FPD1D11 FPD10 / FPD1D10 FPD09 / FPD1D09 FPD08 / FPD1D08 FPD07 / FPD1D07 FPD06 / FPD1D06 FPD05 / FPD1D05 FPD04 / FPD1D04 FPD03 / FPD1D03 FPD02 / FPD1D02 FPD01 / FPD1D01 FPD00 / FPD1D00

FPHS FPVS FPDE FPDET FPCLK FPCLK# AE3 O Flat Panel Clock Complement. 24-bit mode or port 0 in dual 12-bit

FP1HS FP1VS FP1DE FP1DET FP1CLK FP1CLK#

AG9

AG10

AJ9

AE12

AK7 AH7 AG7 AK6 AK5

AJ6

AE8

AK4, AG11 AE11

AF13 AK12

AF12 AH12

AJ12

AK11

AJ10 AH11 AH10

AK9 AE9 O Flat Panel Horizontal Sync. 24-bit mode or port 0 in dual 12-bit mode.

AJ7 O Flat Panel Vertical Sync. 24-bit mode or port 0 in dual 12-bit mode.

AF7 O Flat Panel Data Enable. 24-bit mode or port 0 in dual 12-bit mode.

AJ4 I Flat Panel Detect. 24-bit mode or port 0 in dual 12-bit mode.

AE7 O Flat Panel Clock. 24-bit mode or port 0 in dual 12-bit mode.

AK10 O Flat Panel Horizontal Sync. For port 1 in dual 12-bit mode. AE10 O Flat Panel Vertical Sync. For port 1 in dual 12-bit mode.

AG8 O Flat Panel Data Enable. For port 1 in dual 12-bit mode.

AF10 I Flat Panel Detect. For port 1 in dual 12-bit mode.

AG12 O Flat Panel Clock. For port 1 in dual 12-bit mode.

AF9 O Flat Panel Clock Complement. For port 1 in dual 12-bit mode. For

O Flat Panel Data. For 24-bit or dual 12-bit flat panel display modes.

Two FPD interface modes, 24-bit and dual 12-bit, are supported.

Strap High (3C5.12[4]=1): 24-bit Strap Low (3C5.12[4]=0): Dual 12-bit

In “24-bit” mode, only one set of control pins is required. However, in dual 12-bit mode, the CN333 provides two sets of control signals that are required for certain LVDS transmitter chips.

In 24-bit mode, two operating modes are supported:

3C5.12[4]=1 & 3x5.88[2]=0 & 3x5.88[4]=0 Double data rate: each rising and falling clock edge transmits a complete 24-bit pixel.

3C5.12[4]=1 & 3x5.88[2]=0 & 3x5.88[4]=1 Single data rate: each clock rising edge transmits a complete 24-bit pixel.

In dual 12-bit mode,

3C5.12[4]=0 & 3x5.88[2] = 1 Double data rate: Each rising and falling clock edge transmits half (12 bits) of two 24-bit pixels.

mode. For double-data-rate data transfers.

double-data-rate data transfers.

Flat Panel Power Control

Signal Name Pin # I/O Signal Description ENAVDD ENAVEE ENABLT

Note: I/O pads for all pins on this page are powered by VCC15AGP (i.e., 1.5V I/O).

Revision 1.0, January 5, 2005 -17- Pin Descriptions

AE4 IO AD5 IO AE5 IO

Enable Panel VDD Power. Enable Panel VEE Power. Enable Panel Back Light.

CN333 Data Sheet

Digital Video Port 1 (GDVP1) Pin Descriptions

GDVP1 can be configured as either a DVI transmitter interface port (see the DVI Transmitter Interface pin lists below for details).

Digital Video Port 1 (GDVP1) – DVI Interface

Signal Name Pin # I/O Signal Description GDVP1D11

GDVP1D10 GDVP1D9 GDVP1D8 GDVP1D7 GDVP1D6 GDVP1D5 GDVP1D4 GDVP1D3 GDVP1D2 GDVP1D1 GDVP1D0

GDVP1HS GDVP1VS GDVP1DE GDVP1DET

GDVP1CLK GDVP1CLK#

AH6 AH5

AJ3 AK1 AH4 AH3 AG4 AK3 AH1 AG2 AG3

AF4

AG1 O

AF3 O AF1 O

AK2 I Display Detect. If VGA register 3C5.3E[0] = 1, 3C5.1A[4] will read 1

AJ1 O AH2 O

I/O pads for the pins on this page are powered by VCC15AGP (1.5V I/O).

Data.

Horizontal Sync. Vertical Sync. Data Enable.

if a display is connected. Tie to GND if not used.

Clock. Clock Complement.

Revision 1.0, January 5, 2005 -18- Pin Descriptions

+ 55 hidden pages

Via CN333 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual