Via CLE266 User Manual

Data Sheet

CLE266

Version CD/CE

North Bridge

Revision 2.06
December 1, 2004

VIA TECHNOLOGIES, INC.

Copyright Notice:

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Graphics Incorporated reserves the right to make changes in the product design without reservation and without notice to its users.

Trademark Notices:

VT8233A and CLE266 may only be used to identify products of VIA Technologies

C3™ is a registered trademark of VIA Technologies.
Windows XP™, Windows 2000™, Windows ME™, Windows 98™ and Plug and Play™ are registered trademarks of Microsoft Corporation.
PCI™ is a registered trademark of the PCI Special Interest Group.
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All trademarks are the properties of their respective owners.

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th

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CLE266 Version CD / CE Desktop North Bridge Data Sheet

REVISION HISTORY

Document Release Date Revision Initials

1.0 1/14/03 Initial public release, same as internal revision 0.92 with confidential watermark removed DH

1.01 4/8/03 Updated Table 1 in Overview to indicate correct CRT screen resolutions supported
Updated mechanical specs to fix incorrect JEDEC-spec reference

1.1 4/25/03 Changed chipset name to north bridge chip name and removed VT#
Changed incorrect figure captions to table captions

1.2 5/29/03 Added “Version CD” to cover page
Fixed supported screen and LCD resolutions (1400x1050 max)

2.0 5/29/03 Changed “Version CD” to “Version CD / CE” DH

2.01 7/1/03 Removed 8MB Frame Buffer support
Fixed internal AGP speed & resolutions supported in graphics feature bullets & overview
Removed CPU/DRAM 133/100 freq support; added “Version CD/CE” to page header

2.02 7/17/03 Added 8MB Frame Buffer support information in product features, Table 1 (supported

CRT screen resolutions) and register setting of Device 0 RxE1[6:4]

Fixed typo of VCC25 information in notes of the pin list

2.03 3/22/04 Updated cover page, legal page and header
Updated the RSET resistor value in pin description table
Capitalized north bridge and south bridge
Modified the name of table 2 and table 3
Modified legend in mechanical specification

2.04 4/19/04 Added mechanical specifications for lead-free concern EY

2.05 8/11/04 Updated mechanical specification figure SV

2.06 12/1/04 Updated top marking in mechanical specificaiton VL

DH

DH

DH

DH

AL

SV

Revision 2.06, December 1, 2004 -i- Revision History

CLE266 Version CD / CE Desktop North Bridge Data Sheet

TABLE OF CONTENTS

REVISION HISTORY .......................................................................................................................................................................I

TABLE OF CONTENTS.................................................................................................................................................................. II

LIST OF FIGURES .........................................................................................................................................................................IV

LIST OF TABLES ...........................................................................................................................................................................IV

PRODUCT FEATURES.................................................................................................................................................................... 1

CLE266 SYSTEM OVERVIEW ...................................................................................................................................................... 5

CLE266 VERSION CD / CE OVERVIEW....................................................................................................................................... 5

SYSTEM POWER MANAGEMENT ................................................................................................................................................... 6

HIGH-PERFORMANCE 3D ACCELERATOR.................................................................................................................................... 6

128-BIT 2D GRAPHICS ENGINE ..................................................................................................................................................... 6

DVD PLAYBACK AND VIDEO CONFERENCING ............................................................................................................................. 6

TV DISPLAY OUTPUT SUPPORT .................................................................................................................................................... 7

VIDEO CAPTURE INTERFACE ........................................................................................................................................................ 7

LCD, FLAT PANEL MONITOR AND TV OUTPUT DISPLAY SUPPORT........................................................................................... 7

HIGH SCREEN RESOLUTION CRT SUPPORT ................................................................................................................................7

PINOUTS............................................................................................................................................................................................ 8

PIN DESCRIPTIONS....................................................................................................................................................................... 11

REGISTERS..................................................................................................................................................................................... 19

REGISTER OVERVIEW ................................................................................................................................................................. 19

MISCELLANEOUS I/O................................................................................................................................................................... 30

PCI CONFIGURATION SPACE I/O ............................................................................................................................................... 30

DEVICE 0 REGISTER DESCRIPTIONS........................................................................................................................................... 31

Device 0 Host Bridge Header Registers .............................................................................................................................. 31

Device 0 Host Bridge Device-Specific Registers................................................................................................................. 33

V-Link Control...................................................................................................................................................................................... 33

Host CPU Control .................................................................................................................................................................................36

DRAM Control...................................................................................................................................................................................... 37

PCI Bus Control ....................................................................................................................................................................................43

GART / Graphics Aperture Control ......................................................................................................................................................45

AGP Control.......................................................................................................................................................................................... 46

V-Link Control...................................................................................................................................................................................... 48

Power Management............................................................................................................................................................................... 49

Frame Buffer and High Memory Control.............................................................................................................................................. 50

BIOS Scratch......................................................................................................................................................................................... 50

DEVICE 1 REGISTER DESCRIPTIONS........................................................................................................................................... 51

Device 1 PCI-to-PCI Bridge Header Registers .................................................................................................................. 51

Device 1 PCI-to-PCI Bridge Device-Specific Registers ..................................................................................................... 53

Internal AGP Bus Control ..................................................................................................................................................................... 53

Power Management............................................................................................................................................................................... 55

Revision 2.06, December 1, 2004 -ii- Table of Contents

CLE266 Version CD / CE Desktop North Bridge Data Sheet

FUNCTIONAL DESCRIPTION.................................................................................................................................................... 56

INTEGRATED GRAPHICS CONTROLLER ...................................................................................................................................... 56

Internal Architecture ........................................................................................................................................................... 56

GRAPHICS MODES ....................................................................................................................................................................... 57

Desktop Modes - Single Display .......................................................................................................................................... 57

Desktop Modes - LCD VGA 640x480 Multiple Display .................................................................................................... 58

Desktop Modes - LCD SVGA 800x600 Multiple Display.................................................................................................. 59

Desktop Modes - LCD XGA 1024x768 Multiple Display.................................................................................................. 60

Desktop Modes - LCD SXGA 1280x1024 Multiple Display.............................................................................................. 61

Desktop Modes - LCD SXGA+ 1400x1050 Multiple Display............................................................................................ 62

Graphics Modes That Allow LCD Centering and Expansion .......................................................................................... 63

VGA Graphics Modes .......................................................................................................................................................... 64

Direct Draw Graphics Modes .............................................................................................................................................. 65

Graphics Modes for TV Display.......................................................................................................................................... 66

Additional Graphics Modes for IA Devices........................................................................................................................ 67

FLAT PANEL DISPLAY RGB MAPPING ....................................................................................................................................... 68

ELECTRICAL SPECIFICATIONS .............................................................................................................................................. 69

ABSOLUTE MAXIMUM RATINGS ................................................................................................................................................. 69

DC CHARACTERISTICS................................................................................................................................................................ 69

AC TIMING SPECIFICATIONS...................................................................................................................................................... 69

MECHANICAL SPECIFICATIONS............................................................................................................................................. 70

Revision 2.06, December 1, 2004 -iii- Table of Contents

CLE266 Version CD / CE Desktop North Bridge Data Sheet

LIST OF FIGURES

FIGURE 1. SYSTEM BLOCK DIAGRAM.................................................................................................................................... 5

FIGURE 2. BALL DIAGRAM (TOP VIEW)................................................................................................................................. 8

FIGURE 3. GRAPHICS APERTURE ADDRESS TRANSLATION......................................................................................... 45

FIGURE 4. GRAPHICS CONTROLLER INTERNAL BLOCK DIAGRAM.......................................................................... 56

FIGURE 5. MECHANICAL SPECIFICATIONS – 548-PIN 27X27MM BALL GRID ARRAY PACKAGE WITH 1MM

BALL PITCH.............................................................................................................................................................. 70

FIGURE 6. LEAD-FREE MECHANICAL SPECIFICATIONS – 548-PIN 27X27MM BALL GRID ARRAY PACKAGE

WITH 1MM BALL PITCH ........................................................................................................................................ 71

LIST OF TABLES

TABLE 1. SUPPORTED CRT SCREEN RESOLUTIONS.......................................................................................................... 7

TABLE 2. PIN LIST (LISTED BY PIN NUMBER)...................................................................................................................... 9

TABLE 3. PIN LIST (LISTED BY PIN NAME) ......................................................................................................................... 10

TABLE 4. PIN DESCRIPTIONS .................................................................................................................................................. 11

TABLE 5. REGISTERS ................................................................................................................................................................. 19

TABLE 6. SYSTEM MEMORY MAP.......................................................................................................................................... 37

TABLE 7. MA MAP TYPE ENCODING..................................................................................................................................... 38

TABLE 8. MEMORY ADDRESS MAPPING TABLE ............................................................................................................... 38

TABLE 9. VGA / MDA MEMORY / IO REDIRECTION ......................................................................................................... 53

TABLE 10. DESKTOP GRAPHICS MODES – SINGLE DISPLAY ........................................................................................ 57

TABLE 11. DESKTOP GRAPHICS MODES – LCD VGA 640X480 MULTIPLE DISPLAY............................................... 58

TABLE 12. DESKTOP GRAPHICS MODES – LCD SVGA 800X600 MULTIPLE DISPLAY............................................. 59

TABLE 13. DESKTOP GRAPHICS MODES – LCD XGA 1024X768 MULTIPLE DISPLAY............................................. 60

TABLE 14. DESKTOP GRAPHICS MODES – LCD SXGA 1280X1024 MULTIPLE DISPLAY......................................... 61

TABLE 15. DESKTOP GRAPHICS MODES – LCD SXGA+ 1400X1050 MULTIPLE DISPLAY....................................... 62

TABLE 16. GRAPHICS MODES THAT ALLOW LCD CENTERING AND EXPANSION................................................. 63

TABLE 17. VGA GRAPHICS MODES........................................................................................................................................ 64

TABLE 18. DIRECT DRAW GRAPHICS MODES.................................................................................................................... 65

TABLE 19. GRAPHICS MODES FOR TV DISPLAY ............................................................................................................... 66

TABLE 20. ADDITIONAL GRAPHICS MODES FOR IA DEVICES ..................................................................................... 67

TABLE 21. FPD RGB MAPPING................................................................................................................................................. 68

TABLE 22. ABSOLUTE MAXIMUM RATINGS....................................................................................................................... 69

TABLE 23. DC CHARACTERISTICS......................................................................................................................................... 69

TABLE 24. AC TIMING MIN / MAX CONDITIONS................................................................................................................ 69

Revision 2.06, December 1, 2004 -iv- Table of Contents

CLE266 Version CD / CE Desktop North Bridge Data Sheet

CLE266 VERSION CD / CE

NORTH BRIDGE

Single-Chip SMA North Bridge

with 133 / 100 / 66 MHz Front Side Bus for VIA C3 CPUs

with Integrated 2D / 3D AGP Graphics Core

plus Advanced DDR Memory Controller

supporting DDR266 / 200 DDR SDRAM

and PC133 / PC100 SDR SDRAM

for Desktop PC Systems

PRODUCT FEATURES

• Defines Integrated Solutions for Value PC Desktop Designs

– High performance SMA North Bridge: Integrated Apollo Pro266T and graphics accelerator in a single chip
– 64-bit advanced memory controller supporting DDR266 / 200 DDR SDRAM and PC133 / PC100 SDR SDRAM
– Combines with VIA VT8233A V-Link South Bridge for integrated audio, ATA-133 IDE and 4 USB ports

• High Performance CPU Interface

– Support for Socket-370 VIA C3 processors
– 133 / 100 / 66 MHz CPU Front Side Bus (FSB)
– Built-in Phase Lock Loop circuitry for optimal skew control within and between clocking regions
– Five outstanding transactions (Four In-Order Queue (IOQ) plus one output latch)
– Dynamic deferred transaction support

• High Bandwidth 266 MB / Sec 8-Bit V-Link Host Controller

– Supports 66 MHz V-Link Host interface with total bandwidth of 266 MB/Sec
– V-Link operates at 2x or 4x modes
– Full-duplex commands with separate strobe / command
– Request / Data split transaction
– Configurable outstanding transaction queue for Host to V-Link Client accesses
– Supports Defer / Defer-Reply transactions
– Transaction assurance for V-Link Host to Client access (eliminates V-Link Host-Client Retry cycles)
– Intelligent V-Link transaction protocol to minimize data wait-states / throttle transfer latency. All V-Link transactions

(both Host and Client) have a consistent view of transaction data depth and buffer size to avoid data overflow.

– Highly efficient V-Link arbitration with minimum overhead. All V-Link transactions have predictable cycle length

with known Command / Data duration.

Revision 2.06, December 1, 2004 -1- Product Features

CLE266 Version CD / CE Desktop North Bridge Data Sheet

• Advanced High-Performance DDR / SDR DRAM Controller

– Supports DDR266 / 200 DDR SDRAM and PC133 / PC100 SDR SDRAM memory types
– DRAM interface synchronous with host CPU (133 / 100 MHz) for most flexible configuration
– DRAM interface may be faster or slower than CPU by 33 MHz
– Concurrent CPU, AGP and V-Link access
– Mixed 1M / 2M / 4M / 8M / 16M / 32M / 64MxN DRAMs
– Supports 4 banks up to 2 GB DRAMs (512Mb x8 / x16 DRAM technology)
– Flexible row and column addresses. 64-bit data width only
– LVTTL 3.3V DRAM interface with 2.5V SSTL-2 DRAM interface (DDR) and 5V-tolerant inputs (SDR)
– Programmable I/O drive capability for MA, command and MD signals
– Two-bank interleaving for 16Mbit SDRAM support
– Two-bank and four bank interleaving for 64Mbit SDRAM support
– Supports maximum 8-bank interleave (i.e., 8 pages open simultaneously); banks are allocated based on LRU
– Seamless DRAM command scheduling for maximum DRAM bus utilization (e.g., precharge other banks while

accessing the current bank)
– Four cache lines (16 quadwords) of CPU to DRAM write buffers
– Four cache lines of CPU to DRAM read prefetch buffers
– Read around write capability for non-stalled CPU read
– Speculative DRAM read before snoop result
– Burst read and write operation
– x-1/2-1/2-1/2-1-1/2-1/2-1/2 back-to-back accesses for DDR SDRAM (x-1-1-1-1-1-1-1 for SDR)
– Supports DDR SDRAM CL 2/2.5/3 and 1T per command
– Decoupled and burst DRAM refresh with staggered RAS timing (CAS before RAS or self refresh)

• Integrated Graphics / Video Accelerator

– Optimized Shared Memory Architecture (SMA)
– 8 / 16 / 32 / 64MB frame buffer using system memory
– Internal AGP 4x-equivalent performance
– Separate 128-bit data paths between North Bridge and graphics core for pixel data flow and texture / command

access
– Graphics engine clocks up to 133 MHz decoupled from memory clock
– Direct hardware inputs to force graphics accelerator into suspend / standby states
– High quality DVD video playback
– VIP 1.1 / VIP 2.0-compatible video capture inputs up to 165 MHz data rate
– Internal hardware VGA controller with true-color / high-color sprite for hardware cursor implementation
– 128-bit 2D graphics engine
– 128-bit 3D graphics engine
– Floating point triangle setup engine
– 3M triangles/second setup engine
– 133M pixels/second trilinear fill rate

• Extensive Display Support

– CRT display interface with 24-bit true-color RAMDAC up to 250 MHz pixel rate with gamma correction capability
– Direct TFT flat panel interface up to 24-bit data width supporting 18, 24 or 18+18 TFT panels or LVDS encoders
– 12-bit DVI 1.0-compatible interface for drive of flat panel monitor using external TMDS encoders
– Interface to external TV Encoder for NTSC or PAL TV display
– Flexible output configuration: CRT output plus 8-bit video capture port plus either 1) LCD Panel + DVI or TV-Out

or 2) DVI + TV-Out + 2
– Support for panel resolutions up to 1600x1200, CRT resolutions up to 1400x1050and DVI up to 1280x1024
– Automatic panel power sequencing and VESA DPMS CRT power-down
– Dual view capability where CRT and Flat Panel Monitor can have a different resolution and refresh rate
– Built-in reference voltage generator and monitor sense circuits

2

C Serial Bus and DDC Monitor Communications for CRT Plug-and-Play configuration

– I

nd

8-bit video capture port (or video capture port extension to 16-bit)

Revision 2.06, December 1, 2004 -2- Product Features

CLE266 Version CD / CE Desktop North Bridge Data Sheet

• Video Support

– Up to three video windows for video conferencing applications
– High quality scaler (up or down) for both horizontal and vertical scaling (linear interpolation for horizontal and

vertical up-scaling and filtering for horizontal and vertical down-scaling)
– Color space conversion
– Color enhancement (contrast, hue, saturation, brightness and gamma correction)
– Color and chroma key support
– Hardware sub-picture blending
– Bob / weave de-interlacing mode and advanced de-interlacing to improve video quality
– Video capture inputs (one or two 8-bit ports or one 16-bit port) with built-in phase adjuster to fine tune the clock/data

signal timing
– PAL / NTSC TV output capability using external TV encoder
– Supports CCIR601standard

• MPEG-2/1 Video Decoder

– Motion compensation for full speed DVD playback
– Hardware accelerated Slice layer, IDCT and Motion compensation

• 2D Hardware Acceleration Features

– BitBLT (bit block transfer) functions including alpha blts
– Text function
– Bresenham line drawing / style line function
– ROP3, 256 operation
– Color expansion
– Source and destination color keys
– Transparency mode
– Window clipping
– 8, 15/16and 32 bpp mode acceleration

• 3D Hardware Acceleration Features

– Microsoft DirectX 7.0 and 8.0 compatible
– OpenGL driver available
– Floating-point setup engine
– Triangle rate up to 3-million triangles per second and Pixel rate up to 133-million pixels per second for 2 texture,

depth test and alpha blending
– Flat and Gouraud shading
– Hardware back-face culling
– 16-bit, 32-bit Z testand 24+8 Z+Stencil test support
– Z-Bias support
– Stipple Test, Line-Pattern test, Texture-Transparence test, Alpha test support
– Edge anti-aliasing support
– Two textures per pass
– Tremendous Texture Format: 16/32 bpp ARGB, 1/2/4/8 bpp Luminance, 1/2/4/8 bpp Intensity, 1/2/4/8 bpp Paletized

(ARGB), YUV 422/420 format
– Texture sizes up to 2048x2048
– High quality texture filter modes: Nearest, Linear, Bi-linear, Tri-linear, Anisotropic
– LOD-Bias support
– Vertex Fog and Fog Table
– Specular Lighting
– Alpha Blending
– High quality dithering
– ROP2 support
– Internal full 32-bit ARGB format for high rendering quality
– System balance to achieve high performance

Revision 2.06, December 1, 2004 -3- Product Features

CLE266 Version CD / CE Desktop North Bridge Data Sheet

• Advanced System Power Management

– Power down of SDRAM (CKE)
– Independent clock stop controls for CPU / SDRAM and on-chip AGP bus
– Suspend power plane for preservation of memory data
– Suspend-to-DRAM and self-refresh power down
– Low-leakage I/O pads
– ACPI 1.0B and PCI Bus Power Management 1.1 compliant

• Full Software Support

– Drivers for major operating systems and APIs: [Windows 9x, Windows NT, Windows 2000, Windows XP,

Direct3D, DirectDraw and DirectShow, OpenGL ICD for Windows 9x, NT, 2000 and XP]
– North Bridge / Chipset and Video BIOS support (including all standard VESA CRT display modes)

• 2.5V Core and Mixed 3.3V / 5V Tolerant and GTL+ I/O

• 27 x 27mm Ball Grid Array Package with 548 Balls and 1mm Ball Pitch

Revision 2.06, December 1, 2004 -4- Product Features

CLE266 Version CD / CE Desktop North Bridge Data Sheet

CLE266 SYSTEM OVERVIEW

CLE266 is a high performance, cost-effective and energy efficient SMA chipset North Bridge which may be used for the
implementation of desktop personal computer systems with 133 / 100 / 66 MHz CPU host bus (“Fron t Side Bus”) frequencies and
based on 64-bit Socket-370 VIA C3 processors.

System

VIA C3™

Socket-370

CPU

TFT Flat Panel

Flat

Panel

Monitor

133 or 100 MHz
Front Si de Bus

CRT

24-bit Direct

Panel Interface

or DVI plus 8-b it

Video Capture

Extension

64-bit 133 / 100 MHz DDR or SDR SDRAM

CLE266

SMA

North Bridge

548-pin HSBGA

12-bit DVI
or TV Out

8-Bit

Video

Capture

Port

Flat

Panel

Monitor

Figure 1. System Block Diagram

66 MHz QDR, 8-bit V-Link

PCI Slots

TV

Encoder

Television

33MHz,

32-bit

PCI

4x USB

Display

Manageme nt

VT8233A

V-Link

South Bridge

376-pin BGA

AC-Link

VT16 16

AC'97 Aud io Codec

MC-97

Modem Codec

Integrated
AC'97 Aud io

Bus

Direct

LPC

VT1211

LPC

Super

I/O

UDMA / ATA

133 / 100 / 66 / 33

EPROM

Or LPC

Serial / IR

Parallel

Floppy Disk

Keyboard

Mouse

The complete chipset consists of the CLE266 North Bridge and the VT8233A V-Link South Bridge. The CLE266 North Bridge
integrates VIA’s Apollo Pro266T system controller, 128-bit graphics accelerator and flat panel interfaces into a single 548 BGA
package. The CLE266 provides superior performance between the CPU, DRAM, V-Link bus and internal AGP 8x graphics

controller bus with pipelined, burst and concurrent operation. The VT8233A V-Link Client controller is a highly integrated PCI /

LPC controller. Its internal bus structure is based on a 66 MHz PCI bus that provides 2x bandwidth compared to previous
generation PCI / ISA bridge chips. The VT8233A also provides a 266 MB / Sec bandwidth Host / Client V-Link interface with V­Link-PCI and V-Link-LPC controllers. It supports five PCI slots of arbitration and decoding for all integrated functions and LPC
bus.

CLE266 Version CD / CE Overview

The CLE266 supports four banks of DDR / SDR SDRAMs up to 2 GB. The DRAM controller supports DDR266 / 200 Double­Data-Rate (DDR) SDRAM but can also support standard PC1 33 / PC100 Synchronous DRAM (SDR SDRAM). The DD R / SDR
DRAM interface allows zero wait state bursting between the DRAM and the data buffers at 133 / 100 MHz. Th e different banks
of DRAM can be composed of an arbitrary mixture of 1M / 2M / 4M / 8M / 16M / 32M / 64M xN DRAMs. The DRAM controller
can run either synchronous or pseudo-synchronous with the host CPU bus.

The CLE266 host system controller supports a high speed 8-bit 66 MHz Quad Data Transfer interconnect (V-Link) to the
VT8233A South Bridge. Each chip also contains a built-in bus-to-bus bridge to allow simultaneous concurren t operations on each
bus. Five levels (doublewords) of post write buffers are included to allow for concurrent CPU and V-Link operation. For V-Link
Host operation, forty-eight levels (doublewords) of post write buffers and sixteen levels (doublewords) of prefetch buffers are
included for concurrent V-Link bus and DRAM/cache accesses. The combined V-Link Host and Client controllers realize a
complete PCI sub-system that supports enhanced PCI bus commands such as Memory-Read-Line, Memory-Read-Multiple and
Memory-Write-Invalid commands to minimize snoop overhead. In addition, advanced features are supported such as snoop ahead,

Revision 2.06, December 1, 2004 -5- Overview

CLE266 Version CD / CE Desktop North Bridge Data Sheet

snoop filtering, L1 write-back forward to PCI master and L1 write-back merged with PCI post write buffers to minimize PCI
master read latency and DRAM utilization. Delay transaction and read caching mechanisms are also implemented for further
improvement of overall system performance.

The CLE266 North Bridge also integrates a VIA-designed 128-bit graphics accelerator into the chip. This brings mainstream
graphics performance to the Value PC with leading-edge 2D, 3D and DVD video acceleration into a cost effective package. Based
on its capabilities, the CLE266 is an ideal solution for the consumer, corporate desktop users and entry-level professionals.

The industry’s first low-cost integrated AGP 8x solution to support DDR memory, the CLE266 North Bridge combines internal
AGP 8x equivalent performance with massive 2Kx2K textures to deliver unprecedented performan ce and image quality for the
Value PC desktop market.

The 376-pin Ball Grid Array VT8233A Client V-Link PCI / LPC controller suppor ts four levels (doublewords) of line buffers,
type F DMA transfers and delay transaction to allow efficient PCI bus utilization and (PCI-2.1 compliant). The VT8233A
integrated PCI controller and PCI arbitration for up to five PCI slots. One of the PCI REQ / GNT pairs can be configur ed as high­priority to better support a low latency PCI bus master device.

The VT8233A also includes an integrated keyboard controller with PS2 mouse support, integrated DS12885 style real time clock
with extended 256 byte CMOS RAM, integrated master mode enhanced IDE controller with full scatter / gather capability and
extension to UltraDMA-133 / 100 / 66 / 33 for 133 / 100 / 66 / 33 MB/sec transfer rate, integrated USB interface with two root
hubs and four functional ports with built-in physical lay er transceivers, Distributed DMA support and OnNow / ACPI compliant
advanced configuration and power management interface.

System Power Management

For sophisticated power management, the CLE266 provides independent clock stop control for the CPU / SDRAM and PCI and
CKE control for powering down of the SDRAM. A separate suspend-well plane is implemented for the SDRAM control signals
for Suspend-to-DRAM operation. Using the CLE266 North Bridge coupled with the VT8233A South Bridge, a complete power
conscious PC main board can be implemented with no external TTLs.

High-Performance 3D Accelerator

Featuring an internal 128-bit 3D graphics engine, the CLE266 North Bridg e utilizes a single cycle architecture that provides high
performance along with superior image quality. Several new features enhance the 3D architecture, including single-pass
multitexturing, anisotropic filtering and an 8-bit stencil buffer. The chip also offers the industry’s only simultaneous usage of
single-pass multitexturing and single-cycle trilinear filtering – enab ling stunning image quality without performance loss. Image
quality is further enhanced with true 32-bit color rendering throughout the 3D pipeline to produce more vi vid and realistic images.
The advanced triangle setup engine provides industry leading 3D performance for a realistic user experience in games and other
interactive 3D applications. The 3D engine is optimized for AGP texturing from system memory.

128-bit 2D Graphics Engine

The CLE266 North Bridge advanced 128-bit 2D graphics engine delivers high-speed 2D acceleration for productivity applications.
The enhanced 2D architecture optimizes SMA performance and provides acceleration of all color depths.

DVD Playback and Video Conferencing

The CLE266 North Bridge provides the ideal architecture for high quality MPEG-2 based DVD applications and video
conferencing. For DVD playback, the integrated video accelerator offloads the CPU by performing the planar to packed format
conversion and motion compensation tasks, while it is enhanced s caling algorithm delivers incredible full-screen video playback.
For video conferencing, multiple video windows enable a cost effective solution.

Revision 2.06, December 1, 2004 -6- Overview

CLE266 Version CD / CE Desktop North Bridge Data Sheet

TV Display Output Support

The CLE266 North Bridge provides an interface to an external TV Encoder (VIA VT1621, VT1622 or compatible).

Video Capture Interface

The CLE266 North Bridge provides a VIP 2.0-compatible interface to allow capture of video from an external source. This
interface can be configured as one 8-bit, one 16-bit or two 8-bit ports.

LCD, Flat Panel Monitor and TV Output Display Support

The CLE266 North Bridge supports a wide variety of LCD panels through a direct interface up to 24-bits wide. This includes
support for VGA, SVGA, XGA, SXGA+, UXGA and UXGA+ TFT color panels with 18-bit and 24-bit interfaces (both 1
pixel/clock and 2 pixels/clock for both 18 and 24-bit interfaces). The CLE266 North Bridge supports UXGA (1600x1200) and
higher resolutions only with the VIA VT1631 LVDS Transmitter chip since the VT1631 supports dual-edge data transfer.

In addition to the 24-bit panel interface, also provided is a 12-bit interface to a TMDS encoder. This interface is Digital Visual
Interface (DVI) 1.0 compliant for driving an external flat panel monitor. The pins of the DVI port can optionally be configured for
support of an external TV-Encoder for display of video on a TV display. An alternate configuration, however, allows the upper
bits of the 24-bit direct flat panel interface to be configured as a DVI interface with di splay resolution support up to 1280x1024.
This allows both TV out and DVI capability at the same time with the lower bits of the flat panel interface configured for either an
8-bit direct panel interface, a second 8-bit video capture port or an extension of the basic 8-bit capture port to 16 bits.

Available display interface combinations:

• CRT + DVI + TV-Out + 8-Bit or 16-Bit Video Capture Port

• CRT + DVI + TV-Out + Two 8-Bit Video Capture Ports

• CRT + 24-bit LCD Panel + DVI or TV-Out + 8-bit Video Capture Port

High Screen Resolution CRT Support

Resolutions Supported

VGA - 640x480x8/16/32
SVGA - 800x600x8/16/32
XGA - 1024x768x8/16/32
SXGA - 1280x1024x8
SXGA - 1280x1024x16
SXGA - 1280x1024x32
SXGA+ - 1400x1050x8
SXGA+ - 1400x1050x16
SXGA+ - 1400x1050x32

Note: WHQL's DCT certification requires frame buffer size to be 16MB or above. For non-Window based applications, CLE266

supports 8MB frame buffer to reserve more available memory space for the system. Please refer to the register setting of
Device 0 Offset E1[6:4] for more details.

Table 1. Supported CRT Screen Resolutions

System Memory Frame Buffer Size

8 MB 16/32 MB 64 MB











 
 
 
 
 
 
 
 
 

Revision 2.06, December 1, 2004 -7- Overview

CLE266 Version CD / CE Desktop North Bridge Data Sheet

PINOUTS Figure 2. Ball Diagram (Top View)

Key 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

TVVS

TVD1

TVD3

TVD6

TVD9

DFT

A

DVIVS

DVID1

DVID3

DVID6

TVHS

TVD0

TVD2

B

DVIHS

DVID0

NC

TVCLK

C

DVIDT

CPD 3 CPD 2 CPD 1 CPD 0 TVBL#

D

CPD 5 CPD 4 CP

E

FPDE

F

CPD8

FPD2

G

CPD11

FPD5

H

CPD13

FPD7

J

CPD15

FPD10

K

DFDE

FPD15

L

DFD4

FPD18

M

DFD7

FPD21

N

DFD10

VAD

P

0

VAD 5 VDN

R

VUP

T

STB#

VAD

U

2

VAD 6 VAD 7 VAD 4 VL

V

PWR

W

OK

DVICLK

FPHS

CPHS

FPD1

CPD10

FPD4

CPD12

FPD6

CPD14

FPD9

DFHS

FPD14

DFD3

FPD17

DFD6

FPD22

DFD11

GND

STB

VUP
STB

GND

SUS

ST#

TVCKR

DFCLK

TVD5

DVID2

DVID5

TVD4

NC

DVID4

CLK

FPVS
CPVS

FPD0
CPD9

FPD3

DCLK I EN

CPCK1

FPCLK

DCLK

FPD8

FPD11

DFVS

DFD0

FPD13

FPD12

DFD2

DFD1

FPD19

FPD16

DFD8

DFD5

FPD20

FPD23

DFD9

DFDET

VAD 1 G

VDN
STB#

VDN

CMD

VREF

VL

PAR

COMP

RE

SET#

CPD 6 VCC

CPD 7 VCC

EN

VDD

O

CLK

VAD

3

VL

GND

CS3#

Y MD59 GND CS1# GND

AA MD63 MD58 MD62 CS0#

DQS

AB

7#

DQM

7

MD57

S

CAS# S WE#

DVID9

TVD8

DVID8

TVD7

DVID7

DVIDE

FP

FP

EN

VEE

BLT

GND

GND

VCC

FP

VCC

FP

GND

GND

VBE#

VUP

CMD

VCC

VL

VCC

VL

VSUS

25

VCC

M

VCC

M

TVD10

DVID10

TVD11

DVID11

AGP

IN

STDBY

INT

BIST

A#

AGP

SUSP

GPIO 0 GPIO 2 SP

GPIO 1 GPIO 3 SP

GND

F6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 F21

G

VCC

H

VCC

J

VCC

K

VCC

L

VCC

M

VCC

N

VCC

P

VCC

R

VCC

T

VCC M VCC

U

VCC M VCC

V

VCC M VCC

W

Y

AA6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 AA21

MA11

VREF

AC MD61 GND CS2# MD53 GND MA10 MD42 GND MD40 NC MA2 MD32 MA4 MA5

AD MD56 MD60 MD51 MD52

AE MD55 GND

AF MD50 MD54

DQS

GND MD47 MD46 GND MD41 MD39 GND

6#

DQM

MD49 MD48 MD43

6

S

RAS#

MA12

DQS

DQM

SP

CLK2 H SYNC

AGP

IN

BUSY#V SYNC

AGP
STP#

DAT2

DAT1

CLK1

VCC

FP

FP

FP

FP

FP

FP

VL

VL

VL

M

5#

5

VCC

FP

VCC

VCC

25

VCC

25

VCC

Panel

25

VCC

25

VCC

25

VCC

25

VCC

25

VCC

25

VCC

25

25

25

VCC

25

VCC M VCC M VCC M VCC M VCC M VCC M VCC M VCC M VCC M VCC M VCC M VCC

VCC M VCC

MD44 MD38 MA0 MA1 MD37 MD31 MA6

MD45 MD35 MD34

AB RSET

AG

SP

AR

VCC
RGB

GND GND XIN HD58 GND GND VTT VTT GND HD44

VCC

FP

FP

VCC

25

25

Flat

K10 11 12 13 14 15 16 K17

L

M

N

P

R

VL

Bus

T

U10 11 12 13 14 15 16 U17

DRAM

VCC

25

25

NC GND GND MA3 GND GND MA7 MA9

M

GND

GND

PLL1

GND

VCC

RGB

PLL1

VCC

GND

DAC

PLL2

GND

VCC

DAC

PLL2

VCC

VCC

FP

FP

VCC

VCC

25

25

GND GND GND GND GND GND

GND GND GND GND GND GND

GND GND GND GND GND GND

GND GND GND GND GND GND

GND GND GND GND GND GND

GND GND GND GND GND GND

VCC

VCC

25

25

DQM

MD33 GND MD30 MD25 GND MD22

4

DQS

MD36 MD27 MD26 MD29 MD28 MD19

4#

HD56 HD54 HD57 HD47 HD51 HD39 HD36 HD34 HD32 HD33 HD26 HD23 HD21

PLL3

GND HD61 HD55 GND HD40 HD49 GND HD37 HD22 GND HD19 HD24 GND HD16

VCC

HD60 HD46 HD52 HD63 HD41 HD45 HD38 HD28 HD31 HD25 HD30 HD7 HD3

PLL3

HD50 HD53 HD62 HD59 HD48 HD42 HD27 HD43 HD29 HD35 HD20 HD13 HD14 HD11

GND VTT VTT VTT VTT VTT VTT

VCC

VCC

VCC

25

VCC

25

25

VCC

25

VCC

25

25

VCC

VCC

25

25

DQM

MA8 MA13 GND MA14

3

DQS

MD24 MD23 MD18 MD17 MD11 MD10

3#

VCC

25

L

M

N

P

R

T

VCC

25

GTL

GND VTT HD2 HD9 GND HD18

VREF

VTT HD8 HD12 HD17 HD10

HD5 HD1 HD4 HD6 HD15

G

VCC

VCC

25

CPU

VCC

25

VCC M VCC M M

DQS

2#

DQM

2

VTT

25

VCC

VTT

25

VCC

VTT

25

VCC

VTT

25

VCC

VTT

25

VCC

VTT

25

VCC

VTT

25

VCC

VTT

25

VCC

VTT

25

VCC

VTT

25

VCC

VCC

25

M

VCC

VCC

25

M

M

GND MD16 MD14 GND MD12 MD8 GND MD6

MD21 MD20 MD15

VREF

CKE 0 CKE 2 CKE 1 MCLK

HA26 HA18

H

VTT HA29 HA24 HA27 HA30

J

VTT HA20 HA19 HA22 HA17

K

GND HA23 HA31 GND HA25

L

GND HA15 HA28 HA21 HA10

M

GND HA5 HA12 HA16 HA13

N

GND HA6 HA9 GND HA3

P

BNR# HA14 HA8 HA4 HA11

R

GTL

T

VREF

VTT

U

VTT

V

GND HIT#

W

GND

Y

GND MD0

VCC M VCC

MCLK

M

DQM 1 CKE

DQS

1#

CPU

RST#

HREQ

HA7

1#

DE

FER# H REQ0#

HIT

M# H REQ3#H LOCK#

D

BSY#

H

GND

CLK

HCK

VCC
HCK

VCC

MCK

GND

FB

MCK

MD2

3

MD13 MD9 MD3 MD7

GND HD0

HREQ

4# B PRI#

HT

H

REQ2#

RS1#

RS0#

D

RDY#

B

REQ0#

0#

GND

RDY#

RS2#

ADS#

MD5 MD4

GND MD1

DQM 0 DQS

Revision 2.06, December 1, 2004 -8- Pin Diagram

CLE266 Version CD / CE North Bridge Data Sheet

K

K

K

Table 2. Pin List (Listed by Pin Number)

Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin # Pin Names Pin # Pin Name

A01 O TVVS / DVIVS D01 I CPD03 G19 P VTT P01 IO VAD0 / strap Y09 P VCCM AD01 IO MD56
A02 O TVD01 / DVID01 D02 I CPD02 G22 IO HD05 P02 P GND Y10 P VCCM AD02 IO MD60
A03 O TVD03 / DVID03 D03 I CPD01 G23 IO HD01 P03 IO VAD1 / strapY11 P VCCM AD03 IO MD51
A04 O TVD06 / DVID06 D04 I CPD00 G24 IO HD04 P04 I GCL
A05 O TVD09 / DVID09 D05 O TVBL# / DVIDE G25 IO HD06 P05 P GND Y13 P VCCM AD05 O SRAS#
A06 I DFTIN D06 O TVD11 / DVID11 G26 IO HD15 P07 P VCCVL Y14 P VCCM AD06 O MA12
A07 I AGPSTDBY D07 IO GPIO0 H01 O FPD05 / CPD13 P20 P VTT Y15 P VCCM AD07 O DQS5#
A08 IO SPCLK2 D08 IO GPIO2 H02 O FPD04 / CPD12 P22 P GND Y16 P VCCM AD08 IO MD44
A09 O HSYNC D09 IO SPDAT1 H03 O FPD03 / CPCK1 P23 IO HA06 Y17 P VCCM AD09 IO MD38
A10 O AB D10 P VCCRGB H04 I DCLKI P24 IO HA09 Y18 P VCCM AD10 O MA00
A11 A RSET D11 P GNDDAC H05 O ENBLT P25 P GND Y19 P VCCM AD11 O MA01
A12 P GNDPLL1 D12 P VCCPLL2 H07 P VCCFP P26 IO HA03 Y22 P GND AD12 IO MD37
A13 P GNDPLL3 D13 IO HD50 H20 P VTT R01 IO VAD5 Y23 I HCLK AD13 IO MD31
A14 IO HD56 D14 IO HD53 H22 IO HA26 R02 O VDNSTB Y24 P GNDHCK AD14 O MA06
A15 IO HD54 D15 IO HD62 H23 IO HA18 R03 O VDNSTB# Y25 IO RS2# AD15 O DQS3#
A16 IO HD57 D16 IO HD59 H24 O CPURST# R04 IO VAD3 / strapY26 IO DRDY# AD16 IO MD24
A17 IO HD47 D17 IO HD48 H25 P GND R05 IO VBE# AA01 IO MD63 AD17 IO MD23
A18 IO HD51 D18 IO HD42 H26 IO HD00 R07 P VCCVL AA02 IO MD58 AD18 IO MD18
A19 IO HD39 D19 IO HD27 J01 O FPD07 / CPD15 R20 P VTT AA03 IO MD62 AD19 IO MD17
A20 IO HD36 D20 IO HD43 J02 O FPD06 / CPD14 R22 IO BNR# AA04 O CS0# AD20 IO MD11
A21 IO HD34 D21 IO HD29 J03 O FPCLK / DFCL
A22 IO HD32 D22 IO HD35 J04 O DCLKO R24 IO HA08 AA22 P GND AD22 O DQM1
A23 IO HD33 D23 IO HD20 J05 P GND R25 IO HA04 AA23 IO MD00 AD23 O CKE3
A24 IO HD26 D24 IO HD13 J07 P VCCFP R26 IO HA11 AA24 P VCCHCK AD24 IO MD02
A25 IO HD23 D25 IO HD14 J20 P VTT T01 I VUPSTB# AA25 IO ADS# AD25 O DQM0
A26 IO HD21 D26 IO HD11 J22 P VTT T02 I VUPSTB AA26 O BREQ0# AD26 O DQS0#
B01 O TVHS / DVIHS E01 I CPD05 J23 IO HA29 T03 O VDNCMD AB01 O DQS7# AE01 IO MD55
B02 O TVD00 / DVID00 E02 I CPD04 J24 IO HA24 T04 P VLVREF AB02 O DQM7 AE02 P GND
B03 O TVD02 / DVID02 E03 I CPCLK J25 IO HA27 T05 I VUPCMD AB03 IO MD57 AE03 O DQS6#
B04 O TVD05 / DVID05 E04 I CPD06 J26 IO HA30 T07 P VCCVL AB04 O SCAS# AE04 P GND
B05 O TVD08 / DVID08 E05 P VCCFP K01 O FPD10 / DFDE / strapT20 P VTT AB05 O SWE# AE05 IO MD47
B06 O INTA# E06 P GND K02 O FPD09 / DFHS / strapT22 P GTLVREF AB06 O MA11 AE06 IO MD46
B07 I BISTIN E07 IO GPIO1 K03 O FPD08 / DFVS / strapT23 IO HREQ1# AB07 P MEMVREF AE07 P GND
B08 O AGPBUSY# E08 IO GPIO3 K04 O FPD11 / DFD00 / strapT24 IO HA07 AB08 P VCCM AE08 IO MD41
B09 O VSYNC E09 IO SPCLK1 K05 P GND T25 IO HREQ4# AB09 P VCCM AE09 IO MD39
B10 O AG E10 P GND K07 P VCCFP T26 IO BPRI# AB10 – NC AE10 P GND
B11 P GNDRGB E11 P GND K20 P VTT U01 IO VAD2 / strapAB11 P GND AE11 O DQM4
B12 P VCCPLL1 E12 I XIN K22 P VTT U02 P GND AB12 P GND AE12 IO MD33
B13 P GND E13 IO HD58 K23 IO HA20 U03 IO VLPAR AB13 O MA03 AE13 P GND
B14 IO HD61 E14 P GND K24 IO HA19 U04 P GND AB14 P GND AE14 IO MD30
B15 IO HD55 E15 P GND K25 IO HA22 U05 P VCCVL AB15 P GND AE15 IO MD25
B16 P GND E16 P VTT K26 IO HA17 U07 P VCCM AB16 O MA07 AE16 P GND
B17 IO HD40 E17 P VTT L01 O FPD15 / DFD04 / strapU20 P VTT AB17 O MA09 AE17 IO MD22
B18 IO HD49 E18 P GND L02 O FPD14 / DFD03 / strapU22 P VTT AB18 P VCCM AE18 O DQS2#
B19 P GND E19 IO HD44 L03 O FPD13 / DFD02 / strapU23 IO DEFER# AB19 P VCCM AE19 P GND
B20 IO HD37 E20 P GTLVREF L04 O FPD12 / DFD01 / strapU24 IO HREQ0# AB20 P MEMVREF AE20 IO MD16
B21 IO HD22 E21 P GND L05 P VCCFP U25 P GND AB21 P VCCM AE21 IO MD14
B22 P GND E22 P VTT L07 P VCCFP U26 IO HREQ2# AB22 P VCCM AE22 P GND
B23 IO HD19 E23 IO HD02 L20 P VTT V01 IO VAD6 AB23 O MCLK AE23 IO MD12
B24 IO HD24 E24 IO HD09 L22 P GND V02 IO VAD7 AB24 P VCCMCK AE24 IO MD08
B25 P GND E25 P GND L23 IO HA23 V03 IO VAD4 AB25 IO MD05 AE25 P GND
B26 IO HD16 E26 IO HD18 L24 IO HA31 V04 A VLCOMP AB26 IO MD04 AE26 IO MD06
C01 I DVIDET F01 O FPDE / CPD08 L25 P GND V05 P VCCVL AC01 IO MD61 AF01 IO MD50
C02 O TVCLK / DVICLK F02 O FPHS / CPHS L26 IO HA25 V07 P VCCM AC02 P GND AF02 IO MD54
C03 I TVCLKR / NC F03 O FPVS / CPVS M01 O FPD18 / DFD07 / strapV20 P VCCM AC03 O CS2# AF03 O DQM6
C04 O TVD04 / DVID04 F04 I CPD07 M02 O FPD17 / DFD06 / strapV22 P VTT AC04 IO MD53 AF04 IO MD49
C05 O TVD07 / DVID07 F05 P VCCFP M03 O FPD19 / DFD08 / strapV23 I HITM# AC05 P GND AF05 IO MD48
C06 O TVD10 / DVID10 F22 P VTT M04 O FPD16 / DFD05 / strapV24 IO HREQ3# AC06 O MA10 AF06 IO MD43
C07 I AGPSUSP F23 IO HD08 M05 P VCCFP V25 I HLOCK# AC07 IO MD42 AF07 O DQM5
C08 IO AGPSTP# F24 IO HD12 M07 P VCCFP V26 IO RS1# AC08 P GND AF08 IO MD45
C09 IO SPDAT2 F25 IO HD17 M20 P VTT W01 I PWRO
C10 O AR F26 IO HD10 M22 P GND W02 I SUSST# AC10 – NC AF10 IO MD34
C11 P VCCDAC G01 O FPD02 / CPD11 M23 IO HA15 W03 I RESET# AC11 O MA02 AF11 O DQS4#
C12 P GNDPLL2 G02 O FPD01 / CPD10 M24 IO HA28 W04 O CS3# AC12 IO MD32 AF12 IO MD36
C13 P VCCPLL3 G03 O FPD00 / CPD9 M25 IO HA21 W05 P VSUS25 AC13 O MA04 AF13 IO MD27
C14 IO HD60 G04 O ENVDD M26 IO HA10 W07 P VCCM AC14 O MA05 AF14 IO MD26
C15 IO HD46 G05 O ENVEE N01 O FPD21 / DFD10 / strapW20 P VCCM AC15 O DQM3 AF15 IO MD29
C16 IO HD52 G08 P VCCFP N02 O FPD22 / DFD11 / strapW22 P GND AC16 O MA08 AF16 IO MD28
C17 IO HD63 G09 P VCCFP N03 O FPD20 / DFD09 / strapW23 IO HIT# AC17 O MA13 AF17 IO MD19
C18 IO HD41 G10 P VCCFP N04 O FPD23 / DFDET W24 IO DBSY# AC18 P GND AF18 O DQM2
C19 IO HD45 G11 P VCCFP N05 P GND W25 IO HTRDY# AC19 O MA14 AF19 IO MD21
C20 IO HD38 G12 P VCCFP N07 P VCCFP W26 IO RS0# AC20 O CKE0 AF20 IO MD20
C21 IO HD28 G13 P GND N20 P VTT Y01 IO MD59 AC21 O CKE2 AF21 IO MD15
C22 IO HD31 G14 P VTT N22 P GND Y02 P GND AC22 O CKE1 AF22 O DQS1#
C23 IO HD25 G15 P VTT N23 IO HA05 Y03 O CS1# AC23 I MCLKFB AF23 IO MD13
C24 IO HD30 G16 P VTT N24 IO HA12 Y04 P GND AC24 P GNDMCK AF24 IO MD09
C25 IO HD07 G17 P VTT N25 IO HA16 Y05 P VCCM AC25 P GND AF25 IO MD03
C26 IO HD03 G18 P VTT N26 IO HA13 Y08 P VCCM AC26 IO MD01 AF26 IO MD07

Center VCC25 Pins (44 pins): H8-19, J8, 19, K8,19, L8,19, M8,19, N8,19, P8,19, R8,19, T8,19, V8,19, W8-19.
Center GND Pins (37 pins): G13, L11-16, M11-16, N11-16, P11-16, R11-16, T11-16

R23 IO HA14 AA05 P VCCM AD21 IO MD10

Y12 P VCCM AD04 IO MD52

AC09 IO MD40 AF09 IO MD35

Revision 2.06, December 1, 2004 -9- Pin Lists

CLE266 Version CD / CE North Bridge Data Sheet

K

K

K

K

Table 3. Pin List (Listed by Pin Name)

Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin # Pin Names Pin # Pin Name

A10 O AB N01 O FPD21 / DFD10 / strap P24 IO HA09 A15 IO HD54 AC09 IO MD40 K07 P VCCFP
B10 O AG N02 O FPD22 / DFD11 / strapM26 IO HA10 B15 IO HD55 AE08 IO MD41 L05 P VCCFP

AA25 IO ADS# N04 O FPD23 / DFDET R26 IO HA11 A14 IO HD56 AC07 IO MD42 L07 P VCCFP

B08 O AGPBUSY# F01 O FPDE / CPD08 N24 IO HA12 A16 IO HD57 AF06 IO MD43 M05 P VCCFP
A07 I AGPSTDBY F02 O FPHS / CPHS N26 IO HA13 E13 IO HD58 AD08 IO MD44 M07 P VCCFP
C08 IO AGPSTP# F03 O FPVS / CPVS R23 IO HA14 D16 IO HD59 AF08 IO MD45 N07 P VCCFP
C07 I AGPSUSP P04 I GCLK M23 IO HA15 C14 IO HD60 AE06 IO MD46 AA24 P VCCHC
C10 O AR B13 P GND N25 IO HA16 B14 IO HD61 AE05 IO MD47 U07 P VCCM
B07 I BISTIN B16 P GND K26 IO HA17 D15 IO HD62 AF05 IO MD48 V07 P VCCM
R22 IO BNR# B19 P GND H23 IO HA18 C17 IO HD63 AF04 IO MD49 V20 P VCCM

T26 IO BPRI# B22 P GND K24 IO HA19 W23 IO HIT# AF01 IO MD50 W07 P VCCM
AA26 O BREQ0# B25 P GND K23 IO HA20 V23 I HITM# AD03 IO MD51 W20 P VCCM
AC20 O CKE0 E06 P GND M25 IO HA21 V25 I HLOCK# AD04 IO MD52 Y05 P VCCM
AC22 O CKE1 E10 P GND K25 IO HA22 U24 IO HREQ0# AC04 IO MD53 Y08 P VCCM
AC21 O CKE2 E11 P GND L23 IO HA23 T23 IO HREQ1# AF02 IO MD54 Y09 P VCCM
AD23 O CKE3 E14 P GND J24 IO HA24 U26 IO HREQ2# AE01 IO MD55 Y10 P VCCM

E03 I CPCLK E15 P GND L26 IO HA25 V24 IO HREQ3# AD01 IO MD56 Y11 P VCCM

D04 I CPD00 E18 P GND H22 IO HA26 T25 IO HREQ4# AB03 IO MD57 Y12 P VCCM

D03 I CPD01 E21 P GND J25 IO HA27 A09 O HSYNC AA02 IO MD58 Y13 P VCCM

D02 I CPD02 E25 P GND M24 IO HA28 W25 IO HTRDY# Y01 IO MD59 Y14 P VCCM

D01 I CPD03 G13 P GND J23 IO HA29 B06 O INTA# AD02 IO MD60 Y15 P VCCM

E02 I CPD04 H25 P GND J26 IO HA30 AD10 O MA00 AC01 IO MD61 Y16 P VCCM

E01 I CPD05 J05 P GND L24 IO HA31 AD11 O MA01 AA03 IO MD62 Y17 P VCCM

E04 I CPD06 K05 P GND Y23 I HCL

F04 I CPD07 L22 P GND H26 IO HD00 AB13 O MA03 AB07 P MEMVREF Y19 P VCCM

H24 O CPURST# L25 P GND G23 IO HD01 AC13 O MA04 AB20 P MEMVREF AA05 P VCCM
AA04 O CS0# M22 P GND E23 IO HD02 AC14 O MA05 AB10– NC AB08 P VCCM

Y03 O CS1# N05 P GND C26 IO HD03 AD14 O MA06 AC10– NC AB09 P VCCM
AC03 O CS2# N22 P GND G24 IO HD04 AB16 O MA07 W01 I PWROK AB18 P VCCM

W04 O CS3# P02 P GND G22 IO HD05 AC16 O MA08 W03 I RESET# AB19 P VCCM
W24 IO DBSY# P05 P GND G25 IO HD06 AB17 O MA09 W26 IO RS0# AB21 P VCCM

H04 I DCLKI P22 P GND C25 IO HD07 AC06 O MA10 V26 IO RS1# AB22 P VCCM

J04 O DCLKO P25 P GND F23 IO HD08 AB06 O MA11 Y25 IO RS2# AB24 P VCCMC
U23 IO DEFER# U02 P GND E24 IO HD09 AD06 O MA12 A11 A RSET B12 P VCCPLL1
A06 DFTIN U04 P GND F26 IO HD10 AC17 O MA13 AB04 O SCAS# D12 P VCCPLL2

AD25 O DQM0 U25 P GND D26 IO HD11 AC19 O MA14 E09 IO SPCLK1 C13 P VCCPLL3
AD22 O DQM1 W22 P GND F24 IO HD12 AC23 I MCLKFB A08 IO SPCLK2 D10 P VCCRGB

AF18 O DQM2 Y02 P GND D24 IO HD13 AB23 O MCL
AC15 O DQM3 Y04 P GND D25 IO HD14 AA23 IO MD00 C09 IO SPDAT2 R07 P VCCVL
AE11 O DQM4 Y22 P GND G26 IO HD15 AC26 IO MD01 AD05 O SRAS# T07 P VCCVL

AF07 O DQM5 AA22 P GND B26 IO HD16 AD24 IO MD02 W02 I SUSST# U05 P VCCVL

AF03 O DQM6 AB11 P GND F25 IO HD17 AF25 IO MD03 AB05 O SWE# V05 P VCCVL
AB02 O DQM7 AB12 P GND E26 IO HD18 AB26 IO MD04 D05 O TVBL# / DVIDE T03 O VDNCMD
AD26 IO DQS0# AB14 P GND B23 IO HD19 AB25 IO MD05 C02 O TVCLK / DVICLKR02 O VDNSTB

AF22 IO DQS1# AB15 P GND D23 IO HD20 AE26 IO MD06 C03 I TVCLKR R03 O VDNSTB#
AE18 IO DQS2# AC02 P GND A26 IO HD21 AF26 IO MD07 B02 O TVD00 / DVID00 V04 A VLCOMP
AD15 IO DQS3# AC05 P GND B21 IO HD22 AE24 IO MD08 A02 O TVD01 / DVID01 U03 IO VLPAR

AF11 IO DQS4# AC08 P GND A25 IO HD23 AF24 IO MD09 B03 O TVD02 / DVID02 T04 P VLVREF
AD07 IO DQS5# AC18 P GND B24 IO HD24 AD21 IO MD10 A03 O TVD03 / DVID03 W05 P VSUS25
AE03 IO DQS6# AC25 P GND C23 IO HD25 AD20 IO MD11 C04 O TVD04 / DVID04 B09 O VSYNC
AB01 IO DQS7# AE02 P GND A24 IO HD26 AE23 IO MD12 B04 O TVD05 / DVID05 E16 P VTT

Y26 IO DRDY# AE04 P GND D19 IO HD27 AF23 IO MD13 A04 O TVD06 / DVID06 E17 P VTT
C01 I DVIDET AE07 P GND C21 IO HD28 AE21 IO MD14 C05 O TVD07 / DVID07 E22 P VTT
H05 O ENBLT AE10 P GND D21 IO HD29 AF21 IO MD15 B05 O TVD08 / DVID08 F22 P VTT
G04 O ENVDD AE13 P GND C24 IO HD30 AE20 IO MD16 A05 O TVD09 / DVID09 G14 P VTT
G05 O ENVEE AE16 P GND C22 IO HD31 AD19 IO MD17 C06 O TVD10 / DVID10 G15 P VTT

J03 O FPCLK / DFCLK AE19 P GND A22 IO HD32 AD18 IO MD18 D06 O TVD11 / DVID11 G16 P VTT
G03 O FPD00 / CPD9 AE22 P GND A23 IO HD33 AF17 IO MD19 B01 O TVHS / DVIHS G17 P VTT
G02 O FPD01 / CPD10 AE25 P GND A21 IO HD34 AF20 IO MD20 A01 O TVVS / DVIVS G18 P VTT
G01 O FPD02 / CPD11 D11 P GNDDAC D22 IO HD35 AF19 IO MD21 P01 IO VAD0 / strap G19 P VTT
H03 O FPD03 / CPCK1 Y24 P GNDHCK A20 IO HD36 AE17 IO MD22 P03 IO VAD1 / strap H20 P VTT
H02 O FPD04 / CPD12 AC24 P GNDMCK B20 IO HD37 AD17 IO MD23 U01 IO VAD2 / strap J20 P VTT
H01 O FPD05 / CPD13 A12 P GNDPLL1 C20 IO HD38 AD16 IO MD24 R04 IO VAD3 / strap J22 P VTT

J02 O FPD06 / CPD14 C12 P GNDPLL2 A19 IO HD39 AE15 IO MD25 V03 IO VAD4 K20 P VTT

J01 O FPD07 / CPD15 A13 P GNDPLL3 B17 IO HD40 AF14 IO MD26 R01 IO VAD5 K22 P VTT
K03 O FPD08 / DFVS / strap B11 P GNDRGB C18 IO HD41 AF13 IO MD27 V01 IO VAD6 L20 P VTT
K02 O FPD09 / DFHS / strap D07 IO GPIO0 D18 IO HD42 AF16 IO MD28 V02 IO VAD7 M20 P VTT
K01 O FPD10 / DFDE / strap E07 IO GPIO1 D20 IO HD43 AF15 IO MD29 R05 IO VBE# N20 P VTT
K04 O FPD11 / DFD00 / strap D08 IO GPIO2 E19 IO HD44 AE14 IO MD30 C11 P VCCDAC P20 P VTT
L04 O FPD12 / DFD01 / strap E08 IO GPIO3 C19 IO HD45 AD13 IO MD31 E05 P VCCFP R20 P VTT
L03 O FPD13 / DFD02 / strap E20 P GTLVREF C15 IO HD46 AC12 IO MD32 F05 P VCCFP T20 P VTT
L02 O FPD14 / DFD03 / strap T22 P GTLVREF A17 IO HD47 AE12 IO MD33 G08 P VCCFP U20 P VTT
L01 O FPD15 / DFD04 / strap P26 IO HA03 D17 IO HD48 AF10 IO MD34 G09 P VCCFP U22 P VTT

M04 O FPD16 / DFD05 / strap R25 IO HA04 B18 IO HD49 AF09 IO MD35 G10 P VCCFP V22 P VTT
M02 O FPD17 / DFD06 / strap N23 IO HA05 D13 IO HD50 AF12 IO MD36 G11 P VCCFP T05 I VUPCMD
M01 O FPD18 / DFD07 / strap P23 IO HA06 A18 IO HD51 AD12 IO MD37 G12 P VCCFP T02 I VUPSTB
M03 O FPD19 / DFD08 / strap T24 IO HA07 C16 IO HD52 AD09 IO MD38 H07 P VCCFP T01 I VUPSTB#

N03 O FPD20 / DFD09 / strap R24 IO HA08 D14 IO HD53 AE09 IO MD39 J07 P VCCFP E12 I XIN

Center VCC25 Pins (44 pins): H8-19, J8,19, K8,19, L8,19, M8,19, N8,19, P8,19, R8,19, T8,19, V8,19, W8-19.
Center GND Pins (37 pins): G13, L11-16, M11-16, N11-16, P11-16, R11-16, T11-16

AC11 O MA02 AA01 IO MD63 Y18 P VCCM

D09 IO SPDAT1 P07 P VCCVL

Revision 2.06, December 1, 2004 -10- Pin Lists

CLE266 Version CD / CE North Bridge Data Sheet

Pin Descriptions

Table 4. Pin Descriptions

CPU Interface

Signal Name Pin # I/O Signal Description

HA[31:3]#

HD[63:0]#

ADS#

BNR#

BPRI#

DBSY#

DEFER#

DRDY#

HIT#

HITM#

HLOCK#

HREQ[4:0]#

HTRDY#

RS[2:0]#

CPURST#

BREQ0#

Note: Clocking of the CPU interface is performed with HCLK.
Note: Internal pullup resistors are provided on all GTL interface pins. If the CPU does not have internal pullups, the North

Bridge internal pullups may be enabled to allow the interface to meet GTL bus interface specifications (see strap
descriptions).

(see pin list) IO Host Address Bus. HA[31:3] connect to the address bus of the host CPU. During

CPU cycles HA[31:3] are inputs. These signals are driven by the CLE266 North Bridge
during cache snooping operations.

(see pin list) IO Host CPU Data. These signals are connected to the CPU data bus.

AA25 IO Address Strobe. The CPU asserts ADS# in T1 of the CPU bus cycle.

R22 IO Block Next Request. Used to block the current request bus owner from issuing new

requests. This signal is used to dynamically control the processor bus pipeline depth.

T26 IO Priority Agent Bus Request. The owner of this signal will always be the next bus

owner. This signal has priority over symmetric bus requests and causes the current
symmetric owner to stop issuing new transactions unless the HLOCK# signal is
asserted. The CLE266 North Bridge drives this signal to gain control of the processor
bus.

W24 IO Data Bus Busy. Used by the data bus owner to hold the data bus for transfers requiring

more than one cycle.

U23 IO Defer. A dynamic deferring policy is used to optimize system performance. The

DEFER# signal is also used to indicate a processor retry response.

Y26 IO Data Ready. Asserted for each cycle that data is transferred.

W23 IO Hit. Indicates that a caching agent holds an unmodified version of the requested line.

Also driven in conjunction with HITM# by the target to extend the snoop window.

V23 I Hit Modified. Asserted by the CPU to indicate that the address presented with the last

assertion of EADS# is modified in the L1 cache and needs to be written back.

V25 I Host Lock. All CPU cycles sampled with the assertion of HLOCK# and ADS# until

the negation of HLOCK# must be atomic.
T25, V24,
U26, T23,

U24

W25 IO Host Target Ready. Indicates that the target of the processor transaction is able to

Y25, V26, W26 IO Response Signals. Indicates the type of response per the table below:

H24 O CPU Reset. Reset output to CPU. External pullup and filter capacitor to ground

AA26 O Bus Request 0. Bus request output to CPU.

IO Request Command. Asserted during both clocks of the request phase. In the first

clock, the signals define the transaction type to a level of detail that is sufficient to

begin a snoop request. In the second clock, the signals carry additional information to

define the complete transaction type.

enter the data transfer phase.

RS[2:0]#

000 Idle State

001 Retry Response

010 Defer Response

011 Reserved

100 Hard Failure

101 Normal Without Data

110 Implicit Writeback

111 Normal With Data

should be provided per CPU manufacturer’s recommendations.

Response type

Revision 2.06, December 1, 2004 -11- Pin Description

CLE266 Version CD / CE North Bridge Data Sheet

The pinouts were defined assuming the ATX PCB layout model shown below (and general pin layout shown) as a guide for PCB
component placement. Other PCB layouts (AT, LPX and NLX) were also considered and can typically follow the same general
component placement.

PCI Slots

VT8233A

South

Bridge

1 26

FP

Socket-370

CPU

CR

CPU

T

CLE

266

DRAM

A

…

AF

IDE Connectors

DRAM Modules

Power

Supply

V-Link Interface

Signal Name Pin # I/O Signal Description

VAD7,
VAD6,
VAD5,

VAD4,
VAD3 / strap,
VAD2 / strap,
VAD1 / strap,
VAD0 / strap
VLPAR
VBE#

VUPCMD
VUPSTB
VUPSTB#
VDNCMD
VDNSTB
VDNSTB#

V2
V1
R1

V3
R4
U1

P3

P1
U3 IO
R5 IO
T5 I
T2 I
T1 I
T3 O
R2 O
R3 O

IO

Address/Data Bus.
IO
IO

SB

Strap

IO
IO
IO
IO
IO

Function Setting (L=strap low, H=strap high) Register Pin
VAD3 GTL Pullup Enable L=Disable, H=Enable Rx50[6] SA19
VAD2 IOQ Depth L=1-Level, H=8-Level Rx50[7] SA18
VAD1 CPU FSB Clock Msb LL=66 MHz, LH=100 MHz Rx54[7] SA17
VAD0 CPU FSB Clock Lsb Hx=133 MHz Rx54[6] SA16

Parity.
Byte Enable.
Command from Client-to-Host.
Strobe from Client-to-Host.
Complement Strobe from Client-to-Host.
Command from Host-to-Client.
Strobe from Host-to-Client.
Complement Strobe from Host-to-Client.

Revision 2.06, December 1, 2004 -12- Pin Description

CLE266 Version CD / CE North Bridge Data Sheet

p

DDR Synchronous DRAM Memory Interface

Signal Name Pin # I/O Signal Description

MD[63:0]

MA[14-0]

CS[3:0]#

DQM[7:0]

DQS[7:0]# AB1, AE3, AD7, AF11,

SRAS#

SCAS#

SWE#

CKE[3:0]

(see pinout tables) IO Memory Data. These signals are connected to the DRAM data bus.

Output drive strength may be set by Device 0 Rx6D[1-0].

AC19, AC17, AD6, AB6,

AC6, AB17, AC16, AB16,

O Memory Address. DRAM address lines. Output drive strength may

be set by Device 0 Rx6C[7-6].

AD14, AC14, AC13, AB13,

AC11, AD11, AD10

W4, AC3, Y3, AA4 O Chip Select. Chip select of each bank. Output drive strength may be

set by Device 0 Rx6D[3-2].

AB2, AF3, AF7, AE11,

AC15, AF18, AD22, AD25

O Data Mask. Data mask of each byte lane. Output drive strength may

be set by Device 0 Rx6D[5-4].

IO DDR Data Strobe. Data strobe of each byte lane. Output drive

AD15, AE18, AF22, AD26

strength may be set by Device 0 Rx6C[3-2].

AD5 O Row Address Command Indicator. Output drive strength may be

set by Device 0 Rx6C[7-4].

AB4 O Column Address Command Indicator. Output drive strength may

be set by Device 0 Rx6C[7-4].

AB5 O Write Enable Command Indicator. Output drive strength may be

set by Device 0 Rx6C[7-4].

AD23, AC21, AC22, AC20 O Clock Enables. Clock enables for each DRAM bank for powering

down the SDRAM or clock control for reducing power usage and for
reducing heat / temperature in high-speed memory systems. See
Device 0 Rx6B[4].

SMB / I2C Interface

Signal Name Pin # I/O Signal Description

SPCLK[2:1]

SPDAT[2:1]

A8, E9 IO Serial Port (SMB/I2C) Clocks. These are the clocks for serial data

transfer. SPCLK1 is typically used for DDC communications with a
CRT monitor. As an output, it is programmed via CRA0[0]. As an
input, its status is read via CRA0[2]. In either case the serial port
must be enabled by CRA0[4] = 1. SPCLK2 is typically used for I
communications. As an output, it is programmed via CRB1[0]. As
an input, its status is read via CRB1[2]. The port is enabled via
CRB1[4] = 1.

C9, D9 IO Serial Port (SMB/I2C) Data. These are the data signals used for

serial data transfer. SPDAT1 is typically used for DDC
communications with a CRT monitor. As an output, it is

rogrammed via CRA0[1]. As an input, its status is read via
CRA0[3]. In either case the serial port must be enabled by CRA0[4]
= 1. SPDAT2 is typically used for I
output, it is programmed via CRB1[1]. As an input, its status is read
via CRB1[3]. The port is enabled via CRB1[4] = 1.

2

2

C communications. As an

C

Revision 2.06, December 1, 2004 -13- Pin Description

CLE266 Version CD / CE North Bridge Data Sheet

Digital Monitor (DVI) Interface

Signal Name Pin # I/O Signal Description

DVID11 / TVD11,
DVID10 / TVD10,
DVID09 / TVD9,
DVID08 / TVD8,
DVID07 / TVD7,
DVID06 / TVD6,
DVID05 / TVD5,
DVID04 / TVD4,
DVID03 / TVD3,
DVID02 / TVD2,
DVID01 / TVD1,
DVID00 / TVD0

DVICLK / TVCLK C2 O Digital Monitor Clock Out. Internally pulled down during reset
DVIHS / TVHS B1 O Digital Monitor Horizontal Sync. Internally pulled down during reset
DVIVS / TVVS A1 O Digital Monitor Vertical Sync. Internally pulled down during reset
DVIDE / TVBL# D5 O Digital Monitor Display Enable. Indicates valid data on DVID[11:0]. Internally

DVIDET / NC C1 I Digital Monitor Detect. Rx?? will read 1 if a digital monitor is connected. Must be

D6
C6
A5
B5
C5
A4
B4
C4
A3
B3
A2
B2

O Digital Monitor Data Out. Internally pulled down during reset

pulled down during reset

tied to GND if not used.

TV Encoder Interface

Signal Name Pin # I/O Signal Description

TVD11 / DVID11,
TVD10 / DVID10,
TVD9 / DVID09,
TVD8 / DVID08,
TVD7 / DVID07,
TVD6 / DVID06,
TVD5 / DVID05,
TVD4 / DVID04,
TVD3 / DVID03,
TVD2 / DVID02,
TVD1 / DVID01,
TVD0 / DVID00

TVCLKR / NC C3 I TV Encoder Clock In. Input clock from encoder. Internally pulled down.
TVCLK / DVICLK C2 O TV Encoder Clock Out. Output clock to TV encoder. Internally pulled down.
TVHS / DVIHS B1 O TV Encoder Horizontal Sync. Internally pulled down during reset
TVVS / DVIVS A1 O TV Encoder Vertical Sync. Internally pulled down during reset
TVBL# / DVIDE D5 O TV Encoder Blanking. Internally pulled down during reset

D6
C6
A5
B5
C5
A4
B4
C4
A3
B3
A2
B2

O TV Encoder Data. Internally pulled down during reset

Revision 2.06, December 1, 2004 -14- Pin Description

CLE266 Version CD / CE North Bridge Data Sheet

CRT Interface

Signal Name Pin # I/O Signal Description

AR
AB
AG
HSYNC
VSYNC
RSET

C10 A Analog Red. Analog red output to the CRT monitor.
A10 A Analog Blue. Analog blue output to the CRT monitor.
B10 A Analog Green. Analog green output to the CRT monitor.

A9 O Horizontal Sync. Output to CRT.
B9 O Vertical Sync. Output to CRT.

A11 A

Reference Resistor. Tie to GNDRGB through an external 147 Ω
control the RAMDAC full-scale current value.

± 1% resistor to

Direct LCD Panel Interface

Signal Name Pin # I/O Signal Description

Flat Panel Data Out. Bits 8-22 also function as strap inputs that are sampled on the

FPD23 / DFDET,
FPD22 / DFD11 / strap,
FPD21 / DFD10 / strap,
FPD20 / DFD09 / strap,
FPD19 / DFD08 / strap,
FPD18 / DFD07 / strap,
FPD17 / DFD06 / strap,
FPD16 / DFD05 / strap,
FPD15 / DFD04 / strap,
FPD14 / DFD03 / strap,
FPD13 / DFD02 / strap,
FPD12 / DFD01 / strap,
FPD11 / DFD00 / strap,
FPD10 / DFDE / strap,
FPD9 / DFHS / strap,
FPD8 / DFVS / strap,
FPD7 / CPD15,
FPD6 / CPD14,
FPD5 / CPD13,
FPD4 / CPD12,
FPD3 / CPCK1,
FPD2 / CPD11,
FPD1 / CPD10,
FPD0 / CPD09

FPVS / CPVS F3 O Flat Panel Vertical Sync. Internally pulled down.
FPHS / CPHS F2 O Flat Panel Horizontal Sync. Internally pulled down.
FPDE / CPD08 F1 O Flat Panel Data Enable. Internally pulled down.
FPCLK / DFCLK J3 O Flat Panel Clock. Internally pulled down during reset.
ENVDD
ENVEE

ENBLT

N4
N2
N1

N3
M3
M1
M2
M4

L1

L2

L3

L4

K4

K1

K2

K3

J1

J2
H1
H2
H3
G1
G2
G3

G4 O Enable VDD. This signal is driven high to initiate a flat panel power up sequence.
G5 O Enable VEE. This signal is driven high for a programmable time after ENVDD is

H5 O

O

rising edge of RESET#. These straps are defined per the table below. “L” indicates

O

strap low (4.7KΩ to ground), “H” = strap high (4.7KΩ to 10KΩ t 3.3V). See Design

O

Guide for details.

O
O

Strap

O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O

Function Setting Register

FPD22 Reserved for Test Always Strap Low –

FPD21-20 TV Mode LL=PAL, LH=NTSC, EXSR13[4:3]
HL=PAL-N, HH=PAL-NC
FPD19 TV # of Lines L=525 Lines, H=625 Lines EXSR12[6]

FPD18 DVI Port Configuration L=DVI, H=TV EXSR12[5]
FPD17 Panel Interface Config L=DVI / Capture, H=Panel EXSR12[4]
FPD16-13 Panel Type Customer Defined (contact VIA) EXSR12[3:0]

FPD12 Reserved for Test Always Strap Low –
FPD11 Reserved for Test Always Strap Low –
FPD10 Reserved for Test Always Strap Low –
FPD9 Reserved for Test Always Strap Low –
FPD8 Reserved for Test Always Strap Low –

driven high during a flat panel power up sequence.
Enable Backlight.

Revision 2.06, December 1, 2004 -15- Pin Description

CLE266 Version CD / CE North Bridge Data Sheet

Video Capture Interface

Signal Name Pin # I/O Signal Description

I

CPD15 / FPD7,
CPD14 / FPD6,
CPD13 / FPD5
CPD12 / FPD4,
CPD11 / FPD2,
CPD10 / FPD1,
CPD09 / FPD0
CPD08 / FPDE
CPD07
CPD06
CPD05
CPD04
CPD03
CPD02
CPD01
CPD00

CPVS / FPVS F3 I Video Capture Vertical Sync. Internally pulled down.
CPHS / FPHS F2 I Video Capture Horizontal Sync. Internally pulled down.
CPCLK

CPCK1 / FPD3 H3 I Video Capture Clock 1. Clock for capture data inputs 8-15 when used as a second 8-bit

Note: The Video Capture Port may always be used in 8-bit input mode. The “upper” data bits (CPD[15:8] may be used as a 16-bit

extension or as a second 8-bit port if the 24-bit direct flat panel interface is not used.

J1

J2
H1
H2
G1
G2
G3

F1
F4
E4
E1

E2
D1
D2
D3
D4

E3 I Video Capture Clock 0. Clock for capture data inputs 0-7 (or 0-15 when capture port is

Flat Panel Data Out.

configured as 16-bit)

capture port.

Alternate Digital Monitor (DVI) Interface

Signal Name Pin # I/O Signal Description

O

DFD11 / FPD22,
DFD10 / FPD21,
DFD09 / FPD20,
DFD08 / FPD19,
DFD07 / FPD18,
DFD06 / FPD17,
DFD05 / FPD16,
DFD04 / FPD15,
DFD03 / FPD14,
DFD02 / FPD13,
DFD01 / FPD12,
DFD00 / FPD11

DFCLK / FPCLK J3 O Digital Monitor Clock. Internally pulled down during reset.
DFHS / FPD9 K2 O Digital Monitor Horizontal Sync. Internally pulled down during reset
DFVS / FPD8 K3 O Digital Monitor Vertical Sync. Internally pulled down during reset
DFDE / FPD10 K1 O Digital Monitor Display Enable. Indicates valid data on DFD[11:0]. Internally pulled down

DFDET / FPD23 N4 O Digital Monitor Detect. Rx?? will read 1 if a digital monitor is connected. Must be tied to

Note: All “DFxxx” pins perform the same function as the “DMxxx” pins (the other DVI interface muxed with the TV-out pins).

N2
N1
N3

M3
M1
M2
M4

L1

L2

L3

L4
K4

Digital Monitor Data Out.

during reset

GND if not used.

Revision 2.06, December 1, 2004 -16- Pin Description

CLE266 Version CD / CE North Bridge Data Sheet

b

p

Clocks, Resets, Power Control, General Purpose I/O, Interrupts and Test

Signal Name Pin # I/O Signal Description

HCLK

MCLK

MCLKFB
DCLKI

DCLKO

XIN

RESET#

PWROK

SUSST#

INTA#

AGPBUSY#

GPIO0
GPIO1
GPIO2
GPIO3

AGPSTOP#

AGPSTDBY

AGPSUSP

GCLK
BISTIN

DFTIN

NC

Y23 I Host Clock. This pin receives the host CPU clock (100 / 133 MHz). This clock is

used by all CLE266 logic that is in the host CPU domain.

AB23 O Memory (SDRAM) Clock. Output from the internal clock generator to the

external clock buffer.

AC23 I Memory (SDRAM) Clock Feedback. Input from the external clock buffer.

H4 I Dot Clock (Pixel Clock) In. Used for external EMI reduction circuit if used.

Loop back from DCLKO if external EMI reduction circuit not implemented.

J4 O Dot Clock (Pixel Clock) Out. Used for external EMI reduction circuit if used.

Loop back to DCLKI if external EMI reduction circuit not implemented.

E12 I Reference Frequency Input. 14.31818 MHz reference clock input for the internal

graphics controller Phase Locked Loops (PLLs). All internal graphics controller
clocks are synthesized on chip using this frequency as a reference.

W3 I Reset. When asserted low, this signal resets the internal logic of the chip and sets

all register bits to their default values. The rising edge of this signal is used to
sample all power-up strap options. Normally driven by the South Bridge.

W1 I Power OK. When asserted high, this signal indicates that system voltages are

correct and stable. Driven by on­the chipset South Bridge.

W2 I Suspend Status. For implementation of the Suspend-to-DRAM feature.

Normally driven by the South Bridge. Connect to an external pullup if not used.

B6 O Interrupt. PCI interrupt output (handled by the interrupt controller in the South

Bridge)

B8 O AGP Interface Busy. Connect to a South Bridge GPIO pin for monitoring the

status of the internal AGP bus. See CLE266 Design Guide for details.

D7 O

E7 O

D8 O

E8 O
C8 I AGP Stop. Assert low to stop the internal AGP interface (for power measurement

A7 I AGP Standby. Assert high to put the internal AGP interface into standby mode

C7 I AGP Suspend. Assert high to put the internal AGP interface into suspend mode

P4 I Graphics Clock. 66 MHz clock from system clock synthesizer.
B7 I BIST (Built-In-Self-Test) In. This

A6 I DFT (Design-For-Test) In. This pin is used for testing and must be tied low on

AB10, AC10 – No Connect. Do not connect. Reserved for future use.

General Purpose Input / Output 0.
General Purpose Input / Output 1.
General Purpose Input / Output 2.
General Purpose Input / Output 3.

only, not used in normal operation)

(for power measurement only, not used in normal operation)

(for power measurement only, not used in normal operation)

all board designs.

all board designs.

oard Power Good circuitry. Also connected to

in is used for testing and must be tied low on

Revision 2.06, December 1, 2004 -17- Pin Description

CLE266 Version CD / CE North Bridge Data Sheet

Power, Ground and Test

Signal Name Pin # I/O Signal Description

VTT

GTLVREF

VCCM
MEMVREF
VCCVL
VLCOMP
VLVREF

VCC25
VSUS25
VCCHCK
VCCMCK
VCCFP
VCCRGB
VCCDAC
VCCPLL1
VCCPLL2
VCCPLL3
GND
GNDHCK

GNDMCK

GNDRGB
GNDDAC
GNDPLL1
GNDPLL2
GNDPLL3

(see pin list) P Power for CPU I/O Interface Logic. Voltage is CPU dependent. See CLE266

Design Guide for details.

E20, T22 P CPU Interface GTL+ Voltage Reference. 2/3 VTT ±2% typically derived using a

resistive voltage divider. See CLE266 Design Guide for details.
(see pin list) P Power for Memory I/O Interface Logic. 2.5 ±5%.
AB7, AB20 P

P7, R7, T7, U5, V5 P Power for V-Link I/O Interface Logic. 2.5V ±5%.

V4 I V-Link P-Channel Compensation. Connect 70 Ω 1% resistor to ground.
T4 P V-Link Voltage Reference. 0.9V derived using a resistive voltage divider between

(see pin list) P Power for Internal Digital Logic. 2.5V ±5%.

W5 P Suspend Power. 2.5V ±5%.
AA24 P Power for Host CPU Clock DLL. 2.5V ±5%.
AB24 P Power for Memory Clock DLL. 2.5V ±5%.

(see pin table) P Power for Flat Panel, DVI, TV-Out and Video Capture Interfaces. 3.3V ±5%.

D10 P Power for CRT RGB Outputs. 2.5V ±5%.
C11 P Power for DAC Digital Logic. 2.5V ±5%.
B12 P Power for Graphics Controller PLL 1. 2.5V ±5%.
D12 P Power for Graphics Controller PLL 2. 2.5V ±5%.
C13 P Power for Graphics Controller PLL 3. 2.5V ±5%.

(see pin table) P Ground for Internal Digital Logic. Connect to primary PCB ground plane.

Y24 P Ground for Host CPU Clock Circuitry. Connect to main ground plain through a

AC24 P Ground for Memory Clock Circuitry. Connect to main ground plain through a

B11 P
D11 P
A12 P
C12 P
A13 P

Memory Voltage Reference.

VCC25 and ground (see Design Guide for details).

ferrite bead.

ferrite bead.

Connection Point for RGB Load Resistors.
Ground for DAC Digital Circuitry.
Ground for Graphics Controller PLL 1.
Ground for Graphics Controller PLL 2.
Ground for Graphics Controller PLL 3.

Revision 2.06, December 1, 2004 -18- Pin Description