How it Works
Vestel
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SAT3600
Schematic
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Vestel SAT3600 Schematic

VESTEL STB

SERVICE MANUAL

SATELLITE STB
MODELS
SAT 3600 SAT 3700 SAT 3701 SAT 3702 SAT 3703 SAT 3800 SAT 3801 SAT 3802
SERVICE MANUAL

SATELLITE STB MODELS

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REVISION HISTORY .................................................................................................................................................................6
I5518 (IC100)........................................................................................................................................................................7
ST SDRAM 8MB F
LASH MEMORY 1 MBYTE (IC301)........................................................................................................................................23
EEPROM
YTE (IC300)......................................................................................................................................................23
S 128K (16,384 X 8) 2-WIRE SERIAL (IC302).........................................................................................................25
USED IC LISTS .......................................................................................................................................................................... 33
CONNECTORS..................................................................................................................... ..................................................... 34
P
OWER CONNECTOR..................................................................................................................................................................34
F
RONT PANEL CONNECTOR ....................................................................................................................................................... 34
5512 JTAG C
ONNECTORS.........................................................................................................................................................34
SCART CONNECTION........................................................................................................................................................... 35
TV S
CART SOCKET...................................................................................................................................................................35
CART SOCKET................................................................................................................................................................36
VCR S RS232 S RCA (A
ERIAL PORT..................................................................................................................................................................36
UDIO AND COMPOSITE VIDEO) CONNECTOR................................................................................................................. 36
POWER REQUIREMENTS......................................................................................................................................................37
PCB EXPLANATIONS..............................................................................................................................................................37
INTRODUCTION................................................................................................................................................................... 37
POWER BOARD (16PW07 E3) ............................................................................................................................................ 37
MAIN BOARD (16MB07 E3 ) ............................................................................................................................................... 38
FRONT PANEL BOARD (TK507-2)....................................................................................................................................39
SERVICE MENU INTERFACE...............................................................................................................................................40
RF M
ODULATOR SYSTEM :........................................................................................................................................................40
ODULATOR TYPE : ............................................................................................................................................................ 40
RF M T
UNER TYPE :............................................................................................................................................................................40
S
CARTS :.................................................................................................................................................................................... 40
R
EBOOT :................................................................................................................................................................................... 40
C
LEAR DATABASE :...................................................................................................................................................................41
L/R: DBC
OWNLOAD PGM : ...................................................................................................................................................................42
D R
EMOTE/FRONT TEST : .............................................................................................................................................................. 42
7-S S
YSTEM DIAGNOSTIC :............................................................................................................................................................... 43
D
EVELOPMENT TEAM :..............................................................................................................................................................43
U
PLOAD DEFAULT SAT_XPDRS :...............................................................................................................................................43
OWNLOAD DEFAULT SAT_XPDRS :......................................................................................................................................... 43
D R
S232 TEST :.............................................................................................................................................................................44
OPY – OK: UPLOAD PGM :....................................................................................................................................... 41
EGMENT DISPLAY TEST :......................................................................................................................................................43
SOFTWARE UPGRADE THROUGH RS232.........................................................................................................................45
SCHEMATICS............................................................................................................. ERROR! BOOKMARK NOT DEFINED.
BILL OF MATERIALS.............................................................................................................................................................48
BOARD LAYOUT.......................................................................................................ERROR! BOOKMARK NOT DEFINED.
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REVISION HISTORY

Rev 1.0 07/25/02 Tuncay Akkurt Initial Revision
Schematics
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SERVICE MANUAL

GENERAL DESCRIPTION

Major functional blocks are discussed briefly in this section. A more detailed description is contained later in the document.

STi5518 (IC100)

1. Introduction

The STi5518 integrates in a single chip: a transport dem ultiplex block; an ST20 32-bit system CPU; an audio/video MPEG2 decoder; display and gr aphics features; a digi tal video encoder; and s ystem peripherals. The Sti5518 integrates D irecTV and D VB desc ram blers in the tra nsport demultip lex block , allowin g it to be used in b oth Digital Video Broadcasting (DVB) and Digital Satellite System (DSS) set-top box applications.

2. Technical Specification

Integrated 32-bit host CPU up to 81 MHz
2 Kbytes of Icache, 2 Kbytes of Dcache, and 4 Kbytes of SRAM configurable as Dcache.
Audio decoder
5.1 channel Dolby Digital® /MPEG-2 multi-channel decoding, 3 X 2-channel PCM outputs IEC60958 -IEC61937 digit al out put SRS®/TruSurround® DTS® digital out and MP3 decoding Alignment beep for satellite dishes.
Video decoder
Supports MPEG-2 MP@ML Fully programmable zoom-in and zoom-out NTSC to PAL conversion.
DVD and SVCD subpicture decoder
High performance on-screen display
2 to 8 bits per pixel OSD options Anti-flicker, anti-flutter and anti-aliasing filters.
PAL/NTSC/SECAM encoder
RGB, CVBS, Y/C and YUV outputs with 10-bit DACs Macrovision® 7.01/6.1 compatible (optional).
Shared SDRAM memory interface
1 or 2x16-Mbit, or 1x64-Mbit 125 MH
Programmable CPU memory interface for SDRAM, ROM, peripherals...
Front-end interface
DVD, VCD, SVCD and CD-DA compatible
Z SDRAM.
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Serial, parallel and ATAPI int er f ac es Hardware sector filtering Integrated CSS decryption and track buffer.
Hardware transport-stream demultiplexor
Parallel/serial input DES and DVB descramblers 32 PID support.
Integrated peripherals
2 UARTs, 2 SmartCards, I
2C controller, 3 PWM outputs, 3 capture timers
Modem support 44 bits of programmable I/O IR transmitter/receiver.
Professional toolset support
ANSI C compiler and libraries.
208 pin PQFP package.
The STi5518 is a hig hly integrated single-chip deco der, d es ig ned f or use in feature-rich mass-market set-top boxes. It integrates a high-performance 32-bit CPU, a dedicated block for DVB/DirecTV transport demultiplexing and descrambling, modules for MPEG-2 video and audio decoding with 3D-surround and MP3 support, advanced display and graphics features, a digital video encoder and all of the system peripherals required in a typical low-cost interactive receiv er. To cover t he needs of DVD-capable s et-top boxes , ST i5518 integr ation opt ions incl ude a CS S decryption block, a Dolby Digital audio decoder and Macrovision copy protection. An ATAPI interface is built-in, supporting the glueles s c onnection of s tandar d Hard Dis k Drives. I n this wa y, the ST i551 8 is id eal for set- top boxes featuring trick modes such as live TV recording , pausing and time-shif ting. The STi5518 is backward compatible with the popular STi5500 set-t op box deco der, all owing eas y migrat ion from the previous generation. T he high level of integration in a single PQFP-2 08 pac kage makes the STi5518 ideally suited fo r lo w-c os t, h ig h-vol ume set-top box applications.
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3. Architecture overview
The figure below shows the architecture of the Sti5518. This chapter gives a brief overview of each of the functional blocks of the STi5518.

4. STi5518 functional modules

a. Central processor
The STi5518 Central Processing Unit is a ST20C2+ 32-bit processor core. It contains instruction processing logic, instruction and data pointers, and an operand regist er. It directly accesses the high-s peed on-chip SRAM, which can store data or programs and uses the cache to reduce access time to off-chip program and data memory. The processor can access memory via the Programmable CPU Interface (often referred to as the EMI) or the Shared Memory Interface (SMI), which is shared with the video, audio, sub-picture and OSD decoders.
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b. MPEG video decoder
This is a real-time video compression processor supporting the MPEG-1 and MPEG-2 standards at video rates up t 720 x 480 x 60 Hz and 720 x 576 x 50 Hz. Picture format conversion for display is performed by vertical and horizontal filters. User- defined bitmaps can be super -impos ed on the d isplay pictur e b y using the on- screen d isplay function. The display unit is part of the MPEG vide o decoder, it overla ys the f our displa y planes shown i n the figure below. The display planes are norm ally overlaid in the ord er illustrated, with the background color at the back and the sub-picture at the f ront (us ed as a curs or p lane). T he s ub-pic ture pla ne ca n a ltern ativel y be posi tioned bet ween the OSD and MPEG video planes where it can be used as a second on-screen display plane.
c. Audio decoder
The audio decoder accepts: Dolby Digital, MPEG-1 layers I, II and III, MPEG-2 layer II 6-channel, PCM, CDDA data formats; MPEG2 PES streams for MPEG-2, MPEG-1, Dolby Digital, MP3, and Linear PCM (LPCM). The audio decoder supports DTS® digital out (DVD DTS and CDDA DTS). SPDIF input data (IEC-60958 or IEC-61937 standards) is accepted if an external circuitry extr acts the PCM clock from the str eam. Skip frame, repeat block s and soft mute frame features can be used to synchronize audio and video data. PTS audio extraction is also supported. The devic e outputs up to 6 channels of PCM data and appr opriate clocks for ex ternal digital-to-anal og converters. Program mable downmix enables 1,2, 3 or 4 channel outputs. D ata can be output in either I²S f ormat or Sony format. The decoder can form at output data according t o IEC-60958 s tandard (for non c ompress ed data: L/R channels, 16, 18, 20 an d 24-bits) or IEC-6193 7 standar d (for com pres sed data), for F or 32 kHz. Sampling frequenc i es of 96 kHz, 48 kHz, 44.1 kHz, 32 kHz and half sampling frequencies are supported. A downsampling f ilter (9 6 kHz/48 kHz) is available. T he decoder supports dual mode for MPEG an d Do lby Digital. It includes a Dolby surround compatible downmix and a ProLogic decoder. A pink noise generator enables the accurate positioning of speakers for optim al surround sound s etup. PCM be ep tone is a s pecial m ode used for S et Top Box. It generates a triangular signal of variable frequency and amplitude on the left and right channels. In global mute mode, the decoder decodes the incoming bitstream normally but the PCM and SPDIF outputs are softmuted. This mode is used to prepare a period of decoding mode, to synchronize audio and video data without hearing the audio. S low-forward and fast-forward tr ick modes are available f or compressed and n on-compressed data. The control interface of the decoder is activated via memory mapped registers in the ST20 address space.
S = 96 kHz, 48 kHz, 44.1 k Hz
d. IR transmitter/receiver
The STi5518 provides a pulse-position modulated signal for automatic VCR programming by the set-top box. The signal is output to the IR blast pin and an accessory jack pin, simultaneously. The pulse frequency, number of pulses (envelope length) and the total cycle time is controlled by registers.
e. Modem analog front-end interface
The Modem Analog Front- end interface is used to trans fer transmit and receive D AC and ADC samples bet ween the memory and an external modem analog front-end (MAFE), using a synchronous serial protocol. DMA is used to transfer the sample data between memory buffers and the MAFE interface module, with separate transmit and receive buffer s and double buf fering of the buf fer pointer s. FIFOs are us ed to tak e into account the ac cess laten cy to memory, in a worst c ase system and to all ow the use of bursts for m emory bandwidth eff iciency improvem ent. The V22 bis standard is supported.
f. Memory subsystem
On-chip
The on-chip memory includes 2K bytes of instruction c ache, 2Kbytes of data cache and 4 Kbytes of SRAM th at can be optionally configured as data cache. The subsystem provides 240M/bytes of internal bandwidth, supporting pipelined 2- cycle internal m emory access. The instruction a nd data caches are direct-m apped, with a write-back system for the data-c ache. The caches support bur st accesses to the external memories for refill and write-back. Burst access increases the performance of pagemode DRAM memories.
Off-chip
There are two off-chip memory interfaces:
• The external memory interface (EMI) accessed by the ST20 is used for the transfer of data and programs
between the STi5518 and external peripherals, flash and additional SDRAM and DRAM.
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• Shared memory interface (SMI) controls the movement of data between the STi5518 and 16, 32 or 64 Mbits of
SDRAM. This external SDRAM stores the display data generated by the MPEG decoder and CPU and the C2+ code data. The EMI uses minimal external support logic to support memory subsystems, and accesses a 32 Mbytes of physical address space (greater if SDRAM or DRAM is used) i n four ge nera l purpos e m emor y banks of 8 or 16 b its wide, 21 or 22 address lines, an d byte select. F or applications req uiring extra m emory, the EMI su pports this extra memor y with zero external support logic , even for 16-bit SDRAM devices. The EMI c an be configured for a wide variety of timing and decode functions b y the conf igurat ion regis ters. The t im ing of each of the four m em or y banks c an be set separately, with different device types being placed in each bank with no need for external hardware.
g. Serial communication
Asynchronous serial controllers
The Asynchronous Serial Controller (ASC), also referred to as the UART interface, provides serial communication between the STi5518 and other microcontrollers, microprocessors or external peripherals. The STi5518 has four ASCs, two of which are generally used by the SmartCard controllers.
Eight or nine bit data transfer, parity generation, and the number of stop bits are programmable. Parity, framing, and overrun error detection increase data transfer reliability. Transmission and reception of data can be double-buffered, or 16-deep FIFOs can be used. A mechanism to distinguish the address from the data bytes is included for multiprocessor comm unication. Testing is supported by a loop-back option. A 16-bit baud-rate generator provides the ASC with a separate serial clock signal.
Two ASCs support full-duplex and 2 half-duplex asynchronous communication, where both the transmitter and the receiver use the same data fram e format and the sam e baud rate. Each A SC can be set to operate in SmartCard mode for use when interfacing to a SmartCard.
Synchronous serial controller
Two Synchronous Serial Controllers (SSC) provide high-speed interfaces to a wide variety of serial memories, remote control recei vers and other microcontrol lers. The SSCs support all of the features of the Serial Peripher al Interface bus (SPI) a nd the I SSCs share pins with the parallel input/output (PIO) ports, and support half-duplex synchronous communication.
h. Front-end interface
The STi5518 can be connected to a front-end through the following interfaces:
2C bus. The SSCs c an be program med to interf ace to other serial b us standar ds. The
• I2S interface;
• multi-format serial interface;
• multi-format parallel interface;
• ATAPI interface (for Hard Disk Drives and DVD-ROMs)
i. On-chip PLL
The on-chip PLL accepts 27 MHz input and generates all the internal high-frequency clocks needed for the CPU, MPEG and audio subsystems.
j. Diagnostic controller (DCU)
The ST20 Diagnostic Controller Unit (DCU) is used to boot the CP U and to c ontro l a nd monitor the chip systems via the standard IEEE 1194.1 Test Acc ess Port. The DCU includes on-chip hard ware with ICE (In Circuit Emulation) and LSA (Logic State Analyzer) featur es to facilitate verificati on and debugging of softwar e running on the on-c hip CPU in real time. It is an independent hardware module with a private link from the host to support real-time diagnostics.
k. Interrupt subsystem
The interrupt system allows an on-chip module or external interrupt pin to interrupt an active process so that an
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interrupt handling process can be run. An interrupt can be signalled by one of the following: a signal on an external interrupt pin, a signal from an internal peripheral or subsystem, software asserting an interrupt in the pending register. Interrupts are im plemented by an on-chip interrupt controll er and an on-ch ip interrupt-level co ntroller. The interrupt controller s upports eight prioritized inter rupts as inputs and manag es the pending interrupts. Th is allows the nesting of pre-em ptive interrupts for real-time system design. Each interrupt can be programmed to be at a lower or higher priority than the high priority process queue.
l. PAL/NTSC/SECAM encoder
The integrated digital encoder converts a multiplexed 4:2:2 or 4:4:4 YCbCr stream into a standard analog baseband PAL/NTSC or SECAM signal and into RGB, YUV, Yc and CV BS components. The encoder can perform closed­caption, CGMS encoding, and a ll o ws M ac rovision
TM 7.01/6.1 copy protection. The DENC is able to encode Tele tex t
according to the “CCIR/ITU-R Broadcast Teletext System B” specification, also known as “World System Teletext”. In DVB applicatio ns, Teletext data is em bedded within D VB stream s as MPEG d ata packets . It is the respons ibility of the software to han dle incoming data p ackets and in partic ular to store T eletext packets in a buf fer, which the n passes them to the DENC on request.
m. SmartCard interfaces
Two SmartCard interfaces support SmartCards compliant with ISO7816-3. Each interface is has a UART (ASC), a dedicated programmable clock generator, and eight bits of parallel IO port.
n. PWM and counter module
The PWM and counter module provides three PWM encoder outputs, three PWM decoder (capture) inputs and four programmable timer s. Each capt ure input can be programmed to detect r ising edge, falling edge, both edges or neither edge (disabled) . These facilities are c locked by two indep endent clocks , one for PWM outputs and one for capture inputs/timers. The PWM counter is 8-bit, with 8-bit registers to set the output-high time. The capture/compare counter and the compare and capture registers are 32-bit. The module generates a single interrupt signal.
o. Parallel I/O module
44 bits of parallel I/O are configured in 6 ports, and each bit is programmable as output or input. The output can be configured as a totem-pole or open- drain driver. The input com pare logic can ge nerate an interr upt on any chan ge of any input bit. Many parallel IO have alt ernate functions and can be connected to an int ernal peripheral signal such as a UART or SSC.
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5. Pin list sorted by function
Alternate functions printed in Italic show a suggested use of the PIO; alternate functions not printed in Italic are multiplexed with a specific hardware.
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1. FEI_CFG bits 8 and 9 must be programmed according to the required NRSS configuration.
2. The NRSS_IN and NRSS_OUT pins are swapped around on the STi5518 compared to the STi5508.
3. Register LNK_SDAV_CONF bit 22 (SDE) must be set to 1 to validate the output path.
4. Inverted. ATTENTION! the PIO input is also inverted.
5. The PIO must be configured in open drain.
6. BOOT_FROM_ROM is active during reset.
7. Tie low whenever JTAG is not used.
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