Vestel AV2500, AV2600 Schematic
AV2500/2600
DIGITAL HOME
ENTERTAINMENT SYSTEM
SERVICE MANUAL
1. GENERAL DESCRIPTION
1.1 ES680X Vibratto-II CL DVD Processor
DESCRIPTION
The ES6809 Vibratto™II CL processor is a single chip DVD system on chip with DivX®, MPEG-4,
and DVD video playback. The ES6809 integrates all front-end DVD servo control functions
including read channel, ECC, servo DSP, MCU for high performance disc read and a high quality
TV encoder for a brilliant 480p/576p progressive scan video output with Macrovision™ copy
protection. The ES6809 is an ideal solution for stand-alone DVD players, DVD receivers,
DVD/VCR combos and DVD A/V minicomponent systems.
The ES6809 is built on the ESS proprietary dual CPU Programmable Multimedia Processor
(PMP) core consisting of 32-bit RISC and 64-bit DSP processors that deliver the best DVD
feature set. This PMP core, common through out all generations of Vibratto DVD products,
allows for easy migration from previous ESS based designs. The processing units enable
simultaneous parallel execution of system commands and data processing to perform specialized
encoding and decoding tasks. The vector engine performs audio and video processing to support
MPEG, Dolby®, DTS™, JPEG and DivX standards.
The front-end servo control of the ES6809 supports all popular optical pick-up units (OPU). Its
high performance error handling allows for playback of scratched and fingerprinted media. The
ES6809 has a unified memory architecture for both the front-end servo control and backend
decoder to achieve the lowest possible system memory cost.
The ES6809 has unmatched audio features including an integrated high quality stereo audio
digital to analog converter (DAC) and an analog to digital converter (ADC).
Additionally, the ES6809 supports DVD-Audio, CD-DA, HDCD, MP3, WMA, AAC, Dolby
ProLogic™ II digital audio formats and Karaoke.
The ES6809 CL DVD processor with DTS support is offered with the ES6809D, which has the
same pinout as the standard ES6809. The ES6809 and ES6809D processors are in 208-pin
Plastic Quad Flat Pack (PQFP) device package.
FEATURES
• DVD SoC incorporating all front-end DVD servo control and back-end DVD decode.
• DivX Home Theater quality video at full screen (D1).
• MPEG-4 Advanced Simple Profile* video.
• DVD-Audio multi-channel playback including MLP and 24-bit LPCM decode, CPPM decryption
and watermark detection
• DVD-Video, DVD-R/RW, DVD+R/RW, SVCD, VCD, CDROM, CD-R/RW, CD-DA.
• High-performance focusing, sledding, tracking and CLV/CAV spindle servo control.
• Integrated stereo audio DAC and audio ADC.
• Integrated NTSC/PAL encoder with pixel-adaptive deinterlacer
• Five 54 MHz VDACs for simultaneous composite, Svideo and YUV video outputs.
• Macrovision NTSC/PAL interlaced and progressive scan (480p/576p) video output
• Direct interface of 16-bit DRAM with up to 128-Mb capacity
• Direct interface for up to 4 banks of 8-bit EPROM or Flash memory with up to 4 MB per bank
• CCIR656/601 YUV 4:2:2 input/output
• OSD controller supports 256 colors in 8 degrees of transparency
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• Sub-picture Unit (SPU) decoder supports karaoke lyric, subtitles and EIA-608 compliant Line 21
captioning.
• Dolby Digital, Dolby ProLogic, and Dolby ProLogic II
• DTS Surround (ES6809D only)
• SRS TruSurround®
• MPEG Multichannel, AAC, MP3 and WMA.
• SPDIF digital audio input and output
• JPEG digital photo support (Kodak Picture CD™ and Fujifilm FujiColor CD™)
1.2 MEMORY
1.2.1 System SRAM Interface
The system SRAM interface controls access to optional external SRAM, which can be
used for RISC code, stack, and data. The SRAM bus supports four independent address spaces,
each having programmable bus width and wait states. The interface can support not only SRAM,
ROM/EPROM and memory-mapped I/O ports for standalone applications are also supported.
1.2.2 DRAM Memory Interface
The Vibratto-II CL provides a glueless 16-bit interface to DRAM memory devices used as
video memory for a DVD player. The maximum amount of memory supported is 16 MB of
Synchronous DRAM (SDRAM). The memory interface is configurable in depth to support 128-Mb
addressing. The memory interface controls access to both external SDRAM or EDO memories,
which can be the sole unified external read/write memory acting as program and data memory as
well as various decoding and display buffers.
1.3 FRONT PANEL
The front panel is based around an VFD and a common NEC (or compatible) front panel
controller chip, (uPD16311). The ES6809/ES6908 controls the uPD16311 using several control
signals, (clock, data, chip select). The infrared remote control signal is passed directly to the
ES680X for decoding.
1.4 Back PANEL
Outputs and Inputs at the AV2500/2600 back panel:
- Left, Right RCA audio outputs.
- Composite (CVBS RCA), SCART outputs.
- Input SCART
- 5x15W 4 ohms (L,R,SL,SR,C) + 1x25W 8ohms Subwoofer outputs.
- AM / FM Tuner Antenna input
- DAB Tuner Antenna input (AV2600)
- 220-240 V 50Hz AC Power input
There are 5 Video DACs for the CVBS and RGB. These video signals are buffered by external
video filter IC. (FMS 6145 Five Channel 4th Order Standard Definition Video Filter Driver)
Six channel PWM audio output by the ES680X IC. These 5.1 audio output amplified by a class-d
amplifier.
1 Caoxial S/PDIF input (RCA) and 1 optik S/PDIF output.
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2. SYSTEM BLOCK DIAGRAM and ES6808/09 PIN DESCRIPTION
4
ES6808/09 PIN DESCRIPTION
Names
1, 11, 20, 36, 45, 53, 63, 80,
VD33
AUX0
AUX3
RESET#
AUX1
DMA11:0
VSS
DRAS2-0#
DCS1-0#
VDD
DCAS#
DOE#
DWE#
DSCK
DQM
DB15-0
LA21-0
LWRLL#
LCS3-0#
LD7-0
LOE#
SPDIF_OUT
SPDIF_IN
VD33PLL
VS33PLL
VREF
COMP
RSET
FDAC
VDAC
VD33_DA
VS33_DA
YDAC
CDAC
UDAC
ADC_BIAS
MIC
ADC_CAP
TWS
TSD0
TSD1
Pin Numbers I/O Definitions
97, 122, 130, 156, 182, 197
2 I/O Host control 0.
3 I/O Auxiliary port 3.
4 I Reset (active-low).
5 I/O Host control 1.
6:9, 12:18, 21 O DRAM address bus.
10, 19, 27, 35, 44, 52, 62,
72, 79, 87, 96, 123, 133,
138, 183, 196, 201, 208
22, 23, 26 O DRAM row address strobes (active-low).
24, 25 O DRAM chip selects (active-low).
28, 73, 88, 134, 202 P Core power supply.
29 O DRAM column address strobe (active-low).
30 O DRAM output enable (active-low).
31 O DRAM write enable (active-low).
32 O Output clock to DRAM.
33 O Data input/output mask.
34, 37:43, 46:51, 54, 55 I/O DRAM data bus.
56:61, 64:67, 69:71, 74:78,
81:83, 101
68 O SRAM bus write enable (active-low).
84:86, 89 O SRAM bus chip select (active-low).
90:95, 98, 99 I/O SRAM data bus.
100 O RISC port output enable (active-low).
102 O S/PDIF output.
103 I S/PDIF input.
104 P Power for PLL blocks.
105 G Ground for PLL blocks.
106 I Internal voltage reference to video DAC.
107 I Compensation input.
108 I DAC current adjustment resistor input.
109 O Video DAC output.
110 O Video DAC output.
111 P Power for I/O power supply for VDAC.
112 G Ground for I/O power supply for VDAC.
113 O Video DAC output.
114 O Video DAC output.
115 O Video DAC output.
116 O Audio ADC bias voltage out.
117 I Audio ADC MIC 1.
118 O Audio ADC output capacitance.
119 O Audio transmit frame sync output.
120 O Audio transmit serial data port 0.
121 O Audio transmit serial data port 1.
P I/O power supply.
G Ground.
O SRAM address bus.
5
TSD2
TSD3
TBCK
TXD0
RXD0
MCLK
TXD1
RXD1
AUX3[5]
AUX3[0]
TX
RX
LDCO
LG
IP2
SDEN
SDATA
SCLK
DFCT
MIRR
LDON
BSUM
FE
CE
TE
RFENV
VREFOUT
VREFIN
DMO
FOO
SLO
RPBC
TRO
NC
TEBC
REFD
IN_M
IN
AVDD3
AVSS
DVCC
IP1
IDSEL
AMPSTBY
FGIN
CLOSESW
HOMESW
CLOSE
124 O Audio transmit serial data port 2.
125 O Audio transmit serial data port 3.
126 O Audio transmit bit clock.
127 I/O Serial port 0 transmit.
128 I/O Serial port 0 receive.
129 I/O Audio master clock for audio DAC.
131 I/O Serial port 1 transmit.
132 I/O Serial port 1 receive.
135 I/O Aux3 data I/O 5.
136 I/O Aux3 data I/O 0.
137 I Zero crossing of TE.
139 I Zero crossing of RF envelope.
140 O CD/DVD laser diode select.
141 O DVD-RAM land/groove flag for next track.
142 I DVD-RAM header position index 2.
143 O RF chip serial data enable.
144 I/O Data signal to/from RF chip.
145 O Serial clock source to RF chip.
146 I Defect flag input signal.
147 I Mirror detect input.
148 O Laser diode on/off control.
149 I Photodiode subbeam addition input signal.
150 I Focus input error signal.
151 I Center error input signal.
152 I Tracking error input.
153 I RF ripple envelope input signal.
154 I
155 I Reference voltage for servo analog input signals.
159 O Spindle drive.
160 O Focus drive.
161 O Sled drive.
162 O RF envelope balance control.
163 O Track drive.
164 O No connect.
165 O Tracking error balance control.
166 I Flash reference decouple.
167 I Analog RF signal (minus).
168 I Analog RF signal (plus).
169 P 3.3V analog power for flash.
170 G Analog ground for flash.
171 P 1.8V power for flash.
172 I DVD-RAM header position index 1.
173 I/O DVD-RAM detected signal of ID area.
174 O Power amplifier standby.
175 I Spindle hall sensor input.
176 I Tray closed detector.
177 I Sled home switch position detector.
178 O Drive to close tray.
Reference voltage for servo analog output
signals.
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OPENSW
OPEN
MDET
AUX7
AUX3[7]
EAUX1
AUX3[6]
EAUX0
EAUX3
EAUX2
VSYNC#
HSYNC#
XI
XO
AUX3[4]
AUX3[1]
AUX3[3]
AUX3[2]
AUX6-4, 2
179 I Tray open detector.
180 O Drive to open tray.
181 I Spindle drive motor rotation direction detect.
184 I/O Auxiliary port 7.
185 I/O Aux3 data I/O 7.
186 I/O Extended auxiliary port 1.
187 I/O Aux3 data I/O 6.
188 I/O Extended auxiliary port 0.
189 I/O Extended auxiliary port 3.
190 I/O Extended auxiliary port 2.
191 I/O Vertical sync (active-low); (5V tolerant input).
192 I/O Horizontal sync (active-low); (5V tolerant input).
193 I Crystal clock in.
194 O Crystal clock out.
198 I/O Aux3 data I/O 4.
199 I/O Aux3 data I/O 1.
200 I/O Aux3 data I/O 3.
203 I/O Aux3 data I/O 2.
204-207 I/O Auxiliary ports 2, 4, 5 and 6; (5V tolerant input).
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3. Audio Interface
The audio interface is a bidirectional serial port that connects to an external audio ADC/DAC for
the transfer of PCM (pulse coded modulation) audio data in I2S format. It supports 16-, 24-, and
32-bit audio frames. No external master clock is required.
The ES680X offers three audio interface modes:
1. Stereo mode using TSD0 pin 120.
2. Dolby Digital (AC-3) 5.1 channel mode using TSD[3:0] pins 120, 121, 124, and 125.
3. Dolby Digital (AC-3) 5.1 channel mode using S/PDIF pins 102 and 103.
AV2500/2600 Has also 5.1 channel Class-D amplifier outputs 5 x 4 ohms satelites and 1 x 8
ohms subwoofer.
4. Audio Performance
Table 36 lists the audio performance characteristics of the digital audio processor of the ES6809
under normal operating conditions (AVCC = 3.3V ?10%, DVCC =2.5?10%, TAMB 0 to 70?C).
Parameter Typical Unit
ADC Resolution 16 Bit
ADC Data Sample Rate 192 KHz
ADC Dynamic Range 80 dB
ADC THD 1 %
DAC Resolution 24 Bit
DAC Sample Rate 192 KHz
DAC THD+Noise 75 dB
DAC Dynamic Range 88 dB
DAC Bandwidth 20 KHz
5 VIDEO INTERFACE
Video Display Output
The video output section controls the transfer of video frames stored in memory to the internal TV
encoder of the Vibratto. The output section consists of a programmable CRT controller capable of
operating either in Master or Slave mode.
The video output section features internal line buffers which allow the outgoing luminance and
chrominance data to match the internal clock rates with external pixel clock rates, easily
facilitating YUV4: 2:2 to YUV4: 2:0 component and sample conversion. A polyphase filter
achieves arbitrary horizontal decimation and interpolation.
Video Bus
The video bus has 8 YUV data pins that transfer luminance and chrominance (YUV) pixels in
CCIR601 pixel format (4:2:2). In this format, there are half as many chrominance (U or V) pixels
per line as luminance (Y) pixels; there are as many chrominance lines as luminance.
Video Post-Processing
The Vibratto video post-processing circuitry provides support for the color conversion, scaling,
and filtering functions through a combination of special hardware and software. Horizontal upsampling and filtering is done with a programmable, 7-tap polyphase filter bank for accurate
non-integer interpolations. Vertical scaling is achieved by repeating and dropping lines in
accordance with the applicable scaling ratio.
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Video Timing
The video bus can be clocked either by double pixel clock and clock qualifier or by a single pixel
clock. The double clock typically is used for TV displays, the single for computer displays.
6 SDRAM MEMORY
The ES680X provides a glueless 16-bit interface to DRAM memory devices used as video
memory for a DVD player. The maximum amount of memory supported is 16 MB of
Synchronous DRAM (DRAM). The memory interface is configurable in depth to support 128-Mb
addressing.
Typical SDRAM Configurations:
The memory interface
controls access to both external
SDRAM or EDO memories, which
can be the sole unified external
read/write memory acting as
program and data memory as well
as various decoding and display
buffers. At high clock speeds, the
Vibratto memory bus interface
has sufficient bandwidth to support
the decoding and displaying of
CCIR601 resolution images at full
frame rate.
7 FLASH MEMORY
The decoder board supports AMD class Flash memories. Currently 4 configurations are
supported:
FLASH_512K_8b
FLASH_1024K_8b
FLASH_512Kx2_8b
FLASH_512Kx2_16b
The Vibratto permits both 8- and 16-bit common memory I/O accesses with a removable storage
card via the host interface.
8 SERIAL EEPROM MEMORY
An I2C serial EEPROM is used to store user configuration (i.e. language preferences,
speaker setup, etc.) and software configuration.. Industry standard EEPROM range in size from
1kbit to 256kbit and share the same IC footprint and pinout. The default device is 2kbit, 256kx 8,
SOIC8 SGS Thomson ST24C02M1 or equivalent.
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9 Digital Servo Controller
The digital servo includes an internal
DSP, on-chip RAM and ROM, control
logic, a loader interface, a serial
interface, and an on-chip ADC-DAC,
and interfaces with the MCU.
The MCU handles the high-level
functions of optical disk and front-end
system control. The interface between
the servo controller and the MCU is
illustrated in the Figure.
11 FRONT PANEL
VFD CONTROLLER
The VFD controller is a NEC uPD16311. This controller is not a processor, but does
include a simple state machine which scans the VFD and reads the front panel button matrix. The
16311 also includes RAM so it can store the current state of all the VFD icons and segments.
Therefore, the 16311 need only be accessed when the VFD status changes and when the button
status is read. The ES6808/ES6809 can control this chip directly using PIO pins or can allow the
front panel PIC to control the VFD.
12 RESET CIRCUITRY & VOLTAGE REGULATORS
Two different chips are supported to provide the power-on-reset DS1811 or AAT3520. (optional)
Voltage regulators:
U11: LM1117(1.8V) For 2V PLL power supply
U12: 7805 For 5V power supply
U13: LM1117(3.3V) For 3.3V power supply
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