Vestel 17MB26 Schematic

1. INTRODUCTION

Analog front end consist of a main tuner, a pip tuner and IF decoders. The PLL tuners
supply the IF signals and SAW filters are used for filtering and impedance matching between
demodulator ICs and tuners. The main IF signal is demodulated by demodulator (DRX3961A)
and the pip IF signal is demodulated by (TDA9885T). At the outputs of the demodulators, CVBS
and QSS signals are obtained.

The main tuner CVBS, pip tuner CVBS, FAV CVBS, Scart1 CVBS, SVHS_Y, Scart2
CVBS/Y, DMP CVBS, IDTV/Scart3 CVBS/Y signals are applied to the video matrix switch
(TEA6415). The outputs of the switch are main CVBS to video processor; pip CVBS to video
decoder, scart1_out CVBS to scart1, scart2_out CVBS to scart2, scart3_out CVBS to scart3.

The video decoder IC (VPC3230) decodes to CVBS signal for the pip picture. The source
for the pip picture can be CVBS from the video matrix switch, SVHS, Scart1, Scart2, Scart3 and
DMP. The output of the decoder is 8 bits ITU601_PIP signal connected to video processor IC
SVP LX66.

SVP-LX66 can support up to 1920x1080p panel. It consists of OSD, teletext, scaler,
deinterlacer, 8/10-bit dual LVDS transmitter and HDMI blocks. The inputs to SVP LX66 are
Scart2 RGB/DMP RGB, SC2/SC3 Chroma/SVHS Chroma, Scart1 RGB, main CVBS from video
matrix switch, YPbPr, ITU601_PIP, HDMI, ITU601_IDTV, PC RGB. The output is the 8bits
LVDS signal to the panel.The SVP LX66 uses a DDR RAM (EM6A9320) for faster processing.

The main controller IC is M16C-M30620SPGP. The I/O assignments are as follows:

NAME TYPE DESCRIPTION Port Pin

HDMI RELATED

1 HDMI_HPLG OUT HotPlug output for HDMI-1 source

P1.4 76

device

2 HDMI_HPLG2 OUT HotPlug output for HDMI-2 source

P8.0 22

device
3 HDMI_CEC IN (*) CEC input from HDMI cable P1.5 75
4 HDMI_DTC IN HDMI detection for first input P8.6 11
5 HDMI_DTC2 IN HDMI detection for second input P8.7 10
6 HDMI_DDC_WP OUT HDMI NVM write protect control for

P9.4 3

service
7 SCDT IN (*) Sync Change Detection for HDMI P8.4 18

POWER / PANEL RELATED

8 PROTECT IN Indicates the power supply status P1.7 73
9 STBY / CPU_GO OUT Controls the power supply on or off P1.3 77
10 BLIGHT /

OUT Controls the backlight P1.2 78

PDP_GO
11 DISP_EN OUT Controls the display enable or disable P1.1 79
12 BLIGHT_LVL PWM OUT Controls the backlight level P7.6 24
13 PANEL_VCC OUT Controls the power supply of the panel P1.0 80

SERIAL DATA COMMUNICATION

14 SDA IN/OUT I2C serial data line P7.2 28
15 SCL OUT I2C clock line P7.3 27
16 E2_SDA IN/OUT I2C serial data line for E2PROM P10.7 89
17 E2_SCL OUT I2C clock line for E2PROM P10.6 90
18 E2_WP OUT Controls the write protection of the

P10.5 91

E2PROM

EXTENTION MODULES RELATED

19 IDTV_RX IN IDTV UART receive P6.2 36
20 IDTV_TX OUT IDTV UART transmit P6.3 35
21 IDTV_IRQ OUT IDTV status change notification P6.1 37
22 TVLINK IN (*) /

TVLink interrupt input / data output P1.6 74

OUT

23 DMP_CTRL OUT Controls DMP module P6.0 38

VIDEO RELATED

24 LX_RST OUT Resets the LX66 video processor P8.1 21
25 LX_INT IN (*) Interrupt notification from LX66 P8.3 19
26 RGB_SW_1 OUT RGB switch control 1 P9.2 5
27 RGB_SW_2 OUT RGB switch control 2 P9.3 4

APPLICATION

28 IR IN (*) Remote control interrupt input P8.2 20
29 LED_1 OUT LED control 1 P9.0 7
30 LED_2 OUT LED control 2 P9.1 6
31 MUTE_AMP OUT Mutes the audio amplifier P9.7 100
32 SC1_PIN8 ADC IN Scart 1 pin8 input measurement P10.1 95
33 SC2_PIN8 ADC IN Scart 2 pin8 input measurement P10.2 94

34 SC3_PIN8 ADC IN Scart 3 pin8 input measurement P10.3 93
35 KEYB ADC IN Keyboard input P10.0 97
36 SWU_RX IN UART receive for software upgrade P7.1 29
37 SWU_TX OUT UART transmit for software upgrade P7.0 30
38 RY_BY IN Ready/Busy indication from external

P5.1 45

flash
39 LG_1/IRQPDP IN Interrupt Request from Plasma Display P7.4 26
41 CHROMA_SW OUT Chroma Switch for SVHS P7.5 25
42 DRX_RST OUT DRX reset P9.6 1
43 VGA_STBY IN PC VGA standby detection P9.5 2
44 SERV_DTC IN Service socket detection P7.7 23
45 AC_INFO IN Alternate Current Information P8.5 18

Table 1: Microcontroller I/O Assignments

The PC Audio L/R, DMP Audio L/R, IDTV/SC3 Audio L/R, YPbPr Audio L/R, Scart2
Audio L/R signals are switched via audio switch TEA6420. The outputs of the switch are two
L/R audio signals.

MSP4411K is used for audio processing and it covers the sound processing of all analog
TV-standards worldwide, as well as the NICAM digital sound standard. Audio outputs are
connected to SC1/2/3 connector, audio line out, headphone, Speaker, subwoofer and S/PDIF
connectors. The inputs to the MSP441K are two audio signals from audio switch,
FAV_Audio_L/R, SC1_Audio_L/R, QSS signals from main and pip tuners, Tuner2 mono signal
and HDMI I2S signal.

The AD8190 is a DVI/HDMI switch featuring equalized TMDS inputs and pre­emphasized TMDS outputs, ideal for systems with long cable runs between sources and sinks of
video data. A disable feature sets the outputs to a high impedance state, reducing the power
dissipation.

The primary function of the AD8190 is to switch one of two HDMI single-link sources to
one output. Each HDMI source consists of four differential high-speed channels and four general
purpose control lines. The switched HDMI signal is sent to the video processor IC.

2. CONTROLLER

2.1. Microcontroller: Renesas M16C M30620SPGP

General Description:

The M16C/62P Group (M16C/62P, M16C/62PT) of single-chip microcomputers are built
using the high performance silicon gate CMOS process using a M16C/60 Series CPU core and
are packaged in a 80-pin, 100-pin and 128-pin plastic molded QFP. These single-chip
microcomputers operate using sophisticated instructions featuring a high level of instruction
efficiency. With 1M bytes of address space, they are capable of executing instructions at high
speed. In addition, this microcomputer contains a multiplier and DMAC which combined with
fast instruction processing capability, makes it suitable for control of various OA, communication,
and industrial equipment which requires highspeed arithmetic/logic operations.

General Features:

Main features of M16C are:

• 16-bit Multifunction Timer (Timer A and B): 11 channels

• UART/Clock Synchronous Serial Interface: 3 channels

• Clock Synchronous Serial Interface: 2 channels

• 10-bit A/D Converter: 26 channels

• 8-bit D/A Converter: 2 channels

• DMAC: 2 channels

• CRC Calculation Circuit

• Watchdog Timer

• Clock Generation Circuits: Main Clock Generation Circuit, Sub Clock Generation

Circuit, On-chip Oscillator, PLL Synthesizer

• Oscillation Stop Detection Function

• Voltage Detection Circuit (Option) (Except for T Version and V Version)

• Interrupts: 29 internal factors, 8 external factors, 4 software factors

• Data Flash: 4KB (Flash Memory Version only)

Block Diagram:

Figure 1: M16C Block Diagram

Pin Configuration:

Figure 2: M16C Pin Configuration

Table 2: M16C Pin Descriptions

2.2. Flash IC SST39VF088

General Description:

The SST39VF088 device is a 1M x8 CMOS Multi-Purpose Flash (MPF) manufactured with
SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design
and thick-oxide tunneling injector attain better reliability and manufacturability compared with
alternate approaches. The SST39VF088 writes (Program or Erase) with a 2.7-3.6V power supply.
It conforms to JEDEC standard
pinouts for x8 memories. Featuring high performance Byte-Program, the SST39VF088 device
provides a typical Byte-Program time of 14 µsec. The devices use Toggle Bit or Data# Polling to
indicate the completion of Program operation. To protect against inadvertent write, they have on­chip hardware and
Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of
applications, these devices are offered with a guaranteed endurance of 10,000 cycles. Data
retention is rated at greater than 100 years.The SST39VF088 device is suited for applications that
require convenient and economical updating of program, configuration, or data memory. For all
system applications, they significantly improve performance and reliability, while lowering
power consumption. They inherently use less energy during Erase and Program than alternative
flash technologies. The total energy consumed is a function of the applied voltage, current, and
time of application. Since for any given voltage range, the SuperFlash technology uses less
current to program and has a shorter erase time, the total energy consumed during any Erase or
Program operation is less than alternative flash technologies. They also improve flexibility while
lowering the cost for program, data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and Program times, independent of the number
of Erase/Program cycles that have occurred. Therefore the system software or hardware does not
have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Program cycles. To meet high density,
surface mount requirements, the SST39VF088 is offered in 48-lead TSOP packaging. See below
figure for pin assignments.

General Features:

• Organized as 1M x8

• Single Voltage Read and Write Operations
– 2.7-3.6V

• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention

• Low Power Consumption (typical values at 5 MHz)
– Active Current: 12 mA (typical)
– Standby Current: 4 µA (typical)

• Sector-Erase Capability
– Uniform 4 KByte sectors

• Block-Erase Capability

– Uniform 64 KByte blocks

• Fast Read Access Time:
– 70 and 90 ns

• Latched Address and Data

• Fast Erase and Byte-Program

– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time: 15 seconds (typical)

• Automatic Write Timing

– Internal VPP Generation

• End-of-Write Detection

– Toggle Bit
– Data# Polling

• CMOS I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• Packages Available

– 48-lead TSOP (12mm x 20mm)

Pin Configuration:

Figure 3: Flash IC Pin Configuration

Table 3:Flash IC Pin Descriptions

2.3. 32K I2C Serial EEPROM: 24LC32A

General Description:

The Microchip Technology Inc. 24AA32A/24LC32A (24XX32A*) is a 32 Kbit Electrically
Erasable PROM.The device is organized as four blocks of 8K x 8-bit memory with a 2-wire serial
interface. Low-voltage design permits operation down to 1.8V, with standby and active currents
of only 1 A and 1 mA, respectively. It has been developed for advanced, lowpower applications
such as personal communications or data acquisition. The 24XX32A also has a page write
capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the
same bus, for up to 256 Kbits address space. The 24XX32A is available in the standard 8-pin
PDIP, surface mount SOIC,
TSSOP and MSOP packages.

General Features:

• Single supply with operation down to 1.8V

• Low-power CMOS technology

- 1 mA active current typical

- 1A standby current (max.) (I-temp)

• Organized as 4 blocks of 8K bits (32K bit)

• 2-wire serial interface bus, I2C™ compatible

• Cascadable for up to eight devices

• Schmitt Trigger inputs for noise suppression

• Output slope control to eliminate ground bounce

• 100 kHz (<2.5V) and 400 kHz (2.5V)
compatibility

• Self-timed write cycle (including auto-erase)

• Page write buffer for up to 32 bytes

• 2 ms typical write cycle time for page write

• Hardware write-protect for entire memory

• Can be operated as a serial ROM

• Factory programming (QTP) available

• ESD protection > 4,000V

• 1,000,000 erase/write cycles

• Data retention > 200 years

• 8-lead PDIP, SOIC, TSSOP and MSOP packages

• Standard and Pb-free finishes available

• Available temperature ranges:

- Industrial (I): -40°C to +85°C

- Automotive (E): -40°C to +125°C

Block Diagram:

Figure 4: Serial EEPROM Block Diagram

Pin Configuration:

Figure 5: Serial EEPROM Pin Configuration

3. TUNING AND IF DECODING

3.1. Tuner

The tuners used in the design are combined VHF, UHF tuners suitable for CCIR systems
B/G, H, L, L’, I/I’, and D/K. The tuning is available through the digitally controlled I2C bus
(PLL). Below you will find info on one of the tuners in use.

Description:

The UV1316MK4 tuner belongs to the UV1300 family of third generation WSP tuners,
which are designed to meet a wide range of TV applications. It is a full band tuner suitable for
CCIR systems B/G, H, L, L’, I and I’. The low IF output impedance is designed for direct drive
of a wide variety of SAW filters with sufficient suppression of triple.

Features:

Member of UV1300 MK4 family of small-sized UHF/VHF tuners

• Systems CCIR: B/G, H, L, L’, I and I’; OIRT: D/K

• Digitally-controlled (PLL) tuning via I2C-bus

• Fast 400kHz I2C bus protocol compatible with 3.3V and 5V micro controllers

• Off-air, S-cable and hyperband channels from 48.25 MHz to 863.25MHz inclusive

• World standardized mechanical dimensions and pinning. Horizontal mounting is

optionally available

• Various connector types available

• EURO content available.

Pin Configuration:

Pin Symbol Description
1 AGC Automatic Gain Control Voltage
2 TU Tuning Voltage Monitor(Output)
3 AS I2C Bus Address Select
4 SCL I2C Bus Serial Clock
5 SDA I2C Bus Serial Data
6 N.C. Not Connected
7 Vs Supply Voltage +5V
8 ADC ADC Input
9 Vst Fixed Tuning Supply Voltage +32V
10 I.F out 2 /

d.n.c

11 I.F out 1

Symmetrical I.F output 2 / Do not connect
for asymmetrical

Asymmetrical I.F Output / Symmetrical I.F
output 1

M1,M2,M3,M4 GND

Table 4: UV1316 MK4 Pin Descriptions

Mounting Tags (Ground)

Block Diagram:

Figure 6: UV1316 MK4 Block Diagram

3.2. IF Demodulator: Micronas DRX3961A

DRX 3961A is used to extract CVBS and audio information from the IF output of the tuner.

Features:

• Multistandard QSS IF processing with a single SAW filter

• Programmable IF frequency between 30 and 60 MHz

• DSP-based IF processing for the following standards: B/G, D/K, I, L/L’, and M/N

• Standard specific digital signal processing for channel filtering, audio/video splitting,

group delay equalization (programmable), video AGC and delayed tuner AGC

• Digital picture carrier recovery

• Automatically frequency-adjusted Nyquist slope over complete lock-in frequency range,

which eliminates the need of fine tuning

• Fast AGC algorithms for tuner, video, and SIF outputs

• Programmable tuner take-over point (TOP)

• No sound traps required for video output

• FM radio capability without external components and with standard TV tuner

• I2C bus interface

Pin Configuration:

Figure 7: DRX 3961A Pin Configurations

Block Diagram:

Figure 8: DRX 3961A Block Diagram

3.3. IF Demodulator:TDA9886T

Description:

The TDA9886T is an alignment-free multistandard (PAL and NTSC) vision and sound IF
signal PLL demodulator for negative modulation only and FM processing.
The TDA9886 is an alignment-free multistandard (PAL, SECAM and NTSC) vision and sound
IF signal PLL demodulator for positive and negative modulation, including sound AM and FM
processing.

Features:

· 5 V supply voltage

· Gain controlled wide-band Vision Intermediate Frequency (VIF) amplifier, AC-coupled

· Multistandard true synchronous demodulation with active carrier regeneration: very linear
demodulation, good intermodulation figures, reduced harmonics, and excellent pulse response

· Gated phase detector for L and L-accent standard

· Fully integrated VIF Voltage Controlled Oscillator (VCO), alignment-free, frequencies
switchable for all negative and positive modulated standards via I2C-bus

· Digital acquisition help, VIF frequencies of 33.4, 33.9,38.0, 38.9, 45.75, and 58.75 MHz

· 4 MHz reference frequency input: signal from Phase-Locked Loop (PLL) tuning system or
operating as crystal oscillator

· VIF Automatic Gain Control (AGC) detector for gain control, operating as peak sync detector
for negative modulated signals and as a peak white detector for positive modulated signals

· External AGC setting via pin OP1

· Precise fully digital Automatic Frequency Control (AFC) detector with 4-bit digital-to-analog
converter, AFC bits readable via I2C-bus

· TakeOver Point (TOP) adjustable via I2C-bus or alternatively with potentiometer

· Fully integrated sound carrier trap for 4.5, 5.5, 6.0, and 6.5 MHz, controlled by FM-PLL
oscillator

· Sound IF (SIF) input for single reference Quasi Split Sound(QSS) mode, PLL controlled

· SIF-AGC for gain controlled SIF amplifier, single reference QSS mixer able to operate in high

performance single reference QSS mode and in intercarrier mode, switchable via I2C-bus

· AM demodulator without extra reference circuit

· Alignment-free selective FM-PLL demodulator with high linearity and low noise

· Four selectable I2C-bus addresses

· I2C-bus control for all functions

· I2C-bus transceiver with pin programmable Module Address(MAD)

Pin Configuration:

Symbol Pin Description

VIF1 1 VIF differential input 1
VIF2 2 VIF differential input 2
n.c. - not connected
OP1 3 output port 1; open-collector
FMPLL 4 FM-PLL for loop filter
DEEM 5 de-emphasis output for capacitor
AFD 6 AF decoupling input for capacitor
DGND 7 digital ground
n.c. - not connected
AUD 8 audio output

TOP 9

SDA 10
SCL 11 I2C-bus clock input

SIOMAD 12

n.c. - not connected
n.c. 13 not connected
n.c. - not connected
TAGC 14 tuner AGC output

REF 15
VAGC 16 VIF-AGC for capacitor

n.c. - not connected
CVBS 17 composite video output
n.c. - not connected
AGND 18 analog ground
VPLL 19 VIF-PLL for loop filter

tuner AGC TakeOver Point (TOP)
for resistor adjustment

I2C-bus data input and output

sound intercarrier output and MAD
select with resistor

4 MHz crystal or reference signal
input

VP 20 supply voltage
AFC 21 AFC output
OP2 22 output port 2; open-collector
n.c. - not connected

SIF1 23

SIF2 24

n.c. - not connected
n.c. - not connected

Table 5: TDA9886T Pin Descriptions

SIF differential input 1 and MAD
select with resistor

SIF differential input 2 and MAD
select with resistor

Figure 9: TDA9886T Pin Configurations

3.4. SAW (Surface Acoustic Wave) Filter: Epcos X6966M

X6966M is a bandpass IF filter at f

= 36.125 MHz with tinned CuFe alloy terminals.

c