Vestel 17MB25 Schematic

1. INTRODUCTION.................................................................................................................. 3

2. TUNER................................................................................................................................... 3

1.1 General description of TDTC-G101D: .................................................................. 3

1.2 Features of TDTC-G101D: .................................................................................... 3

1.3 Pin Configuration ................................................................................................... 4

3. AUDIO AMPLIFIER STAGE WITH TPA3101 ...................................................................4

3.1 General Description of TPA3101................................................................................. 4

3.2 Features of TPA3101 .................................................................................................. 4

3.3 Pin Configuration of TPA3101 .............................................................................. 5

4. MICROCONTROLLER (MSTAR)....................................................................................... 6

4.1 Genaral Description..................................................................................................... 6

4.2 Features .................................................................................................................. 6

5. INTEGRATED DVB-T RECEIVER (CHEERTEK) ............................................................ 7

5.1 General Description...................................................................................................... 7

5.2 Features .................................................................................................................. 8

6. 4MX16 BIT SYNCHRONOUS DRAM (SDRAM) ............................................................ 10

6.1 General Description.................................................................................................... 10

6.2 Features ...................................................................................................................... 10

6.3 Pin Configuration ...................................................................................................... 11

7. 512K CMOS SERIAL FLASH – MX25L512 ..................................................................... 12

7.1 General Description.................................................................................................... 12

7.2 Features ...................................................................................................................... 12

8. 16MX16 BIT SYNCHRONOUS DRAM (SDRAM) .......................................................... 14

8.1 General Description.................................................................................................... 14

8.2 Features ...................................................................................................................... 14

9. SAW FILTER ...................................................................................................................... 14

9.1 IF Filter for Audio Applications – Epcos K9656M ................................................... 14

9.1.1 Standarts .................................................................................................................. 14

9.1.2 Features ................................................................................................................... 15

9.1.3 Pin Configuration .................................................................................................. 15

9.1.4 Frequency Response................................................................................................ 15

9.2 IF Filter for Video Applications – Epcos K3958M.................................................... 16

9.2.1 Standarts .................................................................................................................. 16

9.2.2 Features ................................................................................................................... 16

9.2.3 Pin Configuration .................................................................................................... 16

9.2.4 Frequency Response................................................................................................ 17

10. POWER STAGE ................................................................................................................ 17

11. IC SPECIFICATIONS ....................................................................................................... 18

11.1 32K Smart Serial EEPROM – 24C32 ..................................................................... 18

11.2 TL062 ...................................................................................................................... 19

11.3 PI5V330 ................................................................................................................... 20

11.4 74HCT4053............................................................................................................. 21

11.5 FMS6145................................................................................................................. 22

11.6 LM1117................................................................................................................ 23

11.7 ST24LC21 ............................................................................................................... 24

11.8 24LC02.................................................................................................................... 25

11.9 MAX810............................................................................................................... 26

11.10 TDA1308............................................................................................................... 27

11.11 MP1583 .................................................................................................................. 27

11.12 MP2112 ............................................................................................................ 29

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11.13 IRF7314............................................................................................................ 29

12. BLOCK DIAGRAMS ........................................................................................................ 30

12.1 General Block Diagram............................................................................................ 30

12.2 Integrated DVB-T Receiver Block Diagram............................................................ 32

12.3 MSTAR Block Diagram....................................................................................... 33

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1. INTRODUCTION

17MB25 mainboard is based on MSTAR concept IC. This IC is capable of handling audio
processing, video processing, scaling-display processing, 3D comb filter, OSD and text
processing, 8 bit dual LVDS transmitter.

TV supports PAL, SECAM, NTSC colour standards and multiple transmission standards as
B/G, D/K, I/I’, and L/L’ including German and NICAM stereo.

Sound system is able to supply 2x10W (10%THD) audio output power for stereo speakers.
Supported peripherals are:

The analog part of the moard can support DVD module which is connected to mainboard
through a cable.
The USB feature is supported through digital part of the mainboard.

1 RF input VHF1, VHF3, UHF @ 75Ohm(Common)
1 Side AV (SVHS, CVBS, HP, R/L_Audio) (Common)
1 SCART socket(Common)
1 YPbPr (Common)
1 PC input(Optional)
2 HDMI (Common)
1 Stereo audio input for PC(Common)
1 Line out(Common)
1 S/PDIF output(Common)
1 Side S-Video(Optional)
1 Headphone(Common)
1 Common interface(Optional)
1 Digital USB(Opional)
1 RS232(Optional)

2. TUNER

A horizontal mounted and Digital Half-Nim tuner is used in the product, which covers 3
Bands(From 48MHz to 862MHz for COFDM, from 45.25MHz to 863.25MHz for CCIR CH).
The tuning is available through the digitally controlled I2C bus (PLL). Below you will find
info on the Tuner in use.

1.1 General description of TDTC-G101D:

The Tuner covers 3 Bands(from 48MHz to 862MHz for COFDM, from 45.25MHz to

863.25MHz for CCIR CH). Band selection and Tuning are performed digitally via the I2C
bus.

1.2 Features of TDTC-G101D:

 Digital Half-NIM tuner for COFDM
 Covers 3 Bands(From 48MHz to 862MHz for COFDM,
 From 45.25MHz to 863.25MHz for CCIR CH)

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 Including IF AGC with SAW Filter
 Bandwidth Switching (7/8 MHz) possible
 DC/DC Converter built in for Tuning Voltage
 Internal(or External) RF AGC, Antenna Power Optional

1.3 Pin Configuration

3. AUDIO AMPLIFIER STAGE WITH TPA3101

3.1 General Description of TPA3101

The TPA3101D2 Rev.A evaluation module consists of a single 10-W, class-D, stereo audio
power amplifier complete with a small number of external components mounted on a circuit
board that can be used to directly drive a speaker with an external analog audio source as the
input.

The gain of the amplifier is controlled by two gain select pins. The gain selections are 20, 26,
32, 36dB.
The outputs are fully protected against shorts to GND, Vcc and output to output shorts with an
auto recovery feature and monitor output.

3.2 Features of TPA3101

 10-W/ch into an 8-Ω Load From a 13-V Supply
 9.2-W/ch into an 8-Ω Load From a 12-V Supply
 Operates from 10 V to 26 V
 87% Efficient Class-D Operation Eliminates
 Need for Heat Sinks
 Four Selectable, Fixed Gain Settings

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 Differential Inputs
 Thermal and Short-Circuit Protection With
 Auto Recovery Feature
 Clock Output for Synchronization With Multiple Class-D Devices
 Surface Mount 7 mm ´ 7 mm, 48-pin QFN Package
 Surface Mount 7 mm ´ 7 mm, 48-pin HTQFP Package

3.3 Pin Configuration of TPA3101

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4. MICROCONTROLLER (MSTAR)

4.1 Genaral Description

The MST6WB7GQ-3 is a high performance and fully integrated IC for multi-function
LCD monitor/TV with resolutions up to full HD (1920x1080). It is configured with an
integrated triple-ADC/PLL, an integrated DVI/HDCP/HDMI receiver, a multi-standard TV
video and audio decoder, two video de-interlacers, two scaling engines, the MStarACE-3
color engine, an on-screen display controller, an 8-bit MCU and a built-in output panel
interface. By use of external frame buffer, PIP/POP is provided for multimedia applications.
Furthermore, 3-D video decoding and processing are fulfilled for high-quality TV
applications. To further reduce system costs, the MST6WB7GQ-3 also integrates
intelligent power management control capability for green-mode requirements and spread­spectrum support for EMI management.

4.2 Features

LCD TV controller with PIP/POP display functions

 Input supports up to UXGA & 1080P
 Panel supports up to full HD (1920x1080)
 TV decoder with 3-D comb filter
 Multi-standard TV sound demodulator and decoder
 10-bit triple-ADC for TV and RGB/YPbPr
 10-bit video data processing
 Integrated DVI/HDCP/HDMI compliant receiver
 High-quality dual scaling engines & dual 3-D video de-interlacers
 3-D video noise reduction
 Full function PIP/PBP/POP
 MStarACE-3 picture/color processing engine
 Embedded On-Screen Display (OSD) controler engine
 Built-in MCU supports PWM & GPIO
 Built-in dual-link 8/10-bit LVDS transmitter
 5-volt tolerant inputs
 Low EMI and power saving features
 296-pin LQFP

NTSC/PAL/SECAM Video Decoder

 Supports NTSC M, NTSC-J, NTSC-4.43, PAL (B,D,G,H,M,N,I,Nc), and SECAM
 Automatic TV standard detection
 Motion adaptive 3-D comb filter for NTSC/PAL
 8 configurable CVBS & Y/C S-video inputs
 Supports Teletext level-1.5, WSS, VPS, Closed-caption, and V-chip
 Macrovision detection
 CVBS video output

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Video IF for Multi-Standard Analog TV

 Digital low IF architecture
 Stepped-gain PGA with 26 dB tuning range and 1 dB tuning resolution
 Maximum IF analog gain of 37dB in addition to digital gain
 Programmable TOP to accommodate different tuner gain to optimize noise and

linearity performance

Multi-Standard TV Sound Decoder

 Supports BTSC/NICAM/A2/EIA-J demodulation and decoding
 FM stereo & SAP demodulation
 L/Rx4, mono, and SIF audio inputs
 L/Rx3 loudspeaker and line outputs
 Supports sub-woofer output
 Built-in audio output DAC’s
 Audio processing for loudspeaker channel, including volume, balance, mute, tone, EQ,

and virtual stereo/surround

 Optional advanced surround available (Dolby1, SRS2, BBE3… etc)

Digital Audio Interface

 I2S digital audio input & output
 S/PDIF digital audio input & output
 HDMI audio channel processing capability
 Programmable delay for audio/video synchronization

Analog RGB Compliant Input Ports

 Three analog ports support up to UXGA
 Supports HDTV RGB/YPbPr/YCbCr
 Supports Composite Sync and SOG (Sync-on-Green) separator
 Automatic color calibration

DVI/HDCP/HDMI Compliant Input Port

 Two HDMI input ports with built-in switch
 Supports TMDS clock up to 225MHz @ 1080P 60Hz with 12-bit deep-color

resolution

 Single link on-chip DVI 1.0 compliant receiver
 High-bandwidth Digital Content Protection(HDCP) 1.1 compliant receiver

5. INTEGRATED DVB-T RECEIVER (CHEERTEK)

5.1 General Description

CT216T is a highly integrated single chip for DVB-T compliant STB solution. Compared
with Cheertek's previous generations of STB receiver devices. CT216T further interates
COFDM demodulator USB 2.0 HS host controller, memory card reader, 1/2-bit SPIFlash
interface, audio DAC, PWM in/out and SAR-ADC functions. In additiont special
enhangements are provided such as MPEG-4 video decoding, 16-bit OSD with anti-flickering,

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HW JPEG decoding, flesh tone and black-white extensions, and improvement of small video
quality.

CT216T includes COFDM demodulator transport stream de-multiplexer, DVB-CSA
compliant de-scrambler, RISC MPUs, MPEG-1/2/4 AV decoder, digital T\/ encoder, audio
DACs, USB 2.0 HS host controller, memory card reader, smart card reader, CI controller and
other peripherals.

Cli216T is designed in focus on the market of single tuner input product which makes, it a
cost effective solution. Supports include free to air, conditional access for SC (Smart card)
and CI portable devices, PVR, LCD TV, and other DVB-T applications.

5.2 Features

COFDM Demodulator

 ETSI EN 300 744 DVB-T NorDig Unified 1.0.3, and D-book compliant
 Automatic spectral inversion, detection
 Integrated ADC
 Direct IF (36.167 MHz or 43.75 MHz) or low IF (4.57 MHz) supported
 Single IF AGC or dual RF/lF AGC controls with ΔΣ modulabon
 Impulsive noise cancellation
 Carrier acquisition range: ±400 kHz (extensible to ±600 kHz in 8MHz BW)
 Adjacent channel interference (ACI) filter,for supporting 6, 7, and 8MHz channels

with one 8MHz analog filter

 Co-channel interterence (CCl) supression
 RF signal strength monitor

MPU

 Three 32-bit RISC MPU run up to 166MHz with total 448DMIPS
 8KB I-Cache and 8KB D-Cache
 Two general purpose timers
 Watchdog timer
 DSU for source level debug

Memory

 6-bit SDRAM controller supports up to 32MB (16MB for l28-pin)
 Unified memory architecture
 Parallel flash (216-pin only)
 1/2-bit SPI flash

Transport De-multiplexing

 TS, PES, and ES demultiplexing
 OneTS path
 CI CAM interface (216-pin only)
 32 general purpose PID filters
 32 Section filters
 CRC-32 accelerator
 DVB-CSA de-scramblers

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Video Decoding and Processing

 MPEG-2 MP@ML
 MPEG-4 SP&ASP
 PAL/NTSC format conversion
 3:2 pull down
 Zoom in/out from 1/16X to 16X
 HW JPEG decode
 4/8/16-bit OSD with anti-flickering
 On chip NTSC/PAL TV encoder
 CVBS, S-VHS, and component video
 VBI insertion for Teletext, CC and WSS
 ITU-R BT.601 and ITU-R BT.656 outputs
 Flesh tone extension
 Black/white extension,

Audio Decoding and Processing

 MPEG-1: layer 1/2/3
 MPEG-2: layer 1/2
 Decode MPEG-2 and MPEG-1 audio at sampling frequency of 16K, 22.05K, 24K,

32K, 44.1K, and 48KHz

 Decode CU-DA at sampling frequency of 44.1 KHz
 SPDIF out for AC-3 by-pass
 Embedded 2 channels audio DAC for L/R outputs
 Digital mute control and volume adjustment

OSD(On Screen Display)

 There are total 9 display planes: border; background. video. RS1 (Rectangle Strip 1),

RS2, OSD, RS3, RS4, and cursor.

 4/8l16-bit OSD with anti-flickering and anti-flutter
 Support alpha-blending per color
 Adjustable brightness control in window
 Bitmap OSD
 Support horizontal pixel duplication to enlarge bitmap automatically
 Support sub-region redraw to facilitate bitmap display.

Digitnal TV Encoder

 NTSC-M, PAL-B, D, G, H, I, Nc, M encoding
 Four video DACs to provide 6 configuration output: modes
 Support CVBS, S-VHS. and component video outs
 VBI insertion for Teletext, CC and WSS
 Color burst amplitude control
 Programmable sync. level
 On chip, color-bar generator

High Speed I/O

 USB 2.0 HS host controller

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 Memory card reader with SD, MMC, and MS interfaces
 Compliant with SD spec. 1.1 and MMC spec. 4.0 with 1-bit & 4-bit modes.
 Compliant with Memory Stick Pro format spec. 1.02 and Memory stick format spec

1.43 with 1-bit and 4-bit modes.

Peripherals

 Up to 3 full duplex UART with 16-byte FIFO
 2-wire serial (2WS) in master mode .. .
 Up to 2 IS0-7816 compliant SC (1 in 128-pin, can also be used as UART)
 5 digits 7-Segrnent LED control
 5x3 two-dimension key scan
 2 SAR-ADC input
 4 PWM input/output
 1 HW IR command decode
 GPIO

Electrical and Physical Characteristics

 Capable of using single 27MHz clock input crystal
 1.8V and 3.3V dual power supply
 Power standby mode
 PQFP-128 (CT216T-Z) or LQFP-216 (CT216T-R) package

6. 4MX16 BIT SYNCHRONOUS DRAM (SDRAM)

6.1 General Description

The EM638165 SDRAM is a high-speed CMOS synchronous DRAM containing 64 Mbits. It
is internally configured as 4 Banks of 1M word x 16 DRAM with a synchronous interface (all
signals are registered on the positive edge of the clock signal, CLK). Read and write accesses
to the SDRAM are burst oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. Accesses begin with the
registration of a BankActivate command which is then followed by a Read or Write
command. The EM638165 provides for programmable Read or Write burst lengths of 1, 2, 4,
8, or full page, with a burst termination option. An auto precharge function may be enabled to
provide a self-timed row precharge that is initiated at the end of the burst sequence. The
refresh functions, either Auto or Self Refresh are easy to use. By having a programmable
mode register, the system can choose the most suitable modes to maximize its performance.
These devices are well suited for applications requiring high memory bandwidth and
particularly well suited to high performance PC applications.

6.2 Features

 Fast access time from clock: 4.5/5/5.4 ns
 Fast clock rate: 200/166/143 MHz
 Fully synchronous operation
 Internal pipelined architecture
 1M word x 16-bit x 4-bank
 Programmable Mode registers

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 CAS Latency: 2, or 3
 Burst Length: 1, 2, 4, 8, or full page
 Burst Type: interleaved or linear burst
 Burst stop function
 Auto Refresh and Self Refresh
 4096 refresh cycles/64ms
 CKE power down mode
 Single +3.3V ± 0.3V power supply
 Interface: LVTTL
 54-pin 400 mil plastic TSOP II package
 Pb free and Halogen free
 60-ball 6.4mm x 10.1mm VFBGA package
 Pb free

6.3 Pin Configuration

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7. 512K CMOS SERIAL FLASH – MX25L512

7.1 General Description

The MX25L512 is a CMOS 524,288 bit serial Flash memory, which is configured as 65,536 x
8 internally. The MX25L512 feature a serial peripheral interface and software protocol
allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a
serial data input (SI), and a serial data output (SO). SPI access to the device is enabled by CS#
input. The MX25L512 provide sequential read operation on whole chip. After program/erase
command is issued, auto program/ erase algorithms which program/ erase and verify the
specified page or sector/block locations will be executed. Program command is executed on
page (256 bytes) basis, and erase command is executes on chip or sector (4K-bytes). To
provide user with ease of interface, a status register is included to indicate the status of the
chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP
bit. When the device is not in operation and CS# is high, it is put in standby mode and draws
less than 10uA DC current. The MX25L512 utilize MXIC's proprietary memory cell, which
reliably stores memory contents even after 100,000 program and erase cycles.

7.2 Features

General

 Serial Peripheral Interface (SPI) compatible -- Mode 0 and Mode 3
 524,288 x 1 bit structure
 16 Equal Sectors with 4K byte each
 Any Sector can be erased individually
 Single Power Supply Operation
 2.7 to 3.6 volt for read, erase, and program operations
 Latch-up protected to 100mA from -1V to Vcc +1V
 Low Vcc write inhibit is from 1.5V to 2.5V

Performance

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 High Performance
 Fast access time: 85MHz serial clock (15pF + 1TTL Load) and 66MHz serial clock

(30pF + 1TTL Load)

 Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)
 Fast erase time: 60ms(typ.) and 120ms(max.)/sector (4K-byte per sector) ; 1s(typ.) and

2s(max.)/chip(512Kb)

 Low Power Consumption
 Low active read current: 12mA(max.) at 85MHz, 8mA(max.) at 66MHz and

4mA(max.) at 33MHz

 Low active programming current: 15mA (max.)
 Low active erase current: 15mA (max.)
 Low standby current: 10uA (max.)
 Deep power-down mode 1uA (typical)
 Minimum 100,000 erase/program cycles

Software Features

 Input Data Format
 1-byte Command code
 Block Lock protection
 The BP0~BP1 status bit defines the size of the area to be software protected against

Program and Erase instructions.

 Auto Erase and Auto Program Algorithm
 Automatically erases and verifies data at selected sector
 Automatically programs and verifies data at selected page by an internal algorithm

that automatically times the program pulse widths (Any page to be programed should
have page in the erased state first)

 Status Register Feature
 Electronic Identification
 JEDEC 2-byte Device ID
 RES command, 1-byte Device ID

Hardware Features

 SCLK Input
 Serial clock input
 SI Input
 Serial Data Input
 SO Output
 Serial Data Output
 WP# pin
 Hardware write protection
 HOLD# pin pause the chip without diselecting the chip
 PACKAGE
 8-pin SOP (150mil)
 All Pb-free devices are RoHS Compliant

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8. 16MX16 BIT SYNCHRONOUS DRAM (SDRAM)

8.1 General Description

The EM63A165 SDRAM is a high-speed CMOS synchronous DRAM containing 256 Mbits.
It is internally configured as 4 Banks of 2M word x 16 DRAM with a synchronous interface
(all signals are registered on the positive edge of the clock signal, CLK). Read and write
accesses to the SDRAM are burst oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed sequence. Accesses begin with the
registration of a BankActivate command which is then followed by a Read or Write
command. The EM63A165 provides for programmable Read or Write burst lengths of 1, 2, 4,
8, or full page, with a burst termination option. An auto precharge function may be enabled to
provide a self-timed row precharge that is initiated at the end of the burst sequence. The
refresh functions, either Auto or Self Refresh are easy to use. By having a programmable
mode register, the system can choose the most suitable modes to maximize its performance.
These devices are well suited for applications requiring high memory bandwidth and
particularly well suited to high performance PC applications.

8.2 Features

Fast access time from clock: 5/5.4 ns

• Fast clock rate: 166/143 MHz

• Fully synchronous operation

• Internal pipelined architecture

• 4M word x 16-bit x 4-bank

• Programmable Mode registers

- CAS Latency: 2, or 3

- Burst Length: 1, 2, 4, 8, or full page

- Burst Type: interleaved or linear burst

- Burst stop function

• Auto Refresh and Self Refresh

• 8192 refresh cycles/64ms

• CKE power down mode

• Single +3.3V power supply

• Interface: LVTTL

• 54-pin 400 mil plastic TSOP II package

- Pb free and Halogen free

9. SAW FILTER

9.1 IF Filter for Audio Applications – Epcos K9656M

9.1.1 Standarts

 B/G
 D/K
 I
 L/L’

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9.1.2 Features

 TV IF audio filter with two channels
 Channel 1 (L’) with one pass band for sound carriers at 40,40 MHz (L’) and 39,75

MHz (L’- NICAM)

 Channel 2 (B/G,D/K,L,I) with one pass band for sound carriers between 32,35 MHz

and 33,40 MHz

9.1.3 Pin Configuration

1 Input
2 Switching input
3 Chip carrier - ground
4 Output

5 Output

9.1.4 Frequency Response

Frequency Response of Channel 1:

Frequency Response of Channel 2:

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9.2 IF Filter for Video Applications – Epcos K3958M

9.2.1 Standarts

 B/G
 D/K
 I
 L/L’

9.2.2 Features

 TV IF filter with Nyquist slopes at 33.90 MHz and 38.90 MHz
 Constant group delay

9.2.3 Pin Configuration

1 Input
2 Input - ground
3 Chip - carrier ground
4 Output

5 Output

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9.2.4 Frequency Response

10. POWER STAGE

The DC voltages required at various parts of the chassis and inverters are provided by an
external power supply unit or produced on the chassis if an adapter is used for the supply. The
12V dc voltage is switched by IRF 7314 power mosfet in TV sets with mechanical switch to
produce the required standby voltage. Also regulators and mosfets generate 1.8V, 3.3V and
5V and 1.26V voltages for other different parts of the chassis.

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11. IC SPECIFICATIONS

11.1 32K Smart Serial EEPROM – 24C32

General Description

The Microchip Technology Inc. 24C32 is a 4K x 8 (32K bit) Serial Electrically Erasable
PROM. This device has been developed for advanced, low power applications such as
personal communications or data acquisition. The 24C32 features an input cache for fast write
loads with a capacity of eight 8-byte pages, or 64 bytes. It also features a fixed 4K-bit block
of ultra-high endurance memory for data that changes frequently. The 24C32 is capable of
both random and sequential reads up to the 32K boundary. Functional address lines allow up
to eight 24C32 devices on the same bus, for up to 256K bits address space. Advanced CMOS
technology makes this device ideal for low-power non-volatile code and data applications.
The 24C32 is available in the standard 8-pin plastic DIP and 8-pin surface mount SOIC
package.

Features

 Voltage operating range: 4.5V to 5.5V
 Peak write current 3 mA at 5.5V
 Maximum read current 150 µA at 5.5V
 Standby current 1 µA typical
 Industry standard two-wire bus protocol, I2C compatible
 Including 100 kHz and 400 kHz modes
 Self-timed write cycle (including auto-erase)
 Power on/off data protection circuitry
 Endurance: 10,000,000 Erase/Write cycles guaranteed for High Endurance

Block, 1,000,000 E/W cycles guaranteed for Standard Endurance Block

 8 byte page, or byte modes available
 1 page x 8 line input cache (64 bytes) for fast write loads
 Schmitt trigger, filtered inputs for noise suppression
 Output slope control to eliminate ground bounce
 2 ms typical write cycle time, byte or page
 Up to 8 chips may be connected to the same bus for up to 256K bits total

memory

 Electrostatic discharge protection > 4000V
 Data retention > 200 years
 8-pin PDIP/SOIC packages
 Temperature ranges: Commercial (C): 0°C to +70°C, Industrial (I): -40°C to

+85°C

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Pin Configuration

11.2 TL062

General Description

Low-power JFET-input operational amplifier

Features

 Very Low Power Consumption
 Typical Supply Current . . . 200 µA (Per Amplifier)
 Wide Common-Mode and Differential Voltage Ranges
 Low Input Bias and Offset Currents
 Common-Mode Input Voltage Range Includes VCC+
 Output Short-Circuit Protection
 High Input Impedance . . . JFET-Input Stage
 Internal Frequency Compensation
 Latch-Up-Free Operation
 High Slew Rate . . . 3.5 V/µs Typ

19

Pin Configuration

11.3 PI5V330

General Description

Pericom Semiconductor.s PI5V series of mixed signal video circuits are produced in the
Company.s advanced CMOS low-power technology, achieving industry leading performance.
The PI5V330 is a true bidirectional Quad 2-channel multiplexer/demultiplexer that is
recommended for both RGB and composite video switching applications. The VideoSwitch.
can be driven from a current output RAMDAC or voltage output composite video source.
Low ON-resistance and wide bandwidth make it ideal for video and other applications. Also
this device has exceptionally high current capability which is far greater than most analog
switches offered today. A single 5V supply is all that is required for operation. The PI5V330
offers a high-performance, low-cost solution to switch between video sources. The application
section describes the PI5V330 replacing the HC4053 multiplier and buffer/amplifier.

Features

 High-performance, low-cost solution to switch between video sources
 Wide bandwidth: 200 MHz
 Low ON-resistance: 3Ω
 Low crosstalk at 10 MHz: .58 dB
 Ultra-low quiescent power (0.1 µA typical)
 Single supply operation: +5.0V
 Fast switching: 10 ns
 High-current output: 100 mA
 Packages available:
 16-pin 300-mil wide plastic SOIC (S)
 16-pin 150-mil wide plastic SOIC (W)
 16-pin 150-mil wide plastic QSOP (Q)

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Pin Configuration

11.4 74HCT4053

General Description

The 74HC4053; 74HCT4053 is a high-speed Si-gate CMOS device and is pin compatible
with the HEF4053B. It is specified in compliance with JEDEC standard no. 7A. The
74HC4053; 74HCT4053 is triple 2-channel analog multiplexer/demultiplexer with a common
enable input (E). Each multiplexer/demultiplexer has two independent inputs/outputs (nY0
and nY1), a common input/output (nZ) and three digital select inputs (Sn). With E LOW, one
of the two switches is selected (low-impedance ON-state) by S1 to S3. With E HIGH, all
switches are in the high-impedance OFF-state, independent of S1 to S3. VCC and GND are
the supply voltage pins for the digital control inputs (S1 to S3 and E). The VCC to GND
ranges are 2.0 V to 10.0 V for 74HC4053 and 4.5 V to 5.5 V for 74HCT4053. The analog
inputs/outputs (nY0 and nY1, and nZ) can swing between VCC as a positive limit and VEE as
a negative limit. VCC - VEE may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically
ground).

Features

 Low ON resistance:
 80 W (typical) at VCC - VEE = 4.5 V
 70 W (typical) at VCC - VEE = 6.0 V
 60 W (typical) at VCC - VEE = 9.0 V
 Logic level translation:
 To enable 5 V logic to communicate with ±5 V analog signals
 Typical ‘break before make’ built in
 Complies with JEDEC standard no. 7A
 ESD protection: HBM EIA/JESD22-A114-C exceeds 2000 V, MM EIA/JESD22-

A115-A exceeds 200 V

 Multiple package options
 Specified from -40 °C to +85 °C and from -40 °C to +125 °C

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Pin Configuration

11.5 FMS6145

General Description

The FMS6145 Low-Cost Video Filter (LCVF) is intended to replace passive LC fi lters and
drivers with a low-cost integrated device. Five 4th-order fi lters provide improved image
quality compared to typical 2nd or 3rd-order passive solutions. The FMS6145 may be directly
driven by a DC-coupled DAC output or an AC-coupled signal. Internal diode clamps and bias
circuitry may be used if AC-coupled inputs are required. The outputs can drive AC- or DC-

coupled single (150Ω) or dual (75Ω) loads. DC coupling the outputs removes the need for

output coupling capacitors. The input DC levels are offset approximately +280mV at the
output.

Features

 Five 4th-order 8MHz (SD) fi lters
 Drives single,AC- or DC-coupled, video loads (2Vpp, 150Ω)
 Drives dual, AC- or DC-coupled, video loads (2Vpp, 75Ω)
 Transparent input clamping
 AC- or DC-coupled inputs
 AC- or DC-coupled outputs
 DC-coupled outputs eliminate AC-coupling capacitors
 5V only
 Robust 8kV ESD protection
 Lead-free TSSOP-14 package

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Pin Configuration

11.6 LM1117

General Description

The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at 800mA of
load current. It has the same pin-out as National Semiconductor’s industry standard LM317.
The LM1117 is available in an adjustable version, which can set the output voltage from

1.25V to 13.8V with only two external resistors. In addition, it is also available in five fixed
voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V. The LM1117 offers current limiting and thermal
shutdown. Its circuit includes a zener trimmed bandgap reference to as-sure output voltage
accuracy to within ±1%. The LM1117 series is available in SOT- 223, TO-220, and TO-252
D-PAK packages. A minimum of 10μF tantalum capacitor is required at the output to improve
the transient response and stability.

Features

 Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions
 Space Saving SOT-223 Package
 Current Limiting and Thermal Protection
 Output Current 800mA
 Line Regulation 0.2% (Max)
 Load Regulation 0.4% (Max)
 Temperature Range
 LM1117 0°C to 125°C
 LM1117I -40°C to 125°C

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