2.2. Back End............................................................................................................................................5
2.3. Side Board(s).....................................................................................................................................8
IC AND COMPONENT DESCRIPTIONS............................................................................................11
3.1. Basic IC List.....................................................................................................................................11
5.2.2. Creating Mass Production EEPROM........................................................................................42
5.3. TV Menu...........................................................................................................................................42
The document covers 20” (17MB18) chassis building blocks, basic features, service menu settings, and the other
information needed by service personal.
1.2. General Features
The system is a 14” to 20” TFT LCD TV solution with UOCIII Versatile Signal Processor and PW1306 Vid eo Image
Processor chip-set on 4-layer PCB. The TV will support PAL/SECAM B/G/D/K/I/L/L’.
The other general default features of the TV are as listed below:
• 1 Full Scart input (with SVHS support)
• 1 SVHS input through standard S-Video interface.
• 1 CVBS input through standard RCA jack
• 75 ohms antenna input
• D-Sub 15 PC Input
• GERMAN + NICAM STEREO
• <3W S/B Power Consumption from mains supply
• 2x3W Speaker Output Power @16 Ohm spks; HP Output, Stereo Audio line out
• Stereo Audio line in
• Equalizer
• IR Control (RC5)
• OSD;Menu Languages ENG, FRA, GER, ITA, SPA, POR, TUR, SWE, D EN, FIN, NOR, POL, HUN, CZE, BUL,
ARA, PER, RUS (subject to change and be grouped)
• Teletext
• 2H/4H Comb Filter
• White balance settings (warm/normal/cool) for TV&PC
• Full AIR&CABLE band coverage
• Auto Shut down
2. SYSTEM BUILDING BLOCKS
17MB18 chassis main blocks are as follows:
•Analog Front End : UOCIII (Microcontroller + Video Proccessor + Sound Proccessor + IF), CTI, Tuner, SAW
filters, Audio Amp., DAC
• Back End : PW1306(Microcontroller, Scaler, OSD, Keyboard/IR Interface)
17MB18 Main Board consists of two major blocks. The first block is analog front-end and this block is handled by
UOCIII chip that is highly multifunctional. This IC does demodulation of Video & Audio from Tuner IF, CVBS, Audio,
RGB, SVHS input selection and processing. It has an audio processor that supports equalizer or tone control, volume
control, AVL, surround effect etc and supplies amplifier, headphone and CVBS & audio line outputs. It handles video
processing such as colour standard detection and demodulation, picture alignment (brightness, contrast, colour etc.). The
IC also does teletext decoding with 10 pages text memory. After video processing, the processed video is applied to
PW1306 chip in RGB format.
The TV Tuner is an asymmetrical IF output type and is PLL controlled. For multistandard reception, a switch able SAW
filter is used as the sound filter and it is controlled by SAW_SW output from UOC. After the SAW filter block, IF signal
is applied to UOC IF inputs (VIFIN[1,2] and SIF[1, 2]).
As UOCIII can handle all the audio processing, there is no need for additional audio processor solution on the board.
UOC supports three Audio outputs. These outputs are assigned to Headphone, Speaker and Scart Audio line outputs. The
board employs TDA7056A and TDA1308 to drive speaker and headphone outputs respectively. As another dedicated
output for Audio Line out from jack is not possible in UOC, this line out signal is obtained by using I2S input DAC
CS4335. UOCIII I2S output is converted to anolog signal by DAC CS4335.
2.1.1.
Tuner
As the thickness of the TV set has a limit, a horizontal mounted tuner with longer connector is used in the
product. The tuning is available through the digitally controlled I
2
C bus (PLL). Below you will find info on the
Asymmetrical Tuner in use.
General description:
The tuner meets a wide range of applications. It is a combined VHF, UHF tuner suitable for CCIR systems
B/G, H, L, L’, I and I’. The low IF output impedance drives a wide variety of SAW filters with sufficient
suppression of triple transient.
Features:
•
Small sized UHF/VHF tuners
Systems CCIR: B/G, H, L, L’, I and I’; OIRT: D/K
•
Digitally controlled (PLL) tuning via I
•
Off-air channels, S-cable channels and Hyper band
•
S(AE)
Aerial source impedance (unbalanced) 75 Ohm
Z
•
2
C-bus
PIN SYMBOL DESCRIPTION
1
2
3
4
5
6
7
8
9
AGC
Automatic Gain Control Voltage 4
TU Tuning voltage monitor (output)
AS
SCL
SDA
I 2C-Bus Address Select
I 2C-Bus Serial Clock
I 2C-Bus Serial Data
n.c. Not Connected
s
V
ADC
ST
V
Supply Voltage +5V ±0.125
ADC Input
Fixed tuning Supply Voltage +33V ±0.5
±
0.1
10
11
M1,M2,M3,
M4
I.F out 2 Symmetrical I.F output 2 / Do not connect for asymmetrical
I.F out 1 Asymmetrical I.F Output / Symmetrical I.F output 1
GND Mounting Tags (Ground)
2.1.2.
K3953M is an IF Filter for Video Applications. The package is SIP5K. Supported standards are B/G, D/K, I,
L/L’.
K9656M is an IF Filter for Audio Applications. The package is SIP5K. Supported standards are B/G, D/K, I,
L/L’.
2.2. Back End
The Back End section is handled by PW1306 chip. This IC has built in ADC’s for RGB and SOY support. The RGB input
can handle standard interlaced RGB output from UOC, PC VGA RGB input. As only 1 set of ADC is present in PW1306
these sources should be multiplexed.
All the multiplexing operations are controlled by PW1306 via YUV_TV_SW (58) and VGA_TV_SW (57) signals.
The video output from PW1306 is a 48-bit digital RGB bus format and made available on two separate connectors with
TTL control signals (i.e. HS, VS, CLK, etc.). This digital output is intended to interface to TTL compatible display
devices. As PW1306 does not have integrated LVDS transmitter, 24 bit (even part of RGB) video output and TTL control
signals from PW1306 are also inputted to DS90C385 LVDS IC to produce single pixel LVDS output for LVDS
compatible LCDs.
SAW Filters
A: VGA _TV_SW
B: YUV _TV_SW
A B SYNC SOURCE
0 0 UOC
0 1 VGA
1 0 YcbCr
1 1 NOT USED
Table 2: H/V Sync Multiplexing Table
Backlight control is also possible via PW1306 Porta7 pin (PWMOUT, PL176-10), that is a variable duty-cycle pulse
generator output.
The keypads (17TK15, 16, 17, 20, 21) for 17MB18 main board are listed in the Table below. (They have the same connector
pinning though):
Connector PL1 on keypads (connected to the connector PL175 on the main board):
Keypads
17”
Key Name Type Function 21
Power Soft sw. Power shut-down and turn on X
Stand-by Tact sw. Switch between stand-by and turn on modes. TV/AV Tact sw. Input source select button. X
Menu Tact sw. Display main menu on the screen. If any menu is
active, display the upper menu. If main menu is
active, turn menu off.
Program- Tact sw. Go to the lower program at any time in TV mode.
In menu mode, go to down menu item.
Program+ Tact sw. Go to the upper program at any time in TV mode.
In menu mode, go to up menu item.
Volume- Tact sw. Decrease the volume level in the volume. In menu
mode, go to left menu item.
Volume+ Tact sw. Increase the volume level in the volume. In menu
mode, go to right menu item.
Pin No: Name Pin No: Name:
1 Volume+ 6 Program+
2 Volume- 7 Program3 Ground 8 Menu
4 Not Connected* 9 TV/AV
5 Ground 10 Stand-by/Shut-down
*Reserved: It can be +5V in the future designs if needed.
X
X
X
X
X
2.3.2.
IR&LED board contains LED indicator(s) to show TV’s status (Red for stand-by, green for normal operation) and one IR
receiver to get remote control instructions. All the IR&LED boards have the same circuit and connector pinning but the
different mechanical structure to fit different cabinets (see the related section for schematics and connector pinning).
2.4. Power
Several linear regulators and switches are used to generate several separate analog and digital voltage supplies such as +5, +3.3,
+1.8, etc. (Please check the Figure 3, and Table 3 for power management details.)
IC100 PW1306, IC102 Flash, IC176 LVDS, , X IC500, LM1117
IC100 PW1306 X IC501, LM1117
IC100 PW1306 X IC504, LM1117
IC100 PW1306 X IC503, LM1117
IC203 UOC X
IC203 UOC X
X
IC502, LM1117
VPP Panel Display Electronics X
Table 3: Power management table.
9
17” TFT TV Service Manual
_
12V
12V
INV
12VA
9V
LM1117
IRF7314
MC34167
LM1117
VCC5
VCC5A
V3_3A
VCC5A
or
V3_3D
or
12VA
V3_3D
LM1117
V1_8D
LM1117
V1_8A
LM1117
VADC3
LM1117
V1_8V1
V1_8V2
VPP
10
17” TFT TV Service Manual
3. IC AND COMPONENT DESCRIPTIONS
3.1. Basic IC List
No Title Description
IC203 UOCIII Versatile Signal Processor
IC100 PW1306 Video Image Processor with Analog Interface
IC102 MT28F800B3W Flash Memory
IC176 DS90C385 Programmable LVDS Transmitter
IC103 EL1883 Sync Separator
IC404 7 4HC4052 Dual 4-channel Analog Multiplexer
IC200 TA1366FG LTI/CTI IC
IC410, IC411 TDA7056A Class AB Mono 3W Power Amplifier
IC401 TDA1308 Class AB Stereo Headphone Driver
IC500/1/2/3/4,
LM1117 Linear Regulator
IC201
IC400 24LC21
IC101 24LC32
Serial Electrically Erasable PROM
3.2. UOCIII
The UOCIIIseries combines the functions of a Video Signal Processor (VSP) together with a FLASH embedded
TEXT/Control/Graphics m-Controller (TCG m-Controller) and US Closed Caption decoder. In addition the following functions
can be added:
• Adaptive digital (4H/2H) PAL/NTSC combfilter
• Teletext decoder with 10 page text memory
• Multi-standard stereo decoder
• BTSC stereo decoder
• Digital sound processing circuit
• Digital video processing circuit
The UOC III series consists of the following 3 basic concepts:
•Stereo versions. These versions contain the TV processor with a stereo audio selector, the TCG m-Controller, the multi-
standard stereo or BTSC decoder, the digital sound processing circuit and the digital video processing circuit. Options are
the adaptive digital PAL/NTSC comb filter and a teletext decoder with 10 page text memory.
•AV stereo versions. These versions contain the TV processor with stereo audio selector and the TCG m-Controller. Options
are the digital sound processing circuit, the digital video processing circuit, the adaptive digital PAL/NTSC comb filter and
a teletext decoder with a 10 page text memory.
•Mono sound versions. These versions contain the TV processor with a selector for mono audio signals and the TCG m-
Controller. Options are the adaptive digital PAL/NTSC combfilter and a teletext decoder with 10 page text memory.
11
17” TFT TV Service Manual
3.2.1.
Pinout
Figure 6: UOCIII Pin configuration “stereo” and “AV-stereo” versions with Audio DSP
SYMBOL
VSSP2 1 1 1 ground
VSSC4 2 2 2 ground
VDDC4 3 3 3 digital supply to SDACs (1.8V)
VDDA3(3.3V) 4 4 4 supply (3.3 V)
VREF_POS_LSL 5
VREF_NEG_LSL+HPL 6
VREF_POS_LSR+HPR 7
STEREO +AV
STEREO
AV STEREO
NO AUDIO
DSP
- -
- -
- -
MONODESCRIPTION
positive reference voltage SDAC (3.3 V)
negative reference voltage SDAC (0 V)
positive reference voltage SDAC (3.3 V)
VDDA2(3.3) 94 94 94 supply voltage SDAC (3.3 V)
VSSadc 95 95 95 ground for video ADC and PLL
VDDadc(1.8) 96 96 96 supply voltage video ADC and PLL
INT0/P0.5 97 97 97
external interrupt 0 or port 0.5 (4 mA current
sinking capability for direct drive of LEDs)
P1.0/INT1 98 98 98 port 1.0 or external interrupt 1
P1.1/T0 99 99 99 port 1.1 or Counter/Timer 0 input
VDDC2 100 100 100 digital supply to core (1.8 V)
VSSC2 101 101 101 ground
2
P0.4/I2SWS 102
P0.4
-
P0.3/I2SCLK 103
- - port 0.4 or I
102 102 port 0.4
- - port 0.3 or I
S word select
2
S clock
P0.3 - 103 103 port 0.3
2
P0.2/I2SDO2 104
- - port 0.2 or I
S digital output 2
P0.2 - 104 104 port 0.2
2
P0.1/I2SDO1 105
P0.1
-
- - port 0.1 or I
105 105 port 0.1
S digital output 1
15
17” TFT TV Service Manual
SYMBOL
P0.0/I2SDI1/O 106
P0.0
P1.3/T1 107 107 107 port 1.3 or Counter/Timer 1 input
P1.6/SCL 108 108 108
P1.7/SDA 109 109 109
VDDP(3.3V) 110 110 110
P2.0/TPWM 111 111 111 port 2.0 or Tuning PWM output
P2.1/PWM0 112 112 112 port 2.1 or PWM0 output
P2.2/PWM1 113 113 113 port 2.2 or PWM1 output
P2.3/PWM2 114 114 114 port 2.3 or PWM2 output
P3.0/ADC0 115 115 115 port 3.0 or ADC0 input
P3.1/ADC1 116 116 116 port 3.1 or ADC1 input
VDDC1 117 117 117 digital supply to core (+1.8 V)
DECV1V8 118 118 118 decoupling 1.8 V supply
P3.2/ADC2 119 119 119 port 3.2 or ADC2 input
STEREO +AV
STEREO
-
AV STEREO
NO AUDIO
DSP
- - port 0.0 or I
106 106 port 0.0
MONODESCRIPTION
2
S digital input 1 or I2S digital output
2
port 1.6 or I
port 1.7 or I
supply to periphery and on-chip voltage regulator
(3.3 V)
C-bus clock line
2
C-bus data line
P3.3/ADC3 120 120 120 port 3.3 or ADC3 input
VSSC/P 121 121 121 digital ground for m-Controller core and periphery
P2.4/PWM3 122 122 122 port 2.4 or PWM3 output
P2.5/PWM4 123 123 123 port 2.5 or PWM4 output
VDDC3 124 124 124 digital supply to core (1.8V)
VSSC3 125 125 125 ground
P1.2/INT2 126 126 126 port 1.2 or external interrupt 2
P1.4/RX 127 127 127 port 1.4 or UART bus
P1.5/TX 128 128 128 port 1.5 or UART bus
3.3. PW1306
The PW1306 Video Image Processor is a “system-on-a-chip ” that oversamples and processes RGB or YPbPr video from
analog video decoders. The PW1306 integrates video processing, including deinterlacer and video enhancement filters with a
triple ADC. Analog RGB or YPbPr in PC graphics, standard, or high-definition video can be disp layed in either 4:3 or 16:9
formats.
• Supports analog video decoders with tri pl e 8-bit Analog-to-Digital Converters (ADCs) up to 140 MSPS conversion rate