Vestel 17MB08-3 Schematic

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THIS PAGE IS INTENTIONALLY LEFT BLANK

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TABLE OF CONTENTS

INTRODUCTION......................................................................................................................................1

TUNER..........................................................................................................................

IF PART (T

MULTI STANDARD SO

AUDIO AMPLIFIER STAG

POWER....................................................................................................................................................2

MICROCONTROLLE

SERIAL ACCESS CMOS 16K (

CLASS AB STEREO HEADPHON

10.

SAW FILTERS..........................................................................................................................................3

11.

IC DESCRIPTIONS AND INTE

11.1.

11.2.

11.3.

11.4.

11.5.

11.6.

11.7.

11.8.

11.9.

11.10.

11.11.

11.12.

11.13.

11.14.

11.15.

11.16.

11.17.

11.18.

11.19.

12.

12.1.

12.2.

13.

14.

LM1117.........................................................................................................................

LM2576.........................................................................................................................

LM317T .............................................................................................................................................6

ST24LC21 .........................................................................................................................................7

TEA5114A.........................................................................................................................................8

TEA6415........................................................................................................................

VPC3230D.......................................................................................................................

SDA55XX (S

TPA3002D2.....................................................................................................................................13

TDA98

TDA1308 .........................................................................................................................................16

PI5V330...........................................................................................................................................17

GM6015...........................................................................................................................................18

MST9883.........................................................................................................................................19

M74HC4052....................................................................................................................................21

MC34063.........................................................................................................................................22

MSP34X0G.......................................................................................................................

DS90C385.......................................................................................................................................26

NDS8947.........................................................................................................................................27

SERVICE MENU

OPTIONS MENU

APS WSS TEST

BLOCK DIAGRAM..................................................................................................................................35

CIRCUIT DI

DA988X).................................................................................................................................1

UND PROCESSOR............................................................................................1

E WITH T

R SDA55XX............................................................................................................2

DA5550)..............................................................................................................

85/86 ....................................................................................................................................15

SETTINGS.................................................................................................................28

SETTINGS..........................................................................................................

MENU..................................................................................................................34

AGRAMS.............................................................................................................................36

PA3002D2......................................................................................2

2048*8) EEPROM

E DRIVER TDA1308.........................................................................3

RNAL BLOCK

ST24C16..................................................................3

DIAGRAM .......................................................................4

............................1

.....................4

.....................5

....................9

................10

........12

...............23

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1. INTRODUCTION

20” TFT-LCD TV is a

interlacer

TFT TV is a progressive scan flicker free colour television with PC input, driving an WXGA (1366*768) panel with 16:9 aspect ratio. The chassis is capable of operation in PAL, SECAM, NTSC (playback) colour standards and multiple transmission standards as supplying 2x5W (10%THD) speakers. The chassis is equipped with two full SCART’s, one back-AV, one SVHS, one D-Sub 15 (PC) input, one PC stereo audio input and one line out (left and right) and one HP outputs.

and

scaler

Progressive

TV control system based on the

B/G, D/K, I/I’, and L/L’

-controller

SDA555X,

. Sound system output is

with

built-in

de-

2. TUNER

As the thickness of the TV set has a limit, a horizontal mounted tuner is used in the product, which is suitable for CCIR systems B/G, H, L/ I2C bus (PLL). Below you will find info on the Tuner in use.

General description of UV1316:

The UV1316 tuner belongs to the UV 1300 family of tuners, which are designed to meet a wide range of applications. It is a combined VHF, UHF tuner suitable for CCIR systems B/G, H, L, L’, I and I’. The low IF output impedance has been designed for direct drive of a wide variety of SAW filters with sufficient suppression of triple transient.

Features of UV1316:

1. Member of the UV1300 fam

2. Systems CCIR: B/G, H, L, L’, I and I’; OIRT: D/K

3. Digitally controlled (PLL) tuning via I2C-bus

4. Off-air channels, S-cable channels and Hyper band

5. Compact size

6. Complies to “CENELEC EN55020” and “EN55013”

L’, I/I’, and D/K. The tuning is ava

ily small sized UHF/VHF tuners

ilable through the digitally controlled

Pinning:

1. Gain control voltage (AGC) : 4.0V, Max: 4.5V

2. Tuning voltage

3. I²C-bus address select : Max: 5.5V

4. I²C-bus serial clock : Min:-0.3V, Max: 5.5V

5. I²C-bus serial data : Min:-0.3V, Max: 5.5V

6. Not connected

7. PLL supply voltage : 5.0V, Min: 4.75V, Max: 5.5V

8. ADC input

9. Tuner supply voltage : 33V, Min: 30V, Max: 35V

10. Symmetrical IF output 1

11. Symmetrical IF output 2

3. IF PART (TDA988X)

The TDA9885 is an alignment-free sing PLL. The TDA9886 is an alignment-free multistandard (PAL, SECAM and NTSC) vision and sound IF signal PLL demodulator for positive and negative modulation including sound AM and FM processing. Both devices can be used for TV, VT

le standard (without positive modulation) vision and sound IF signal

R, PC and set-top box applications.

4. MULTI STANDARD SOUND PROCESSOR

The MSP34x0G family of single-chip Multistandard Sound Processors covers the sound processing of all analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on a single chip. These TV sound processing ICs include versions for processing the multichannel television sound (MTS) signal conforming to the standard recommended by t The DBX noise reduction, or alternatively, Micronas Noise Reduction (MNR) is performed alignment free. Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio standard. Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA-J. The MSP 34x1G has optimum stereo performance without any adjustments.

he Broadcast Television Systems Committee (BTSC).

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5. AUDIO AMPLIFIER STAGE WITH TPA3002D2

The TPA3002D2 is a 9-W (per channel) efficient, Clas speakers. The TPA3002D2 can drive stereo speakers as low as 8 . The high efficiency of the TPA3002D2 eliminates the need for exter

nal heatsinks when playing music.

s-D audio amplifier for driving bridged-tied stereo

6. POWER

7. MICROCONTROLLER SDA55XX

7.1. General Features

• Feature selection via special function register

• Simultaneous reception of TTX

• Supply Voltage 2.5 and 3.3 V

• ROM version is used.

7.2. External Crystal and Programmable Clock Speed

• Single external 6MHz crystal, all nec

• CPU clock speed selectable vi

• Normal Mode 33.33 MHz CPU cl

7.3. Microcontroller Features

• 8bit 8051 instruction set compatible CPU.

• 33.33-MHz internal clock (max.)

• 0.360 ms (min.) instruction cycle

• Two 16-bit timers

• Watchdog timer

• Capture compare timer for infrared remote control decoding

• Pulse width modulation unit (2 channels 14 bit, 6 channels 8 bit)

• ADC (4 channels, 8 bit)

• UART (rxd, txd)

, VPS, PDC, and WSS (line 23)

essary clocks are generated internally

a special function registers.

ock, Power Save mode 8.33 MHz

7.4. Memory

• Up to 128 Kilobyte on Chip Program ROM

• Eight 16-bit data pointer registers (DPTR)

• 256-bytes on-chip Processor Internal RAM (IRAM)

• 128bytes extended stack memory.

• Display RAM and TXT/VPS/PDC/WSS-Acquisition

• UP to 16KByte on Chip Extended RAM (XRAM) consisting of;

- 1 Kilobyte on-chip ACQ-bu

- 1 Kilobyte on-chip extended-RAM (XRAM,

- 3-Kilobyte Display Memory

7.5. Display Features

• ROM Character set supports all East and West European Languages in single device

• Mosaic Graphic Character Set

• Parallel Display Attributes

• Single/Double Width/Height of Characters

• Variable Flash Rate

• Programmable Screen Size (2

• Flexible Character Matrixes (HxV) 12 x 9...16

• Up to 256 Dynamical Redefinable Characters in in Enhanced Mode

• CLUT with up to 4096 colour combinations

• Up to 16 Colours per DRCS Character

• One out of 8 Colours for Foreground and Backgr

ffer-RAM (access via MOVX)

access via MOVX) for user software

5 Rows x 33...64 Columns)

-Buffer directly accessible via MOVX

standard mode; 1024 Dynamical Redefinable Characters

ound Colours for 1-bit DRCS and ROM Characters

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7.6. ROM Characters

• Shadowing

• Contrast Reduction

• Pixel by Pixel Shiftable Cursor With up to 4 Different Colours

• Support of Progressive Scan and 100 Hz.

• 3 X 4Bits RGB-DACs On-Chip

• Free Programmable Pixel Clock from 10 MHz to 32MHz

• Pixel Clock Independent from CPU Clock

• Multinorm H/V-Display Synchronisation in Master or Slave Mode

7.7. Acquisition Features

• Multistandard Digital Data Slicer

• Parallel Multi-norm Slicing (TTX, VPS, WSS, CC, G+)

• Four Different Framing Codes Available

• Data Caption only limited by available Memory

• Programmable VBI-buffer

• Full Channel Data Slicing Supported

• Fully Digital Signal Processing

• Noise Measurement and Controlled Noise Compensation

• Attenuation Measurement and Compensation

• Group Delay Measurement and Compensation

• Exact Decoding of Echo Disturbed Signals

7.8. Ports

• One 8-bit I/O-port with open drain output and optional I 2 C Bus emulation support (Port0)

• Two 8-bit multifunction I/O-ports (Port1, Port3)

• One 4-bit port working as digital or analogue inputs for the ADC (Port2)

• One 2-bit I/O port with secondary function (P4.2, 4.3, 4.7)

• One 4-bit I/O-port with secondary function (P4.

0, 4.1, 4.4) (Not available in P-SDIP 52)

8. SERIAL ACCESS CMOS 16K

The ST24C16 is a 16Kbit electrically erasable programmable memory (EEPROM), organised as 8 blocks of 256*8 bits. The memory is compatible with the I²C standard, two wire serial interface, which uses a bidirectional data bus and serial clock. The memory carries a built-in 4 bit, unique device identification code (1010) corresponding to the I²C bus definition. This is used together with 1 chip enable input (E) so that up to 2*8K devices may be attached to the I²C bus and selected individually.

(2048*8) EEPROM ST24C16

9. CLASS AB STEREO HEADPHONE DRIVER TDA1308

The TDA1308 is an integrated class AB stereo headphone device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital audio applications.

driver contained in a DIP8 plastic package. The

10. SAW FILTERS

K3953M is an IF Filter for Video Applications. The pack L/L’. K9656M is an IF Filter for Audio Applications. The pack L/L’.

age is SIP5K. Supported st age is SIP5K. Supported st

andards are B/G, D/K, I, andards are B/G, D/K, I,

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11. IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM

LM1117 TDA9885/86 LM2576 TDA1308T LM317T PI5V330 ST24LC21 GM6015 TEA5114A MST9883 TEA6415 M74HC4052 VPC3230D MC34063 SDA55XX MSP3400G TPA3002D2 DS90C385

NDS8947

11.1. LM1117

11.1.1. General Description

The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at 800mA of load current. It has the same pin-out as National Semiconductor’s industry standard LM317. The LM1117 is available in an adjustable version, which can set the output voltage from 1.25V to 13.8V with only two external resistors. In addition, it is also available in The LM1117 offers current limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap reference to as-sure output voltage accuracy to within ±1%. The LM1117 series is available in SOT-223, TO-220, and TO-252 D-PAK packages. A minimum of 10µF tantalum capacitor is required at the output to improve the transient response and stability.

five fixed voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V.

11.1.2. Features

• Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions

• Space Saving SOT-223 Package

• Current Limiting and Thermal Protection

• Output Current 800mA

• Line Regulation 0.2% (Max)

• Load Regulation 0.4% (Max)

• Temperature Range — LM1117 0°C to 125°C

LM1117I -40°C to 125°C

11.1.3. Applications

• 2.85V Model for SCSI-2 Active Termination

• Post Regulator for Switching DC/DC Converter

• High Efficiency Linear Regulators

• Battery Charger

• Battery Powered Instrumentation

11.1.4. Connection Diagrams

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11.2. LM2576

11.2.1. General Description

The LM2576 series of regulators are monolithic integrated circuits ideally suited for easy and convenient design of a step–down switching regulator (buck converter). All circuits of this series are capable of driving a 3.0 A load with excellent line and load regulation. These devices are available in fixed output voltages of 3.3 V, 5.0 V, 12 V, 15 V, and an adjustable output version. These regulators were designed to minimize the number of external components to simplify the power supply design. Standard series of inductors optimized for use with the LM2576 are offered by several different inductor manufacturers. Since the LM2576 converter is a switch–mode power supply, its efficiency is significantly higher in comparison with popular three–terminal linear regulators, cases, the power dissipated is so low that no heatsink

especially with higher input voltages. In many

is required or its size could be reduced dramatically. A standard series of inductors optimized for use with the LM2576 are available from several different manufacturers. This feature greatly simplifie The LM2576 features include a guaranteed ±4% toleranc

s the design of switch–mode power supplies.

e on output voltage within specified input voltages and output load conditions, and ±10% on the oscillator frequency (±2% over 0°C to 125°C). External shutdown is included, featuring 80 mA (typical) sta

ndby current. The output switch includes cycle–by–cycle current limiting, as well as thermal shutdown for full protection under fault conditions.

11.2.2. Features

• 3.3 V, 5.0 V, 12 V, 15 V, and Adjustable Output Versions

• Adjustable Version Output Voltage Range, 1.23 to 37 V ±4% Maximum Over Line and Load Conditions

• Guaranteed 3.0 A Output Current

• Wide Input Voltage Range

• Requires Only 4 External Components

• 52 kHz Fixed Frequency Internal Oscillator

• TTL Shutdown Capability, Low Power Standby Mode

• High Efficiency

• Uses Readily Available Standard Inductors

• Thermal Shutdown and Current Limit Protection

• Moisture Sensitivity Level (MSL) Equals 1

11.2.3. Pin description

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11.3. LM317T

11.3.1. Description

The LM317T is an adjustable 3 terminal positive voltage regulator capable of supplying in excess of 1.5 amps over an output range of 1.25 to 37 volts. This voltage regulator is exceptionally easy to use and requires only two external resistors to set the output voltage. Further, it employs internal current limiting, thermal shutdown and safe area compensation, making it essentially blow–out proof. The LM317 serves a wide variety of applications including local, on card regulation. This device can also be used to make a programmable output regulator, or by connecting a fixed resistor between the adjustment and output, the LM317 can be used as a precision current regulator.

11.3.2. Features

• Output Current in Excess of 1.5 A

• Output Adjustable between 1.2 V and 37 V

• Internal Thermal Ov

erload Protection

• Internal Short Circuit Current Limiting Constant with Temperature

• Output Transistor Safe–Area Compensation

• Floating Operation for High Voltage Applications

• Available in Surface Mount D2PAK, and Standard 3–Lead Tr

ansistor Package

• Eliminates Stocking many Fixed Voltages

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11.4. ST24LC21

11.4.1. Description

The ST24LC21 is a 1K bit electrically erasable programmable memory (EEPROM), organized by 8 bits. This device can operate in two modes: Transmit Only mode and I2C bidirectional mode. When powered, the device is in Transmit Only mode with EEPROM data clocked out from the rising edge of the signal applied on VCLK. The device will switch to the I2C bidirectional mode upon the falling edge of the signal applied on SCL pin. The ST24LC21 can not switch from the I2C bidirectional mode to the Transmit Only mode (except when the power supply is removed). The device operates with a power supply value as low as 2.5V. Both Plastic Dual-in-Line and Plas

tic Small Outline packages are available.

11.4.2. Features

• 1 million Erase/Write cycles

• 40 years data retention

• 2.5V to 5.5V single supply voltage

• 400k Hz compatibility over the full range of supply voltage

• Two wire serial interface I2C bus compatible

• Page Write (Up To 8 Bytes)

• Byte, random and sequential read modes

• Self timed programming cycle

• Automatic address incrementing

• Enhanced ESD/Latch up

• Performances

11.4.3. Pin connections

DIP Pin connections CO Pin connections

NC: Not connected

Signal names

SDA Serial data Ad SCL Serial Clock (I2C mode) V

VCLK Clock transmit only mode

Supply voltage Ground

dress Input/Output

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11.5. TEA5114A

11.5.1. General description

This integrated circuit provides RGB switching allowing connections between peri TV plug, internal RGB generator and video processor in a TV set. The input signal black level is tied to the same reference voltage on each input in order to have no differential voltage when switching two RGB generators. An AC output signal higher than 2 Vpp makes gain going slowly down to 0dBto protect the TV set video amplifier from saturation. Fast blanking output is a logical OR between FB1 (Pin 8) and FB2 (Pin 10).

11.5.2. Features

• 25MHz Bandwidth

• Crosstalk : 55dB

• Short circuit to ground or VCCprotected

• Anti saturation gain changing

• Video switching

11.5.3. Pin Connections

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11.6. TEA6415

11.6.1. General description

The main function of the IC is to switch 8 video input sources on 6 outputs. Each output can be switched on only one of each input. On each input an alignment of the lowest level of the signal is made (bottom of synch. top for CVBS or black level for RGB signals). Each nominal gain between any input and output is

6.5dB. For D2MAC or Chroma signal the alignment is switched off by forcing, with an external resistor bridge, 5 V external resistor bridge). All the switching possibilities are changed through the BUS. Driving 75 needs an external transistor. It is possible to have the same input connected to several outputs. The starting configuration upon power on (power supply: 0 to 10V) is undetermined. In this case, 6 words of 16 bits are necessary to determine one configuration. In other case, 1 word of 16 bits is necessary to determine one configuration.

• 20MHz Bandwidth

• Cascadable with another TEA6415C (Internal address can be changed by pin 7 voltage)

• 8 Inputs (CVBS, RGB, MAC, CHROMA,...)

• 6 Outputs

• Possibility of MAC or chroma signal for each input by bridge

• Bus controlled

• 6.5dB gain between any input and output

• 55dB crosstalk at 5mHz

• Fully ESD protected

on the input. Each input can be used as a normal input or as a MAC or Chroma input (with

11.6.2. Features

switching-off the clamp with an external resistor

load

11.6.3. Pinning

1. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA

2. Data : Low level : -0.3V Max: 1.5V,

High level : 3.0V Max : Vcc+0.5V

3. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA

4. Clock : Low level : -0.3V Max: 1.5V,

High level : 3.0V Max : Vcc+0.5V

5. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA

6. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA

7. Prog

8. Input : Max : 2Vpp, Input Current: 1mA, Max: 3mA

9. Vcc : 12V

10. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA

11. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA

12. Ground

13. Output : 5.5Vpp, Min : 4.5Vpp

14. Output : 5.5Vpp, Min : 4.5Vpp

15. Output : 5.5Vpp, Min : 4.5Vpp

16. Output : 5.5Vpp, Min : 4.5Vpp

17. Output : 5.5Vpp, Min : 4.5Vpp

18. Output : 5.5Vpp, Min : 4.5Vpp

19. Ground

20. Input : Max : 2Vpp, Input Current : 1mA, Max : 3mA

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11.7. VPC3230D

11.7.1. General Description

The VPC 323xD is a high-quality, single-chip video front-end, which is targeted for 4:3 and 16:9, 50/60-Hz and 100/120 Hz TV sets. It can be combined with other members of the DIGIT3000 IC family (such as DDP 331x) and/or it can be used with 3rd-party products. The main features of the VPC 323xD are

• high-performance adaptive 4H comb filter Y/

C separator with adjustable vertical peaking

• multi-standard colour decoder PAL/NTSC/SECAM including all substandards

• four CVBS, one S-VHS input, one CVBS output

• two RGB/YC

r Cb

component inputs, one Fast Blank (FB) input

• integrated high-quality A/D converters and associated clamp and AGC circuits

• multi-standard sync processing

• linear horizontal scaling (0.25 ... 4), as well as

non-linear horizontal sc

aling ‘Panorama-vision’

• PAL+ preprocessing

• line-locked clock, data and sync, or 656-output interface

r C b

• peaking, contrast, brightness, color saturation and tint for RGB/ YC

and CVBS/ S-VHS

• high-quality soft mixer controlled by Fast Blank

• PIP processing for four picture sizes (1/4, 1/9,

• 15 predefined PIP display configurations

1/16 or 1/36 of normal size) with 8-bit resolution

and expert mode (fully programmable)

• control interface for external field memory

• I2C-bus interface

• one 20.25-MHz crystal, few external components

• 80-pin PQFP package

11.7.2. Pin Connections and Short Descriptions

NC = not connected LV = if not used, leave vacant X = obligatory; connect as described in circuit diagram SUPPLYA = 4.75...5.25 V, SUPPLYD = 3.15...3.45 V

Pin No. PQFP 80-pin

1 B1/CB1IN IN VREF Blue1/Cb1 Analog Component Input 2 G1/Y1IN IN VREF Green1/Y1 Analog Component Input 3 R1/CR1IN IN VREF Read1/Cr1 Analog Component Input 4 B2/CB2IN IN VREF Blue2/Cb2 Analog Component Input 5 G2/Y2IN IN VREF Green2/Y2 Analog Component Input 6 R2/CR2IN IN VREF Read2/Cr2 Analog Component Input 7 ASGF X Analog Shield GND 8 FFRSTWIN IN LV or GNDD FIFO Reset Write Input 9 V 10 V 11 GND 12 GND 13 SCL IN/OUT X I2C Bus Clock 14 SDA IN/OUT X I2C Bus Data 15 RESQ IN X Reset Input, Active Low 16 TEST IN GND 17 VGAV IN GND 18 YCOEQ IN GND 19 FFIE OUT LV FIFO Input Enable 20 FFWE OUT LV FIFO Write Enable 21 FFRSTW OUT LV FIFO Reset Write/Read 22 FFRE OUT LV FIFO Read Enable 23 FFOE OUT LV FIFO Output Enable 24 CLK20 IN/OUT LV Main Clock output 20.25 MHz 25 GND 26 V 27 LLC2 OUT LV Double Clock Output 28 LLC1 IN/OUT LV Clock Output 29 V

Pin Name Type Connection

(if not used)

SUPCAP SUPD

D CAP

SUPPA

SUPLLC

OUT X Digital Decoupling Circuitry Supply Voltage SUPPLYD X Supply Voltage, Digital Circuitry SUPPLYD X Ground, Digital Circuitry OUT X Digital Decoupling Circuitry GND

D D D

OUT X Pad Decoupling Circuitry GND OUT X Pad Decoupling Circuitry Supply Voltage

SUPPLYD X Supply Voltage, LLC Circuitry

Short Description

Test Pin, connect to GND

VGAV Input Y/C Output Enable Input, Active Low

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30 GND

LLC

31 Y7 OUT GND 32 Y6 OUT GND 33 Y5 OUT GND 34 Y4 OUT GND 35 GND 36 V

SUPY

37 Y3 OUT GND 38 Y2 OUT GND 39 Y1 OUT GND 40 Y0 OUT GND 41 C7 OUT GND 42 C6 OUT GND 43 C5 OUT GND 44 C4 OUT GND 45 V 46 GND

SUPC

47 C3 OUT GND 48 C2 OUT GND 49 C1 OUT GND 50 C0 OUT GND 51 GND 52 V

SUPSY

SUPPLYD X Ground, LLC Circuitry

Y Y Y Y

Picture Bus Luma (MSB) Picture Bus Luma Picture Bus Luma

Picture Bus Luma SUPPLYD X Ground, Luma Output Circuitry SUPPLYD X Supply Voltage, Luma Output Circuitry

Y Y Y Y C C C C

Picture Bus Luma

Picture Bus Luma (LSB)

Picture Bus Chroma (MSB)

Picture Bus Chroma

Picture Bus Chroma SUPPLYD X Supply Voltage, Chroma Output Circuitry SUPPLYD X Ground, Chroma Output Circuitry

C C C C

Picture Bus Chroma

Picture Bus Chroma (LSB) SUPPLYD X Ground Sync Pad Circuitry SUPPLYD X Supply Voltage, Sync Pad Circuitry

53 INTLC OUT LV Interlace Output 54 AVO OUT LV Active Video Output 55 FSY/HC/HSYA OUT LV Front Sync/ Horizontal Clamp Pulse/Front-End

Horizontal Sync Output

56 MSY/HS IN/OUT LV Main Sync/Horizontal Sync Pulse 57 VS OUT LV Vertical Sync Pulse 58 FPDAT/VSYA IN/OUT LV Front End/Back-End Data/Front-End Vertical Sync

Output

59 V

STBYY

SUPPLYA X Standby Supply Voltage

60 CLK5 OUT LV CCU 5 MHz Clock Output 61 NC - LV or GNDD Not Connected 62 XTAL1 IN X Analog Crystal Input 63 XTAL2 OUT X Analog Crystal Output 64 ASGF X Analog Shield GND 65 GND

SUPPLYA X Ground, Analog Front-End

66 VRT OUTPUT X Reference Voltage Top, Analog 67 I2CSEL IN X I2C Bus Address Select 68 ISGND SUPPLYA X Signal Ground for Analog Input, connect to GND 69 V

SUPF

SUPPLYA X Supply Voltage, Analog Front-End

70 VOUT OUT LV Analog Video Output 71 CIN IN LV Chroma/Analog Video 5 Input 72 VIN1 IN VRT Video 1 Analog Input 73 VIN2 IN VRT Video 2 Analog Input 74 VIN3 IN VRT Video 3 Analog Input 75 VIN4 IN VRT Video 4 Analog Input 76 V

SUPAI

77 GND

SUPPLYA X Supply Voltage, A

nalog Component Inputs Front-End

SUPPLYA X Ground, Analog Component Inputs Front-End

78 VREF OUTPUT X Reference Voltage Top, Analog Component Inputs

Front-End

79 FB1IN IN VREF Fast Blank Input 80 AISGND SUPPLYA X Signal Ground for Analog Component Inputs, connect

to GND

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11.8. SDA55XX (SDA5550)

11.8.1. General description

The SDA55XX is a single chip teletext decoder for decoding World System Teletext data as well as Video Programming System (VPS), Program Delivery Control (PDC), and Wide Screen Signalling (WSS) data used for PAL plus transmissions (Line 23). The device also supports Closed caption acquisition and decoding. The device provides an integrated general-purpose, fully 8051-compatible Microcontroller with television specific hardware features. Microcontroller

has been enhanced to provide powerful features such as memory banking, data pointers, and additional interrupts etc. The on-chip display unit for displaying Level 1.5 teletext data can also be used for customer defined on screen displays. Internal XRAM consists of up to16 Kbytes. Device has an internal ROM of up

to 128 KBytes. ROMless versions can access up to 1 MByte of external RAM and ROM. The SDA 55XX supports a wide range of standards including PAL, NTSC and contains a digital slicer for VPS, WSS, PDC, TTX and Closed Caption, an accelerating acquisition hardware module, a display generator for Level 1.5 TTX data and powerful On screen Display capabilities based on parallel attributes The 8-bit Microcontroller runs at 360 ns. cycle time (m

, and Pixel oriented characters (DRCS).

in.). Controller with dedicated hardware does most of the internal TTX acquisition processing, transfers data to/from external memory interface and receives/ transmits data via I2C-firmware user-interface. The slicer combined with dedicated hardware stores TTX data in a VBI buffer of 1 Kilobyte. The Microcontroller

firmware performs all the acquisition tasks (hamming and parity-checks, page search and evaluation of header control bits) once per field. Additionally, the firmware can provide high-end Teletext features like Packet-26-handling, FLOF, TOP and list-pages. The interface to user software is optimized for minimal overhead. SDA 55XX is realized in 0.25 micron technology with 2.5 V supply voltage and 3.3 V I/O (TTL compatible). The software and hardware development environment (TEAM) is available to simplify and speed up the development of the software and On Screen Display. TEAM stands for TVT Expert Application Maker. It improves the TV controller software quality in following aspects: – Shorter time to market – Re-usability – Target independent development – Verification and validation before targeting – General test concept – Graphical interface design requiring minimum programming and controller know how. – Modular and open tool chain,

configurable by customer.

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11.9. TPA3002D2

11.9.1. General Description

The TPA3002D2 is a 9-W (per channel) efficient, Clas

s-D audio amplifier for driving bridged-tied stereo speakers. The TPA3002D2 can drive stereo speakers as low as 8 . The high efficiency of the TPA3002D2 eliminates the need for exter

nal heatsinks when playing music.

11.9.2. Features

• 9-W/Ch Into an 8-

• Efficient, Class-D Operation Eliminates He

• 32-Step DC Volume Control From

Load From 12-V Supply

atsinks and Reduces Power Supply Requirements

40 dB to 36 dB

• Line Outputs For External Headphone Amplifier With Volume Control

• Regulated 5-V Supply Output for Powering TPA6110A2

• Space-Saving, Thermally-Enhanced PowerPAD

Packaging

• Thermal and Short-Circuit Protection.

11.9.3. Pinning

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11.10. TDA9885/86

11.10.1. General description

The TDA9885 is an alignment-free single standard (without positive modulation) vision and sound IF signal PLL. The TDA9886 is an alignment-free multistandard (PAL, SECAM and NTSC) vision and sound IF signal PLL demodulator for positive and negative modulation including sound AM and FM processing. Both devices can be used for TV, VTR, PC and set-top box applications.

11.10.2. Features

•

5 V supply voltage Gain controlled wide-band Vision Intermediate Frequency (VIF) amplifier (AC-coupled)

•

• Multistandard true synchronous demodulation with active carrier regeneration (very linear demodulation, good

intermodulation figures, reduced harmonics, excellent pulse response)

•

Gated phase detector for L/L accent standard

• Fully integrated VIF Voltage Controlled Oscillator (VCO), alignment-free; frequencies switchable for all

negative and positive modulated standards via I2C-bus

•

Digital acquisition help, VIF frequencies of 33.4, 33.9, 38.0, 38.9, 45.75 and 58.75 MHz 4 MHz reference frequency input [signal from Phase-Locked Loop (PLL) tuning system] or operating as crystal

•

oscillator

VIF Automatic Gain Control (AGC) detector for gain control, operating as peak sync detector for negative

•

modulated signals and as a peak white detector for positive modulated signals

Precise fully digital Automatic Frequency Control (AFC) detector with 4-bit digital-to-analog converter; AFC bits

•

via I2C -bus readable

TakeOver Point (TOP) adjustable via I2C-bus or alternatively with potentiometer

•

Fully integrated sound carrier trap for 4.5, 5.5, 6.0 and 6.5 MHz, controlled by FM-PLL oscillator Sound IF (SIF) input for single reference Quasi Split Sound (QSS) mode (PLL controlled)

•

• SIF AGC for gain controlled SIF amplifier; single reference QSS mixer able to operate in high performance

single reference QSS mode and in intercarrier mode, switchable via I2C-bus

•

AM demodulator without extra reference circuit Alignment-free selective FM-PLL demodulator with high linearity and low noise

•

• I

C-bus control for all functions

I2C-bus transceiver with pin programmable Module Address (MAD).

•

11.10.3. Pinning

SYMBOL PIN DESCRIPTION

VIF1 1

VIF2 OP1 FMPLL DEEM AFD DGND AUD TOP SDA SCL SIOMA n.c. TAGC REF VAGC CVBS AGND VPLL

AFC OP2 SIF1 SIF2

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

VIF differential input 1 VIF differential input 2 output 1 (open-collector) FM-PLL for loop filter de-emphasis output for capacitor AF decoupling input for capacitor digital ground audio output tuner AGC TakeOver Point (TOP) I2C-bus data input/output I2C-bus clock input sound intercarrier output and MAD select not connected tuner AGC output 4 MHz crystal or reference input VIF-AGC for capacitor; video output analog ground VIF-PLL for loop filter supply voltage (+5 V) AFC output output 2 (open-collector) SIF differential input 1 SIF differential input 2

(Not connected for TDA9885)

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11.11. TDA1308

11.11.1. General Description

The TDA1308 is an integrated class AB stereo headphone driver contained in an SO8 or a DIP8 plastic package. The device is fabricated in a 1 mm CMOS

process and has been primarily developed for portable

digital audio applications.

11.11.2. Features

Wide temperature range

•

No switch ON/OFF clicks Excellent power supply ripple rejection

•

Low power consumption Short-circuit resistant

•

High performance high signal-to-noise ratio

•

High slew rate Low distortion

•

Large output voltage swing.

11.11.3. Pinning

SYMBOL PIN DESCRIPTION PIN VALUE

OUTA 1 Output A (Voltage swing) Min : 0.75V, Max : 4.25V INA(neg) 2 Inverting input A Vo(clip) : Min : 1400mVrms INA(pos) 3 Non-inverting input A 2.5V V

INB(pos) 5 Non-inverting input B 2.5V INB(neg) 6 Inverting input B Vo(clip) : Min : 1400mVrms OUTB 7 Output B (Voltage swing) Min : 0.75V, Max : 4.25V V

4 Negative supply 0V

8 Positive supply 5V, Min : 3.0V, Max : 7.0V

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11.12. PI5V330

11.12.1. General description

Pericom Semiconductor’s PI5V series of mixed signal video circuits are produced in the Company’s advanced CMOS low-power technology, ac The PI5V330 is a true bidirectional Quad 2-channel mult RGB and composite video switching applications. T

hieving industry leading performance.

iplexer/demultiplexer that is recommended for both

he VideoSwitch™ can be driven from a current output RAMDAC or voltage output composite video source. Low ON-resistance and wide bandwidth make it ideal for exceptionally high current capability analog switches offered today. A single 5V s

which is far greater than most

upply is all that is required for operation.

video and other applications. Also this device has

The PI5V330 offers a high-performance, low-cost solution to switch between video sources. The application section describes the PI5V330 replac

ing the HC4053 multiplier and buffer/amplifier.

11.12.2. Features

• High-performance, low-cost solution to switch between video sources

• Wide bandwidth: 200 MHz

• Low ON-resistance: 3W

• Low crosstalk at 10 MHz: –58 dB

• Ultra-low quiescent power (0.1 µA typical)

• Single supply operation: +5.0V

• Fast switching: 10 ns

• High-current output: 100 mA

• Packages available: – 16-pin 300-mil wide plastic SOIC (S) – 16-pin 150-mil wide plastic SOIC (W) – 16-pin 150-mil wide plastic QSOP (Q)

11.12.3. Pin Descriptions

Pin Name Description

S1A, S2 S1B, S2 S1C, S2 S1D, S2

A B C D

Analog Video I/O

IN Select Input EN Enable DA, DB, DC, D

Analog Video I/O

GND Ground V

Power

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11.13. GM6015

11.13.1. General description

The Genesis Microchip 6015RD1 LCD TV reference board is a complete display processor for LCD, PDP and LCOS based televisions. The reference board dem Microchip gm6015 television controller IC. The gm6015 IC is a full-featured, dual-channel video processor with Genesis industry leading Crystal Ciema Plus

onstrates the processing capabilities of the Genesis

video scan conversion. The 6015RD1 board inputs analog YPbPr/RGB, NTSC/PAL/SECAM CVBS/YC, UHF/VHF and outputs digital RGB to an XGA LCD panel. A convenient on-screen display system provides easy

control of the board’s pr

ocessing capabilities. The design kit is complete with hardware and software. Software includes G-Probe debug software, GWizard register calculator and

G-TV application source code.

The 6015RD1 is a related reference board that outputs analog YpbPr/RGB.

11.13.2. Features

•

Dual channel, gm6015 based LCD TV system Industry leading Crystal Cinema Plus video scan conversion

•

Inputs:

i. Component analog

ii.

480/576I, 480/576P, 720P and 1080I HD

iii.

Dual NTSC/PAL/SECAM CVBS and YC

iv.

VGA, SVGA, XGA PC graphics

Separate, composite or sync on Y/G

vi. UHF/VHF RF (NTSC)

•

Default output with XGA LCD interface PCB:

i. Component analog

•

Other outputs:

ii. 8/16/20/24-bit 4:2:2/4:4:4 digital

iii.

480/576I, 480/576P, 720P and 1080I HD

iv.

VGA, SVGA, XGA PC graphics

Separate, composite or sync on Y/G

On-screen display (OSD) user interface with automated self running demonstration

•

Small form factor PCB

YPbPr/RGB

YpbPr/RGB

YCbCr/RGB

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11.14. MST9883

11.14.1. General Description

The MST9883C is a fully integrated analog interface for digitizing high-resolution RGB graphics signals from PC’s and workstations. With a sampling rate capability of up to 140 MHz, it can accurately support display resolutions up to 1280x1024 (SXGA) at 75 Hz. The clamped input circuits provide sufficient bandwidth to accurately digitize each pixel.

11.14.2. Features

• Triple ADC with 12 - 140 MHz Sampling Rate

• Integrated line locked PLL generates pixel clock from HSYNC

• Integrated clamp with timing generator

• Integrated Brightness & Contrast controls

• Pin Compatible with AD9883A

• 4:2:2 and 4:4:4 Output Format Mode

• BT656 output format mode*

• Black and mid-level precision clamp and calibration

11.14.3. Pin Descriptions

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11.15. M74HC4052

11.15.1. General description

The M74HC4052 is a dual four-channel analog MULTIPLEXER/DEMULTIPLEXER fabricated with silicon gate C2MOS technology and it is pinto pin compatible

with the equivalent metal gate CMOS4000B series. It contains 8 bidirectional and digitally controlled analog switches. A built-in level shifting is included to allow an input range up to 6V (peak) for an analog signal with digital control signal of 0 to 6V. V

supply pin is provided for analog input signals. It has an inhibit (INH) input terminal to disable all the

switches when high. For operation as a digital mu A and B control inputs select one channe

l out of four in each section.

All inputs are equipped with protection circuits agai

ltiplexer/demultiplexer, VEE is connected to GND.

nst static discharge and transient excess voltage.

11.15.2. Features

• LOW POWER DISSIPATION: ICC = 4µA (MAX.) at TA=25°C.

• LOGIC LEVEL TRANSLATION TO ENABLE 5V

LOGIC SIGNAL TO COMMUNICATE WITH ±5V

ANALOG SIGNAL

• LOW "ON" RESISTANCE: 70

TYP. (VCC - VEE = 4.5V)

TYP. (VCC - VEE = 9V)

• WIDE ANALOG INPUT VOLTAGE RANGE: ±6V

• FAST SWITCHING: tpd = 15ns (TYP.) at TA = 25 °C

• LOW CROSSTALK

BETWEEN SWITCHES

• HIGH ON/OFF OUTPUT VOLTAGE RATIO

• WIDE OPERATING SUPPLY VOLTAGE RANGE (V

- VEE) = 2V TO 12V

• LOW SINE WAVE DISTORTION: 0.02% at VCC - VEE = 9V

= V

• HIGH NOISE IMMUNITY: V

NIH

= 28 % VCC (MIN.)

NIL

11.15.3. Pin Connections and Descriptions

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11.16. MC34063

11.16.1. Description

The MC34063A Series is a monolithic control circuit containing the primary functions required for DC–to– DC converters. These devices consist of an internal temperature compensated reference, comparator, controlled duty cycle oscillator with an active current series was specifically designed to be incorpor

limit circuit, driver and high current output switch. This

ated in Step–Down and Step–Up and Voltage–Inverting

applications with a minimum number of external components.

11.16.2. Features

• Operation from 3.0 V to 40 V Input

• Low Standby Current

• Current Limiting

• Output Switch Current to 1.5 A

• Output Voltage Adjustable

• Frequency Operation to 100 kHz

• Precision 2% Reference

11.16.3. Pin connections

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11.17. MSP34X0G

MSP3400G

Multistandard Sound Processor Family

11.17.1. Introduction

tional block diagram of the MSP 34x0G. This new generation of TV sound processing ICs now includes versions for processing the multichannel television sound (MTS) signal conforming to the standard recommended by the Broadcast Television Systems Committee (BTSC). The DBX noise reduction, or alternatively, MICRONAS Noise Reduction (MNR) is performed alignment free. Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio standard. Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA-J. The MSP 34x0G has optimum stereo performance without any adjustments. All MSP 34x0G versions are pin and software downward compatible to the MSP 34x0D. The MSP 34x0G further simplifies controlling software. Standard se

lection requires a single I²C transmission only. The MSP 34x0G has built-in automatic functions: The IC is able to detect the actual sound standard automatically (Automatic Standard Detection). Furthermore, pilot levels and identification signals can be evaluated internally with subsequent switching between mono/stereo/bilingual; no I²C interaction is necessary (Automatic Sound Selection).

Source Select

I2S bus interface consists of five pins:

1. I2S_DA_IN1, I2S_DA_IN2: For input, four channels (t

wo channels per line, 2*16 bits) per sampling cycle

(32 kHz) are transmitted.

2. I2S_DA_OUT: For output, two channels (2*16 bi

ts) per sampling cycle (32 kHz) are transmitted.

3. I2S_CL: Gives the timing for the transmission of I2S serial data (1.024 MHz).

4. I2S_WS: The I2S_WS word strobe line defines the left and right sample.

11.17.2. Features

• Standard Selection with single I

C transmission

• Automatic Standard Detection of terrestrial TV standards

• Automatic Sound Selection (mono/stereo/bili

ngual), new registers MODUS, STATUS

• Two selectable sound IF (SIF) inputs

• Automatic Carrier Mute function

• Interrupt output programmable (indicating status change)

• Loudspeaker / Headphone channel with volu

me, balance, bass, treble, loudness

• AVC: Automatic Volume Correction

• Subwoofer output with programmable low-

pass and complementary high-pass filter

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• 5-band graphic equalizer for loudspeaker channel

• Spatial effect for loudspeaker channel

• Four Stereo SCART (line) inputs, on

e Mono input; two Stereo SCART outputs

• Complete SCART in/out switching matrix

• Two I2S inputs; one I2S output

• Dolby Pro Logic with DPL 351xA coprocessor

• All analog FM-Stereo A2 and satellite standards; AM-SECAM L standard

• Simultaneous demodulation of (very) high-deviation FM-Mono and NICAM

• Adaptive deemphasis for satellite (Wegener-Pan

da, acc. to ASTRA specification)

• ASTRA Digital Radio (ADR) together with DRP 3510A

• All NICAM standards

• Korean FM-Stereo A2 standard

11.17.3. Pin connections

NC = not connected; leave vacant LV = if not used, leave vacant OBL = obligatory; connect as described in circuit diagram DVSS: if not used, connect to DVSS AHVSS: connect to AHVSS

Pin No.

PLCC 68-pin

1 16 14 9 8 ADR_WS OUT LV ADR word strobe 2 - - - - NC LV Not connected 3 15 13 8 7 ADR_DA OUT LV ADR Data Output 4 14 12 7 6 I2S_DA_IN1 IN LV I2S1 data input 5 13 11 6 5 I2S_DA_OUT OUT LV I2S data output 6 12 10 5 4 I2S_WS IN/OUT LV I2S word strobe 7 11 9 4 3 I2S_CL IN/OUT LV I2S clock 8 10 8 3 2 I2C_DA IN/OUT OBL I2C data 9 9 7 2 1 I2C_CL IN/OUT OBL I2C clock 10 8 - 1 64 NC LV Not connected 11 7 6 80 63 STANDBYQ IN OBL Stand-by (low-active) 12 6 5 79 62 ADR_SEL IN OBL I2C bus address select 13 5 4 78 61 D_CTR_I/O_0 IN/OUT LV D_CTR_I/O_0 14 4 3 77 60 D_CTR_I/O_1 IN/OUT LV D_CTR_I/O_1 15 3 - 76 59 NC LV Not connected 16 2 - 75 58 NC LV Not connected 17 - - - - NC LV Not connected

18 1 2 74 57 AUD_CL_OUT OUT LV 19 64 1 73 56 TP LV Test pin

20 63 52 72 55 XTAL_OUT OUT OBL Crystal oscillator 21 62 51 71 54 XTAL_IN IN OBL Crystal oscillator 22 61 50 70 53 TESTEN IN OBL Test pin

23 60 49 69 52 ANA_IN2+ IN

24 59 48 68 51 ANA_IN- IN 25 58 47 67 50 ANA_IN1+ IN LV IF input 1

26 57 46 66 49 AVSUP OBL Analog power supply 5V

- - - 65 - AVSUP OBL Analog power supply 5V

- - - 64 - NC LV Not connected

- - - 63 - NC LV Not connected 27 56 45 62 48 AVSS OBL Analog ground

- - - 61 - AVSS OBL Analog ground 28 55 44 60 47 MONO_IN IN LV Mono input

- - - 59 - NC LV Not connected 29 54 43 58 46 VREFTOP OBL 30 53 42 57 45 SC1_IN_R IN LV SCART 1 input, right

31 52 41 56 44 SC1_IN_L IN LV SCART 1 input, left 32 51 - 55 43 ASG1 AHVSS Analog Shield Ground 1 33 50 40 54 42 SC2_IN_R IN LV SCART 2 input, right 34 49 39 53 41 SC2_IN_L IN LV SCART 2 input, left 35 48 - 52 40 ASG2 AHVSS Analog Shield Ground 2

PSDIP 64-pin

PSDIP 52-pin

PQFP 80-pin

PLQFP 64-pin

Pin Name

Type

Connection (if not used)

AVSS via 56 pF/LV

Short Description

Audio clock output (18.432 MHz)

IF Input 2 (can be left vacant, only if IF input 1 is also not in use) IF common (can be left vacant, only if IF input 1 is also not in use)

Reference voltage IF A/D converter

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36 47 38 51 39 SC3_IN_R IN LV SCART 3 input, right 37 46 37 50 38 SC3_IN_L IN LV SCART 3 input, left 38 45 - 49 37 ASG4 AHVSS Analog Shield Ground 4 39 44 - 48 36 SC4_IN_R IN LV SCART 4 input, right 40 43 - 47 35 SC4_IN_L IN LV SCART 4 input, left 41 - - 46 - NC LV or AHVSS Not connected 42 42 36 45 34 AGNDC OBL Analog reference voltage 43 41 35 44 33 AHVSS OBL Analog ground

- - - 43 - AHVSS OBL Analog ground

- - - 42 - NC LV Not connected

- - - 41 - NC LV Not connected 44 40 34 40 32 CAPL_M OBL Volume capacitor MAIN 45 39 33 39 31 AHVSUP OBL Analog power supply 8V 46 38 32 38 30 CAPL_A OBL Volume capacitor AUX 47 37 31 37 29 SC1_OUT_L OUT LV SCART output 1, left 48 36 30 36 28 SC1_OUT_R OUT LV SCART output 1, right 49 35 29 35 27 VREF1 OBL Reference ground 1 50 34 28 34 26 SC2_OUT_L OUT LV SCART output 2, left 51 33 27 33 25 SC2_OUT_R OUT LV SCART output 2, right 52 - - 32 - NC LV Not connected 53 32 - 31 24 NC LV Not connected 54 31 26 30 23 DACM_SUB OUT LV Subwoofer output 55 30 - 29 22 NC LV Not connected 56 29 25 28 21 DACM_L OUT LV Loudspeaker out, left 57 28 24 27 20 DACM_R OUT LV Loudspeaker out, right 58 27 23 26 19 VREF2 OBL Reference ground 2 59 26 22 25 18 DACA_L OUT LV Headphone out, left 60 25 21 24 17 DACA_R OUT LV Headphone out, right

- - - 23 - NC LV Not connected

- - - 22 - NC LV Not connected 61 24 20 21 16 RESETQ IN OBL Power-on-reset 62 23 - 20 15 NC LV Not connected 63 22 - 19 14 NC LV Not connected 64 21 19 18 13 NC LV Not connected 65 20 18 17 12 I2S_DA_IN2 IN LV I2S2-data input 66 19 17 16 11 DVSS OBL Digital ground

- - - 15 - DVSS OBL Digital ground

- - - 14 - DVSS OBL Digital ground 67 18 16 13 10 DVSUP OBL Digital power supply 5V

- - - 12 - DVSUP OBL Digital power supply 5V

- - - 11 - DVSUP OBL Digital power supply 5V 68 17 15 10 9 ADR_CL OUT LV ADR clock

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11.18. DS90C385

11.18.1. General Description

The DS90C385 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 85 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 297.5 Mbytes/sec. Also available is the DS90C365 that converts 21 bits of LVCMOS/LVTTL data into three LVDS (Low Voltage Differential Signaling) data streams. Both transmitters can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe Receiver (DS90CF386/DS90CF366) wi

thout any translation logic. The DS90C385 is also offered in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package which provides a 44% reduction in PCB footprint compared to the TSSOP package. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.

11.18.2. Features

20 to 85 MHz shift clock support Best–in–Class Set & Hold Times on TxINPUTs Tx power consumption <130 mW (typ) @85MHz Grayscale Tx Power-down mode <200µW (max) Supports VGA, SVGA, XGA and Single/Dual Pixel SXGA Narrow bus reduces cable size and cost Up to 2.38 Gbps throughput Up to 297.5 Megabytes/sec bandwidth 345 mV (typ) swing LVDS devices for low EMI PLL requires no external components Compatible with TIA/EIA-644 LVDS standard Low profile 56-lead or 48-lead TSSOP package DS90C385 also available in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package

11.18.3. Pinning

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11.19. NDS8947

11.19.1. General Description

These P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line

power loss, and resistance to transients are needed.

11.19.2. Features

4A, -30V. R

= 0.065W @ VGS = -10V

DS(ON)

= 0.1W @ VGS = -4.5V.

DS(ON)

High density cell design for extremely low R

DS(ON).

High power and current handling capability in a widely used surface mount package. Dual MOSFET in surface mount package.

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12. SERVICE MENU SETTINGS

All system, geometry and white balance alignments are performed in production service mode. Before starting the production mode alignments, make sure that all manual adjustments are done correctly. To start production mode alignments enter the main menu by pressing “ digits 4, 7, 2 and 5 buttons respectively. The following menu appears on the screen.

Service

Options...

ps Wss Test…

TFT17 Version Date Time

After entering the Service menu, you can access its items by pressing “ / ” buttons. In order to enter

selected menu, use “ Entire service menu parameters of TFT TV are listed below.

” buttons. To exit the service menu press “

” button and then press the

button.

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12.1. OPTIONS MENU SETTINGS

In order to enter Options menu, move the cursor to Options Service Menu and press “

” button. The following menu appears on the screen.

parameter by pressing “

/ ” buttons in

Option 1

Hue First APS A.P.S. Headphone VSR DBE Subwoofe Lineout DolbyPro Equalize

00: On

There are 50 items in the OPTIONS menu, but 11 of them are seen when you first enter the menu. Using

/ ”

“

buttons remaining items can be seen.

Hue On/Off

Enables / disables Hue option in Picture menu.

First APS On/Off

If ON, TV starts with APS menu at Start-up.

A.P.S On/Off

Enables / disables Automatic Programming System.

Headphone On/Off

Enables / disables the usage of the

HP and HP related items in sound menu.

VSR On/Off

Enables / disables VSR (Virtual surround).

DBE On/Off

Enables / disables DBE (Dynamic Bass Enhancement).

Subwoofer On/Off

Enables / disables Subwoofer.

Lineout On/Off

Enables / disables Lineout.

DolbyPro On/Off

Enables / disables Dolby prologic system.

Equalizer On/Off

Enables / disables equalizer system.

BG On/Off

Enables / disables BG Standard.

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Option 2

D I L L’ AUS NZ NM FM Prs Avl On Nicam Prs Avl On Scart Prs Avl On Scart Volume Avl On

11: On

DK On/Off

Enables / disables DK Standard.

I On/Off

Enables / disables I Standard.

L On/Off

Enables / disables L Standard.

L On/Off

Enables / disables L’ Standard.

AUS On/Off

Enables / disables AUS Standard.

NZ On/Off

Enables / disables NZ Standard.

NM On/Off

Enables / disables NM Standard.

FM Prs Avl On

Adjusts the FM Prescaler value, when Automatic Volume Levelling is On Min. Value: 0000 00000 Max. Value: 00FF 00255

Nicam Prs Avl On

Adjusts the Nicam Prescaler value, when Automatic Volume Levelling is On Min. Value: 0000 00000 Max. Value: 00FF 00255

Scart Prs Avl On

Adjusts the Scart Prescaler value, when Automatic Volume Levelling is On Min. Value: 0000 00000 Max. Value: 00FF 00255

Scart Volume Avl On

Adjusts the Scart Volume value, when Automatic Volume Levelling is On Min. Value: 0000 00000 Max. Value: 00FF 00255

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Option 3

FM Prs Avl Of Nicam Prs Avl Of Scart Prs Avl Of Scart Volume Avl Of HOTEL VoD AVL Top Text Fast Text TXT Language IF Frequency

Sound

22: 002

FM Prs Avl Off

Adjusts the FM Prescaler value, when Automatic Volume Levelling is Off Min. Value: 0000 00000 Max. Value: 00FF 00255

Nicam Prs Avl Off

Adjusts the Nicam Prescaler value, when Automatic Volume Levelling is Off Min. Value: 0000 00000 Max. Value: 00FF 00255

Scart Prs Avl Off

Adjusts the Scart Prescaler value, when Automatic Volume Levelling is Off Min. Value: 0000 00000 Max. Value: 00FF 00255

Scart Volume Avl Off

Adjusts the Scart Volume value, when Automatic Volume Levelling is Off Min. Value: 0000 00000 Max. Value: 00FF 00255

Hotel VoD On/Off

Enables / disables Hotel Video-on-Demand.

AVL On/Off

Enables / disables Automatic Volume Levelling System.

Top Text On/Off

Enables / disables TopText.

Fast Text On/Off

Enables / disables FastText.

TXT Language

Switches between Teletext Language Groups. Min. Value: 0000 00000 Max. Value: 0004 00004

IF Frequency

Adjusts the IF Frequency. Min. Value: 0000 00000 Max. Value: 00FF 00255

Sound On/Off

Enables / disables Sound.

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Option 4

Carrie RC_Options

V-1 V-2

-Video YPbP PC RGB MENU MIX Hotel Mode LDL

33: Of

Carrier On/Off

Enables / disables sound Carrier feature.

RC_Options On/Off

Enables / disables Remote control usage for Service menu.

AV-1 On/Off

Enables / disables AV-1.

AV-2 On/Off

Enables / disables AV-2.

S-Video On/Off

Enables / disables S-Video.

YPbPr On/Off

Enables / disables YPbPr.

PC RGB On/Off

Enables / disables PC.

MENU On/Off

Enables / disables semi-transparent MENU.

MIX

Enables / disables teletext MIX mode. Enable: 00000001 Disable: 00000000

Hotel Mode On/Off

Enables / disables Hotel mode.

LDLY

Adjusts the Luna / chroma DeLaY value. Min. Value: 0000 00000 Max. Value: 0007 00007

20” TFT TV Service Manual 08/09/2005

Page 35

Option 5

AGC PIP PAP Full PC RGB PC RGB AUDIO Othe

44:

000

AGC

Adjusts the Automatic Gain Control value. Min. Value: 0000 00000 Max. Value: 001F 00031

PIP On/Off

Enables / disables PIP (Picture-In-Picture).

PAP On/Off

Enables / disables PAP (P

icture-And-Picture).

Full PC RGB On/Off

Enables / disables PC standby feature.

PC RGB AUDIO On/Off

Enables / disables PC Audio.

Other

Enables / disables sear

ch mode for DK Standard. Enable: 00000001 Disable: 00000000

20” TFT TV Service Manual 08/09/2005

Page 36

12.2. APS WSS TEST MENU

In order to enter Aps Wss Test menu, move the cursor to Aps Wss Test parameter by pressing “ / ”

buttons in Service Menu and press “

” button. The following menu appears on the screen.

ApsWss Test

Programme VPS Pdc Format 1 PdcFormat 2 Name Wss

P 01

CNN C12 24

There are 6 items in the Aps Wss Test menu. Programme

VPS Pdc Format 1 Pdc Format 2 Name Wss

20” TFT TV Service Manual 08/09/2005

Page 37

+VIN

13. BLOCK DIAGRAM

Page 38

14. CIRCUIT DIAGRAMS

Page 39

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