vestel 17MB01 Schematic

15” TFT TV

SERVICE MANUAL

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TABLE OF CONTENTS

1. INTRODUCTION...................................................................................................................................1

2. TUNER..................................................................................................................................................1

3. TDA988X...............................................................................................................................................1

4. MULTI STANDARD SOUND PROCESSOR ........................................................................................1

5. AUDIO AMPLIFIER STAGE WITH TDA7299.......................................................................................1

6. POWER.................................................................................................................................................2

7. MICROCONTROLLER SDA55XX ........................................................................................................2

7.1. General Features...............................................................................................................................2

7.2. External Crystal and Programmable Clock Speed............................................................................ 2

7.3. Microcontroller Features....................................................................................................................2

7.4. Memory..............................................................................................................................................2

7.5. Display Features................................................................................................................................2

7.6. ROM Characters................................................................................................................................2

7.7. Acquisition Features..........................................................................................................................3

7.8. Ports ..................................................................................................................................................3

8. SERIAL ACCESS CMOS 16K (2048*8) EEPROM ST24C16 ..............................................................3

9. CLASS AB STEREO HEADPHONE DRIVER TDA1308......................................................................3

10. SAW FILTERS ......................................................................................................................................3

11. IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM....................................................................4

11.1. TEA5114A......................................................................................................................................4

11.1.1. General description..............................................................................................................4

11.1.2. Features.................................................................................................................................4

11.1.3. Pin Connections ...................................................................................................................4

11.2. MC34167........................................................................................................................................5

11.2.1. General Description..............................................................................................................5

11.2.2. Features.................................................................................................................................5

11.3. LM7808..........................................................................................................................................5

11.3.1. Description............................................................................................................................5

11.3.2. Features.................................................................................................................................5

11.4. SDA55XX.......................................................................................................................................6

11.4.1. General description..............................................................................................................6

11.5. TFMS5360 .....................................................................................................................................6

11.5.1. Description............................................................................................................................6

11.5.2. Features.................................................................................................................................6

11.6. SST37VF040..................................................................................................................................7

11.6.1. Description............................................................................................................................7

11.6.2. Features.................................................................................................................................7

11.6.3. Pin Description .....................................................................................................................7

11.7. ST24LC21......................................................................................................................................8

11.7.1. Description............................................................................................................................8

11.7.2. Features.................................................................................................................................8

11.7.3. Pin connections....................................................................................................................8

11.8. VPC3230D.....................................................................................................................................9

11.8.1. General Description..............................................................................................................9

11.8.2. Pin Connections and Short Descriptions........................................................................... 9

11.9. AL300...........................................................................................................................................11

11.9.1. General Description............................................................................................................11

11.9.2. Features...............................................................................................................................11

11.9.3. Pin Definition and Description ..........................................................................................11

11.10. LM1086........................................................................................................................................14

11.10.1. Description ..........................................................................................................................14

11.10.2. Features...............................................................................................................................14

11.10.3. Applications ........................................................................................................................14

11.10.4. Connection Diagrams.........................................................................................................14

11.11. LM1117........................................................................................................................................15

11.11.1. General Description............................................................................................................15

11.11.2. Features...............................................................................................................................15

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11.11.3. Applications ........................................................................................................................15

11.11.4. Connection Diagrams.........................................................................................................15

11.12. TDA7299......................................................................................................................................16

11.12.1. Description ..........................................................................................................................16

11.12.2. Features...............................................................................................................................16

11.12.3. Pin Connection ...................................................................................................................16

11.13. DS90C385.................................................................................................................................... 17

11.13.1. General Description............................................................................................................17

11.13.2. Features...............................................................................................................................17

11.13.3. Pin Description ...................................................................................................................17

11.14. TDA1308......................................................................................................................................18

11.14.1. General Description............................................................................................................18

11.14.2. Features...............................................................................................................................18

11.14.3. Pinning.................................................................................................................................18

11.15. TL431...........................................................................................................................................19

11.15.1. Description ..........................................................................................................................19

11.15.2. Features...............................................................................................................................19

11.15.3. Pin Configurations..............................................................................................................19

11.16. 24C16........................................................................................................................................... 20

11.16.1. Description ..........................................................................................................................20

11.16.2. Features...............................................................................................................................20

11.16.3. Pin Configuration................................................................................................................20

11.16.4. Pin Description ...................................................................................................................20

11.17. AL875...........................................................................................................................................21

11.17.1. General Description............................................................................................................21

11.17.2. General Features ................................................................................................................21

11.17.3. Pin Definition and Description ..........................................................................................21

11.18. 74HC244A.................................................................................................................................... 23

11.18.1. Description ..........................................................................................................................23

11.18.2. General Features ................................................................................................................23

11.18.3. Pin Description ...................................................................................................................23

11.19. ICS1523.......................................................................................................................................24

11.19.1. Description ..........................................................................................................................24

11.19.2. Features...............................................................................................................................24

11.20. MC34063......................................................................................................................................25

11.20.1. Description ..........................................................................................................................25

11.20.2. Features...............................................................................................................................25

11.20.3. Pin connections ..................................................................................................................25

11.21. TDA9885/86.................................................................................................................................26

11.21.1. General description ............................................................................................................26

11.21.2. 13.13.2.Features..................................................................................................................26

11.21.3. 13.13.3.Pinning....................................................................................................................26

11.22. MSP34X0G..................................................................................................................................27

11.22.1. Introduction.........................................................................................................................27

11.22.2. Features...............................................................................................................................27

11.22.3. Pin connections ..................................................................................................................28

11.23. SAA3010T....................................................................................................................................30

11.23.1. 14.22.1.Description .............................................................................................................30

11.23.2. 14.22.2.Features..................................................................................................................30

11.23.3. 14.22.3.Pinning....................................................................................................................30

12. SERVICE MENU SETTINGS..............................................................................................................31

12.1. ADJUST MENU SETTINGS ........................................................................................................31

OPTIONS MENU SETTINGS.....................................................................................................................33

12.2. APS WSS TEST MENU............................................................................................................... 38

13. BLOCK DIAGRAM ..............................................................................................................................39

14. CIRCUIT DIAGRAMS .........................................................................................................................40

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1. INTRODUCTION

TFT TV is a progressive scan flicker free colour television with PC input, driving a XGA panel with 4:3 aspect ratio. The chassis is capable of operation in PAL, SECAM, NTSC (playback) colour standards and multiple transmission standards as B/G, D/K, I/I’, and L/L´. Sound system output is supplying 2x2W (10%THD) for left and right outputs of 8Ω speakers. The chassis is equipped with one full SCART, one front-AV, one SVHS, one D-Sub 15 (PC) input and one line out (left and right) and one HP outputs.

2. TUNER

The hardware and software of the TV is suitable for tuners, supplied by different companies, which are selected from the Service Menu. These tuners can be combined VHF, UHF tuners suitable for CCIR systems B/G, H, L, L´, I/I´, and D/K. The tuning is available through the digitally controlled I2C bus (PLL). Below you will find info on one of the Tuners in use.

General description of UV1316:

The UV1316 tuner belongs to the UV 1300 family of tuners, which are designed to meet a wide range of applications. It is a combined VHF, UHF tuner suitable for CCIR systems B/G, H, L, L’, I and I’. The low IF output impedance has been designed for direct drive of a wide variety of SAW filters with sufficient suppression of triple transient.

Features of UV1316:

1. Member of the UV1300 family small sized UHF/VHF tuners

2. Systems CCIR: B/G, H, L, L’, I and I’; OIRT: D/K

3. Digitally controlled (PLL) tuning via I2C-bus

4. Off-air channels, S-cable channels and Hyperband

5. World standardised mechanical dimensions and world standard pinning

6. Compact size

7. Complies to “CENELEC EN55020” and “EN55013” Pinning:

1. Gain control voltage (AGC) : 4.0V, Max: 4.5V

2. Tuning voltage

3. I²C-bus address select : Max: 5.5V

4. I²C-bus serial clock : Min:-0.3V, Max: 5.5V

5. I²C-bus serial data : Min:-0.3V, Max: 5.5V

6. Not connected

7. PLL supply voltage : 5.0V, Min: 4.75V, Max: 5.5V

8. ADC input

9. Tuner supply voltage : 33V, Min: 30V, Max: 35V

10. Symmetrical IF output 1

11. Symmetrical IF output 2

3. TDA988X

The TDA9885 is an alignment-free single standard (without positive modulation) vision and sound IF signal PLL. The TDA9886 is an alignment-free multistandard (PAL, SECAM and NTSC) vision and sound IF signal PLL demodulator for positive and negative modulation including sound AM and FM processing. Both devices can be used for TV, VTR, PC and set-top box applications.

4. MULTI STANDARD SOUND PROCESSOR

The MSP 34x0G family of single-chip Multistandard Sound Processors covers the sound processing of all analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on a single chip. Signal conforming to the standard by the Broadcast Television Systems Committee (BTSC). The DBX noise reduction, or alternatively, MICRONAS Noise Reduction (MNR) is performed alignment free. Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio standard.

5. AUDIO AMPLIFIER STAGE WITH TDA7299

The TDA7299 is an audio class-AB amplifier assembled in SO package specially designed for sound cards application. By utilizing two TDA7299, chassis operates as a stereo TV set. TDA7299 has stand-by feature

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for low stand-by power consumption by using pin #3. It can deliver 2W without clipping at 12V/8Ω applications.

6. POWER

MC34167 is a power switch regulator, which can output 5V from 12V up to 5A. Utilising a power MOSFET inside works at a very high efficiency without producing excessive heat. This IC is the main supply for the voltages used in the main board. Using the pin 5 (stand-by) of IC, TFT TV can have low stand-by power consumption.

7. MICROCONTROLLER SDA55XX

7.1. General Features

• Feature selection via special function register

• Simultaneous reception of TTX, VPS, PDC, and WSS (line 23)

• Supply Voltage 2.5 and 3.3 V

• ROM version is used.

7.2. External Crystal and Programmable Clock Speed

• Single external 6MHz crystal, all necessary clocks are generated internally

• CPU clock speed selectable via special function registers.

• Normal Mode 33.33 MHz CPU clock, Power Save mode 8.33 MHz

7.3. Microcontroller Features

• 8bit 8051 instruction set compatible CPU.

• 33.33-MHz internal clock (max.)

• 0.360 ms (min.) instruction cycle

• Two 16-bit timers

• Watchdog timer

• Capture compare timer for infrared remote control decoding

• Pulse width modulation unit (2 channels 14 bit, 6 channels 8 bit)

• ADC (4 channels, 8 bit)

• UART(rxd,txd)

7.4. Memory

• Up to 128 Kilobyte on Chip Program ROM

• Eight 16-bit data pointer registers (DPTR)

• 256-bytes on-chip Processor Internal RAM (IRAM)

• 128bytes extended stack memory.

• Display RAM and TXT/VPS/PDC/WSS-Acquisition-Buffer directly accessible via MOVX

• UP to 16KByte on Chip Extended RAM (XRAM) consisting of;

- 1 Kilobyte on-chip ACQ-buffer-RAM (access via MOVX)

- 1 Kilobyte on-chip extended-RAM (XRAM, access via MOVX) for user software

- 3 Kilobyte Display Memory

7.5. Display Features

• ROM Character set supports all East and West European Languages in single device

• Mosaic Graphic Character Set

• Parallel Display Attributes

• Single/Double Width/Height of Characters

• Variable Flash Rate

• Programmable Screen Size (25 Rows x 33...64 Columns)

• Flexible Character Matrixes (HxV) 12 x 9...16

• Up to 256 Dynamical Redefinable Characters in standard mode; 1024 Dynamical Redefinable Characters in Enhanced Mode

• CLUT with up to 4096 colour combinations

• Up to 16 Colours per DRCS Character

• One out of 8 Colours for Foreground and Background Colours for 1-bit DRCS and ROM Characters

7.6. ROM Characters

• Shadowing

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• Contrast Reduction

• Pixel by Pixel Shiftable Cursor With up to 4 Different Colours

• Support of Progressive Scan and 100 Hz.

• 3 X 4Bits RGB-DACs On-Chip

• Free Programmable Pixel Clock from 10 MHz to 32MHz

• Pixel Clock Independent from CPU Clock

• Multinorm H/V-Display Synchronisation in Master or Slave Mode

7.7. Acquisition Features

• Multistandard Digital Data Slicer

• Parallel Multi-norm Slicing (TTX, VPS, WSS, CC, G+)

• Four Different Framing Codes Available

• Data Caption only limited by available Memory

• Programmable VBI-buffer

• Full Channel Data Slicing Supported

• Fully Digital Signal Processing

• Noise Measurement and Controlled Noise Compensation

• Attenuation Measurement and Compensation

• Group Delay Measurement and Compensation

• Exact Decoding of Echo Disturbed Signals

7.8. Ports

• One 8-bit I/O-port with open drain output and optional I 2 C Bus emulation support (Port0)

• Two 8-bit multifunction I/O-ports (Port1, Port3)

• One 4-bit port working as digital or analogue inputs for the ADC (Port2)

• One 2-bit I/O port with secondary function (P4.2, 4.3, 4.7)

• One 4-bit I/O-port with secondary function (P4.0, 4.1, 4.4) (Not available in P-SDIP 52)

8. SERIAL ACCESS CMOS 16K (2048*8) EEPROM ST24C16

The ST24C16 is an 16Kbit electrically erasable programmable memory (EEPROM), organised as 8 blocks of 256*8 bits. The memory is compatible with the I²C standard, two wire serial interface, which uses a bidirectional data bus and serial clock. The memory carries a built-in 4 bit, unique device identification code (1010) corresponding to the I²C bus definition. This is used together with 1 chip enable input (E) so that up to 2*8K devices may be attached to the I²C bus and selected individually.

9. CLASS AB STEREO HEADPHONE DRIVER TDA1308

The TDA1308 is an integrated class AB stereo headphone driver contained in a DIP8 plastic package. The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital audio applications.

10. SAW FILTERS

K3953M is an IF Filter for Video Applications. The package is SIP5K. Supported standards are B/G, D/K, I, L/L’. K9656M is an IF Filter for Audio Applications. The package is SIP5K. Supported standards are B/G, D/K, I, L/L’.

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11. IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM

TEA5114A DS90C385 MC34167 TDA1308T LM7808 TL431 SDA55XX 24C16 TFMS5360 AL875 SST37VF040 74HC244A ST24LC21 ICS1523 VPC3230D MC34063 AL300 TDA9885/86 LM1086 MSP3400G LM1117 SAA3010T TDA7299

11.1. TEA5114A

11.1.1. General description

This integrated circuit provides RGB switching allowing connections between peri TV plug, internal RGB generator and video processor in a TV set. The input signal black level is tied to the same reference voltage on each input in order to have no differential voltage when switching two RGB generators. An AC output signal higher than 2 Vpp makes gain going slowly down to 0dBto protect the TV set video amplifier from saturation. Fast blanking output is a logical OR between FB1 (Pin 8) and FB2 (Pin 10).

11.1.2. Features

• 25MHz Bandwidth

• Crosstalk : 55dB

• Short circuit to ground or VCC protected

• Anti saturation gain changing

• Video switching

11.1.3. Pin Connections

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11.2. MC34167

11.2.1. General Description

The MC34167, MC33167 series are high performance fixed frequency power switching regulators that contain the primary functions required for dc–to–dc converters. This series was specifically designed to be incorporated in step–down and voltage–inverting configurations with a minimum number of external components and can also be used cost effectively in step–up applications. These devices consist of an internal temperature compensated reference, fixed frequency oscillator with on–chip timing components, latching pulse width modulator for single pulse metering, high gain error amplifier, and a high current output switch. Protective features consist of cycle–by–cycle current limiting, under voltage lockout, and thermal shutdown. Also included is a low power standby mode that reduces power supply current to 36 mA.

11.2.2. Features

• Output Switch Current in Excess of 5.0 A

• Fixed Frequency Oscillator (72 kHz) with On–Chip Timing

• Provides 5.05 V Output without External Resistor Divider

• Precision 2% Reference

• 0% to 95% Output Duty Cycle

• Cycle–by–Cycle Current Limiting

• Under voltage Lockout with Hysteresis

• Internal Thermal Shutdown

• Operation from 7.5 V to 40 V

• Standby Mode Reduces Power Supply Current to 36 mA

• Economical 5–Lead TO–220 Package with Two Optional Leadforms

• Also Available in Surface Mount D 2 PAK Package

• Moisture Sensitivity Level (MSL) Equals 1

11.3. LM7808

11.3.1. Description

The L7800 series of three-terminal positive regulators is available in TO-220 TO-220FP TO-3 and D 2 PAK packages and several fixed output voltages, making it useful in a wide range of applications. These regulators can provide local on-card regulation, eliminating the distribution problems associated with single point regulation. Each type employs internal current limiting, thermal shutdown and safe area protection, making it essentially indestructible. If adequate heat sinking is provided, they can deliver over 1A output current. Although designed primarily as fixed voltage regulators, these devices can be used with external components to obtain adjustable voltages and currents.

11.3.2. Features

• Output Current Up To 1.5 A

• Output Voltages of 5; 5.2; 6; 8; 8.5; 9; 12; 15; 18; 24V

• Thermal Over load protection

• Short Circuit Protection

• Output Transition SOA Protection

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11.4. SDA55XX

11.4.1. General description

The SDA55XX is a single chip teletext decoder for decoding World System Teletext data as well as Video Programming System (VPS), Program Delivery Control (PDC), and Wide Screen Signalling (WSS) data used for PAL plus transmissions (Line 23). The device also supports Closed caption acquisition and decoding. The device provides an integrated general-purpose, fully 8051-compatible Microcontroller with television specific hardware features. Microcontroller has been enhanced to provide powerful features such as memory banking, data pointers, and additional interrupts etc. The on-chip display unit for displaying Level 1.5 teletext data can also be used for customer defined on screen displays. Internal XRAM consists of up to16 Kbytes. Device has an internal ROM of up to 128 KBytes. ROMless versions can access up to 1 MByte of external RAM and ROM. The SDA 55XX supports a wide range of standards including PAL, NTSC and contains a digital slicer for VPS, WSS, PDC, TTX and Closed Caption, an accelerating acquisition hardware module, a display generator for Level 1.5 TTX data and powerful On screen Display capabilities based on parallel attributes, and Pixel oriented characters (DRCS). The 8-bit Microcontroller runs at 360 ns. cycle time (min.). Controller with dedicated hardware does most of the internal TTX acquisition processing, transfers data to/from external memory interface and receives/ transmits data via I2C-firmware user-interface. The slicer combined with dedicated hardware stores TTX data in a VBI buffer of 1 Kilobyte. The Microcontroller firmware performs all the acquisition tasks (hamming and parity-checks, page search and evaluation of header control bits) once per field. Additionally, the firmware can provide high-end Teletext features like Packet-26-handling, FLOF, TOP and list-pages. The interface to user software is optimized for minimal overhead. SDA 55XX is realized in 0.25 micron technology with 2.5 V supply voltage and 3.3 V I/O (TTL compatible). The software and hardware development environment (TEAM) is available to simplify and speed up the development of the software and On Screen Display. TEAM stands for TVT Expert Application Maker. It improves the TV controller software quality in following aspects: – Shorter time to market – Re-usability – Target independent development – Verification and validation before targeting – General test concept – Graphical interface design requiring minimum programming and controller know how. – Modular and open tool chain, configurable by customer.

11.5. TFMS5360

11.5.1. Description

The TFMS5360 is a miniature receiver for infrared remote control systems.

11.5.2. Features

• Photo detector and preamplifier in one.

• 36 KHZ

• Pin diode and preamp

• IR filter.

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11.6. SST37VF040

11.6.1. Description

The SST37VF512/010/020/040 devices are 64K x8 / 128Kx8 / 256K x8 / 512K x8 CMOS, Many-Time Programmable (MTP), low cost flash, manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST37VF512/010/020/040 can be electrically erased and programmed at least 1000 times using an external programmer, e.g., to change the contents of devices in inventory. The SST37VF512/010/020/040 have to be erased prior to programming. These devices conform to JEDEC standard pinouts for byte-wide flash memories. Featuring high performance Byte-Program, the SST37VF512/010/020/040 provide a typical Byte-Pro-gram time of 10 µs. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with an endurance of at least 1000 cycles. Data retention is rated at greater than 100 years. The SST37VF512/010/020/040 are suited for applications that require infrequent writes and low power nonvolatile storage. These devices will improve flexibility, efficiency and performance while matching the low cost in nonvolatile applications that currently use UV-EPROMs, OTPs, and mask ROMs.

11.6.2. Features

• Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8

• 2.7-3.6V Read Operation

• Superior Reliability – Endurance: At least 1000 Cycles – Greater than 100 years Data Retention

• Low Power Consumption: – Active Current: 10 mA (typical) – Standby Current: 2 µA (typical)

• Fast Read Access Time: – 70 ns, 90 ns

• Latched Address and Data

• Fast Byte-Program Operation: – Byte-Program Time: 10 µs (typical) – Chip Program Time:

0.6 seconds (typical) for SST37VF512

1.2 seconds (typical) for SST37VF010

2.4 seconds (typical) for SST37VF020

4.8 seconds (typical) for SST37VF040

• Electrical Erase Using Programmer – Does not require UV source – Chip-Erase Time: 100 ms (typical)

• CMOS I/O Compatibility

• JEDEC Standard Byte-wide Flash EEPROM Pinouts

• Packages Available – 32-lead PLCC – 32-lead TSOP (8mm x 14mm) – 32-pin PDIP

11.6.3. Pin Description

Symbol Pin name Functions

-A0 Address Inputs To provide memory addresses.

DQ7-DQ0 CE# Chip Enable

WE# Write Enable To program or erase (WE# = VIL pulse during Program or Erase) OE# Output Enable To gate the data output buffers during Read operation when low V

NC No Connection Unconnected pins.

1. AMS = Most significant address AMS = A15 for SST37VF512, A16 for SST37VF010, A17 for SST37VF020, and A18 for SST37VF040

Data Input/output To output data during Read cycles and receive input data during Program

Power Supply To provide 3.0V supply (2.7-3.6V) Ground

cycles. The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low.

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11.7. ST24LC21

11.7.1. Description

The ST24LC21 is a 1K bit electrically erasable programmable memory (EEPROM), organized by 8 bits. This device can operate in two modes: Transmit Only mode and I2C bidirectional mode. When powered, the device is in Transmit Only mode with EEPROM data clocked out from the rising edge of the signal applied on VCLK. The device will switch to the I2C bidirectional mode upon the falling edge of the signal applied on SCL pin. The ST24LC21 can not switch from the I2C bidirectional mode to the Transmit Only mode (except when the power supply is removed). The device operates with a power supply value as low as 2.5V. Both Plastic Dual-in-Line and Plastic Small Outline packages are available.

11.7.2. Features

• 1 million Erase/Write cycles

• 40 years data retention

• 2.5V To 5.5V single supply voltage

• 400k Hz compatibility over the full range of supply voltage

• Two wire serial interface I2C bus compatible

• Page Write (Up To 8 Bytes)

• Byte, random and sequential read modes

• Self timed programming cycle

• Automatic address incrementing

• Enhanced ESD/Latch up

• Performances

11.7.3. Pin connections

DIP Pin connections CO Pin connections

NC: Not connected

Signal names

SDA Serial data Address Input/Output SCL Serial Clock (I2C mode) Vcc Supply voltage Vss Ground VCLK Clock transmit only mode

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11.8. VPC3230D

11.8.1. General Description

The VPC 323xD is a high-quality, single-chip video front-end, which is targeted for 4:3 and 16:9, 50/60-Hz and 100/120 Hz TV sets. It can be combined with other members of the DIGIT3000 IC family (such as DDP 331x) and/or it can be used with 3rd-party products. The main features of the VPC 323xD are

• high-performance adaptive 4H comb filter Y/C separator with adjustable vertical peaking

• multi-standard colour decoder PAL/NTSC/SECAM including all substandards

• four CVBS, one S-VHS input, one CVBS output

• two RGB/YCr Cb component inputs, one Fast Blank (FB) input

• integrated high-quality A/D converters and associated clamp and AGC circuits

• multi-standard sync processing

• linear horizontal scaling (0.25 ... 4), as well as non-linear horizontal scaling ‘Panorama-vision’

• PAL+ preprocessing

• line-locked clock, data and sync, or 656-output interface

• peaking, contrast, brightness, color saturation and tint for RGB/ YC r C b and CVBS/ S-VHS

• high-quality soft mixer controlled by Fast Blank

• PIP processing for four picture sizes (1/4, 1/9, 1/16 or 1/36 of normal size) with 8-bit resolution

• 15 predefined PIP display configurations and expert mode (fully programmable)

• control interface for external field memory

• I2C-bus interface

• one 20.25-MHz crystal, few external components

• 80-pin PQFP package

11.8.2. Pin Connections and Short Descriptions

NC = not connected LV = if not used, leave vacant X = obligatory; connect as described in circuit diagram SUPPLYA = 4.75...5.25 V, SUPPLYD = 3.15...3.45 V

Pin No. PQFP 80-pin

1 B1/CB1IN IN VREF Blue1/Cb1 Analog Component Input 2 G1/Y1IN IN VREF Green1/Y1 Analog Component Input 3 R1/CR1IN IN VREF Read1/Cr1 Analog Component Input 4 B2/CB2IN IN VREF Blue2/Cb2 Analog Component Input 5 G2/Y2IN IN VREF Green2/Y2 Analog Component Input 6 R2/CR2IN IN VREF Read2/Cr2 Analog Component Input 7 ASGF X Analog Shield GNDF 8 FFRSTWIN IN LV or GNDD FIFO Reset Write Input 9 V 10 V 11 GNDD SUPPLYD X Ground, Digital Circuitry 12 GND 13 SCL IN/OUT X I2C Bus Clock 14 SDA IN/OUT X I2C Bus Data 15 RESQ IN X Reset Input, Active Low 16 TEST IN GNDD Test Pin, connect to GNDD 17 VGAV IN GNDD VGAV Input 18 YCOEQ IN GNDD Y/C Output Enable Input, Active Low 19 FFIE OUT LV FIFO Input Enable 20 FFWE OUT LV FIFO Write Enable 21 FFRSTW OUT LV FIFO Reset Write/Read 22 FFRE OUT LV FIFO Read Enable 23 FFOE OUT LV FIFO Output Enable 24 CLK20 IN/OUT LV Main Clock output 20.25 MHz 25 GNDPA OUT X Pad Decoupling Circuitry GND 26 V 27 LLC2 OUT LV Double Clock Output 28 LLC1 IN/OUT LV Clock Output

Pin Name Type Connection

OUT X Digital Decoupling Circuitry Supply Voltage

SUPCAP

SUPPLYD X Supply Voltage, Digital Circuitry

SUPD

OUT X Digital Decoupling Circuitry GND

CAP

OUT X Pad Decoupling Circuitry Supply Voltage

SUPPA

(if not used)

Short Description

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29 V 30 GND

SUPPLYD X Supply Voltage, LLC Circuitry

SUPLLC

SUPPLYD X Ground, LLC Circuitry

LLC

31 Y7 OUT GNDY Picture Bus Luma (MSB) 32 Y6 OUT GNDY Picture Bus Luma 33 Y5 OUT GNDY Picture Bus Luma 34 Y4 OUT GNDY Picture Bus Luma 35 GNDY SUPPLYD X Ground, Luma Output Circuitry 36 V

SUPPLYD X Supply Voltage, Luma Output Circuitry

SUPY

37 Y3 OUT GNDY Picture Bus Luma 38 Y2 OUT GNDY Picture Bus Luma 39 Y1 OUT GNDY Picture Bus Luma 40 Y0 OUT GNDY Picture Bus Luma (LSB) 41 C7 OUT GNDC Picture Bus Chroma (MSB) 42 C6 OUT GNDC Picture Bus Chroma 43 C5 OUT GNDC Picture Bus Chroma 44 C4 OUT GNDC Picture Bus Chroma 45 V

SUPPLYD X Supply Voltage, Chroma Output Circuitry

SUPC

46 GNDC SUPPLYD X Ground, Chroma Output Circuitry 47 C3 OUT GNDC Picture Bus Chroma 48 C2 OUT GNDC Picture Bus Chroma 49 C1 OUT GNDC Picture Bus Chroma 50 C0 OUT GNDC Picture Bus Chroma (LSB) 51 GNDSY SUPPLYD X Ground Sync Pad Circuitry 52 V

SUPPLYD X Supply Voltage, Sync Pad Circuitry

SUPSY

53 INTLC OUT LV Interlace Output 54 AVO OUT LV Active Video Output 55 FSY/HC/HSYA OUT LV Front Sync/ Horizontal Clamp Pulse/Front-End

Horizontal Sync Output 56 MSY/HS IN/OUT LV Main Sync/Horizontal Sync Pulse 57 VS OUT LV Vertical Sync Pulse 58 FPDAT/VSYA IN/OUT LV Front End/Back-End Data/Front-End Vertical Sync

Output 59 V

SUPPLYA X Standby Supply Voltage

STBYY

60 CLK5 OUT LV CCU 5 MHz Clock Output 61 NC - LV or GNDD Not Connected 62 XTAL1 IN X Analog Crystal Input 63 XTAL2 OUT X Analog Crystal Output 64 ASGF X Analog Shield GNDF 65 GNDF SUPPLYA X Ground, Analog Front-End 66 VRT OUTPUT X Reference Voltage Top, Analog 67 I2CSEL IN X I2C Bus Address Select 68 ISGND SUPPLYA X Signal Ground for Analog Input, connect to GNDF 69 V

SUPPLYA X Supply Voltage, Analog Front-End

SUPF

70 VOUT OUT LV Analog Video Output 71 CIN IN LV Chroma/Analog Video 5 Input 72 VIN1 IN VRT Video 1 Analog Input 73 VIN2 IN VRT Video 2 Analog Input 74 VIN3 IN VRT Video 3 Analog Input 75 VIN4 IN VRT Video 4 Analog Input 76 V

SUPPLYA X Supply Voltage, Analog Component Inputs Front-End

SUPAI

77 GNDAI SUPPLYA X Ground, Analog Component Inputs Front-End 78 VREF OUTPUT X Reference Voltage Top, Analog Component Inputs

Front-End 79 FB1IN IN VREF Fast Blank Input 80 AISGND SUPPLYA X Signal Ground for Analog Component Inputs, connect

to GNDAI

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11.9. AL300

11.9.1. General Description

The AL300 is designed to enable simple connection from PC’s or video devices to flat panel displays. It provides LCD/PDP monitor and projector manufacturers with a low-cost, easy solution to bring TV or PC video to LCD panels. The AL300 is equipped with a high quality zoom engine that automatically maintains full screen output display, regardless of the resolution of the incoming signal. The input video can be linearly and independently zoomed in the x and y directions. The AL300 also provides de-interlacing, filtering, and scaling support for interlaced video to be displayed on a LCD panel. Two integrated On Screen Display (OSD) windows provide overlay of a control menu, text, or caption on the output display. With the internal OSD RAM, OSD bitmaps of up to 8K pixels are supported. With optional external userdefined font table ROM, the AL300 OSD functionality is very flexible with font size and display location; virtually all languages and fonts are supported. Special OSD effects such as translucency and blinking offer the manufacturer a unique and vivid way of presenting monitor status, control menu, or other display information. Used with an AL875 (high speed 3-channel ADC with PLL, 100-pin QFP), the AL300 (in 160pin QFP) offers the best cost-performance and total solution for LCD monitors or projectors, or other flat panel devices.

11.9.2. Features

• Converts PC’s or TV’s signals for flat panel displays

• Supports active matrix up to 1280x1024 resolution

• De-interlacing support for video inputs

• Automatic screen positioning support

• Fully programmable zoom ratios

• Independent linear zoom in H and V directions

• Supports single and dual pixel per clock panels

• Dithering logic to enhance color resolution for 12-bit or 18-bit panels

• Built-in high speed PLL

• User-definable font table supporting different languages and font sizes

• Two built-in OSD windows

• I2C programmable

• No external memory required

• Single 3.3 volt power with 5 volt tolerant I/O

• 160-pin 28x28 mm PQFP package

11.9.3. Pin Definition and Description

Pin Name Type Pin # Note Video Interface

TVCLK IN (CMOSd) 1 TVHREF IN (CMOSd) 2

TVVS IN (CMOSs) 3 TVHS IN (CMOSs) 4 Video Horizontal Sync Signal

Graphic Interface

GVS IN (CMOSs) 6 GVH IN (CMOSs) 7 GHREF IN (CMOS) 8 GCLK IN (CMOSd) 9 Graphic Input Clock R/YIN<7:0> IN (CMOS) 11-18

G/UVIN<7:0> IN (CMOS) 20-27

BIN<7:0> IN (CMOS) 29-36

Host Interface

HOSTCLK OUT (CMOS) 38 Buffered Output of the Clock Input for Host Interface such as a

Video Clock from Video Source Video Horizontal Active Data Reference This signal is used to indicate valid data of the YUV input. Video Vertical Sync Signal

Graphic Vertical Sync Signal Graphic Horizontal Sync Signal Graphic Horizontal Active Data Reference

Red Input When in RGB Mode Y Input When in CCIR601 422 and 444 Modes Green Input When in RGB Mode CbCr Input When in CCIR601 422 Mode Cb Input When in CCIR601 444 Mode Refer to register #1Bh for details. Blue Input When in RGB Mode Cr Input When in CCIR601 444 Mode Refer to register #1Bh for details.

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Micro-controller XOUT OUT (CMOS) 39 XIN IN (CMOS) 40

IREQ OUT (CMOS) 41 Interrupt Request, active high SCL IN (CMOSs) 42 SDA INOUT

(COMSsu) GOUT1 OUT (CMOS) 81 GOUT2 OUT (CMOS) 82 GOUT3 OUT (CMOS) 83

Configuration

PWRDN IN (CMOSd) 46

I2CADDR IN (CMOSd) 47

YUVIN IN (CMOSd) 48

Test1 IN (CMOSd) 49 Test2 IN (CMOSd) 50

Panel/Display Interface

RB<7:0> OUT (CMOS) 52-55,

GB<7:0> OUT (CMOS) 62-65,

BB<7:0> OUT (CMOS) 72-75,

PCLKA OUT (CMOS) 84 PCLKB OUT (CMOS) 85 Lagging Pixel Clock of Interleaved Video Output for Right data in

SCLK OUT (CMOS) 86 PHS OUT (CMOS) 88 PVS OUT (CMOS) 89 Panel/Display Vsync. Can be programmed to either polarity. PDSPEN OUT (CMOS) 90

RA<7:0> OUT (CMOS) 92-95,

GA<7:0> OUT (CMOS)

BA<7:0> OUT (CMOS)

PLL (Phase Lock Loop) Interface

IHSREF OUT (CMOS)

57-60

67-70

77-80

97-100

102-105, 107-110

112-115, 117-120

123 Input Hsync Reference, buffered and polarity adjusted, usually for

Crystal Output Crystal Input; the frequency provided is for I2C sampling and for output reference timing when input sync signals are missing or undetectable. Usually in the range of 10~50MHz.

I2C Serial Clock Input I2C Serial Data Input/Output

General Purpose Output. Connected to Register 0x1B bit 2 General Purpose Output. Connected to Register 0x1B bit 3 General Purpose Output. Connected to Register 0x1B bit 1

Power Down 0, Normal Operation 1, Power Down I2C Bus Slave Address Select 0, write address = 70, read address = 71 1, write address = 72, read address = 73 YUV Input 0, RGB Format Video Input 1, CCIR YUV Format Video Input Refer to RIN, GIN, BIN pins Test Pin Test Pin

Right Pixel of Interleaved Red Output in Dual Pixel Mode Valid when Register 0x43 bit4 = ‘1’. Data are output with PCLKB. For AL300 ver. A, the B data lag A data by 90° (half SCLK). For AL300 ver. B, A and B data are aligned. Right Pixel of Interleaved Green Output in Dual Pixel Mode Valid when Register 0x43 bit4 = ‘1’. Data are output with PCLKB. For AL300 ver. A, the B data lag A data by 90° (half SCLK). For AL300 ver. B, A and B data are aligned. Right Pixel of Interleaved Blue Output in Dual Pixel Mode Valid when Register 0x43 bit4 = ‘1’. Data are output with PCLKB. For AL300 ver. A, the B data lag A data by 90° (half SCLK). For AL300 ver. B, A and B data are aligned. Leading Pixel Clock of Interleaved Video Output for Right data in Dual Pixel Mode. Polarity is programmable

Dual Pixel Mode. Polarity is programmable. Default PCLKB lags PCLKA by 180° (one SCLK). Display Pixel Clock (for single pixel per clock mode) Panel/Display Hsync. Can be programmed to either polarity.

Panel/Display Display Enable; used to indicate active output pixels (HDE). Can be programmed to either polarity. Red Data Output When Register 0x43 bit4 = ‘0’, data are output every SCLK. When Register 0x43 bit4 = ‘1’, the left pixel of interleaved red data are output with PCLKA. Green Data Output When Register 0x43 bit4 = ‘0’, data are output every SCLK. When Register 0x43 bit4 = ‘1’, the left pixel of interleaved red data are output with PCLKA. Blue Data Output When Register 0x43 bit4 = ‘0’, data are output every SCLK. When Register 0x43 bit4 = ‘1’, the left pixel of interleaved red data are output with PCLKA.

input PLL to regenerate input pixel clock. Always positive polarity. When no input HSYNC is present, virtual IHSREF can be

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generated by programming registers 41h & 42h

OHSREF OUT (CMOS)

OHSFB OUT (CMOS) OCLK IN (CMOSd) OPLLCLK OUT (CMOS)

VCOIN IN

OSD ROM Interface

ROMDATA <7:0> ROMADDR <15:0>

Power, Ground, Reset RESETB PLLVCC PLLGND VCC

GND

NC Remarks: CMOSd : CMOS with internal pull-down CMOSs : CMOS with Schmitt trigger CMOSsu : CMOS with Schmitt trigger and internal pull-up

IN (CMOSd)

OUT (CMOS)

IN (CMOS)

POWER

GROUND

POWER

GROUND

124 Output Hsync Reference, for output PLL to generate output pixel

125 Output PLL Feedback; works with OHSREF to generate output 126 Output Clock, connected to OPLLCLK when internal PLL is used; 127 Recovered Output Clock generated by the internal PLL

129 PLL External VCO Filter Circuit Input 132-135,

137-140 160-157, 155-152, 150-147, 145-142

122 Reset, active low 128 VCC of Internal PLL, 3.3V 130 GND of Internal PLL 19, 37, 51, 61, 66, 91, 96, 111, 116, 121, 141, 151 5, 10, 28, 45, 56, 71, 76, 87, 101, 106, 131, 136, 146, 156 44 No connection

clock. Always positive polarity. OHSREF is either equivalent to IHSREF or the equally divided IHSREF. Refer to registers 03h, 10h~13h.

pixel clock connected to external PLL clock output when external PLL is used

OSD ROM Data OSD ROM Address

Digital VCC, 3.3V

Digital Ground

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11.10. LM1086

11.10.1. Description

The LM1086 is a series of low dropout positive voltage regulators with a maximum dropout of 1.5V at 1.5A of load current. It has the same pin-out as National Semiconductor’s industry standard LM317. The LM1086 is available in an adjustable version, which can set the output voltage with only two external resistors. It is also available in five fixed voltages: 2.5V, 2.85V, 3.3V, 3.45V and 5.0V. The fixed versions integrate the adjust resistors. The LM1086 circuit includes a zener trimmed band-gap reference, current limiting and thermal shutdown.

11.10.2. Features

Available in 2.5V, 2.85V, 3.3V, 3.45V, 5V and Adjustable Versions Current Limiting and Thermal Protection Output Current 1.5A Line Regulation 0.015% (typical) Load Regulation 0.1% (typical)

11.10.3. Applications

SCSI-2 Active Terminator High Efficiency Linear Regulators Battery Charger Post Regulation for Switching Supplies Constant Current Regulator Microprocessor Supply

11.10.4. Connection Diagrams

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11.11. LM1117

11.11.1. General Description

The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at 800mA of load current. It has the same pin-out as National Semiconductor’s industry standard LM317. The LM1117 is available in an adjustable version, which can set the output voltage from 1.25V to 13.8V with only two external resistors. In addition, it is also available in five fixed voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V. The LM1117 offers current limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap reference to as-sure output voltage accuracy to within ±1%. The LM1117 series is available in SOT-223, TO-220, and TO-252 D-PAK packages. A minimum of 10µF tantalum capacitor is required at the output to improve the transient response and stability.

11.11.2. Features

• Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions

• Space Saving SOT-223 Package

• Current Limiting and Thermal Protection

• Output Current 800mA

• Line Regulation 0.2% (Max)

• Load Regulation 0.4% (Max)

• Temperature Range — LM1117 0°C to 125°C — LM1117I -40°C to 125°C

11.11.3. Applications

• 2.85V Model for SCSI-2 Active Termination

• Post Regulator for Switching DC/DC Converter

• High Efficiency Linear Regulators

• Battery Charger

• Battery Powered Instrumentation

11.11.4. Connection Diagrams

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11.12. TDA7299

11.12.1. Description

The device TDA7299 is a new technology Mono Audio Amplifier in SO package specially designed for 12V sound cards application. Thanks to the fully complementary output configuration the device delivers a rail voltage swing without need of boostrap capacitors.

11.12.2. Features

Can deliver 2W without clipping at 12V/8Ω Internal fixed gain 20dB No boucherot cell Thermal protection AC short circuit protection SVR capacitor for better ripple Rejection Low turn-on/off pop Stand-by mode

11.12.3. Pin Connection

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11.13. DS90C385

11.13.1. General Description

The DS90C385 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 85 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 595 Mbps per LVDS data channel. Using an 85 MHz clock, the data throughput is 297.5 Mbytes/sec. Also available is the DS90C365 that converts 21 bits of LVCMOS/LVTTL data into three LVDS (Low Voltage Differential Signaling) data streams. Both transmitters can be programmed for Rising edge strobe or falling edge strobe through a dedica ted pin. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe Receiver (DS90CF386/DS90CF366) without any translation logic. The DS90C385 is also offered in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package which provides a 44 % reduction in PCB footprint compared to the TSSOP package. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.

11.13.2. Features

• 20 to 85 MHz shift clock support

• Best–in–Class Set & Hold Times on TxINPUTs

• Tx power consumption <130 mW (typ) @85MHz Grayscale

• Tx Power-down mode <200µW (max)

• Supports VGA, SVGA, XGA and Dual Pixel SXGA.

• Narrow bus reduces cable size and cost

• Up to 2.38 Gbps throughput

• Up to 297.5 Megabytes/sec bandwidth

• 345 mV (typ) swing LVDS devices for low EMI

• PLL requires no external components

• Compatible with TIA/EIA-644 LVDS standard

• Low profile 56-lead or 48-lead TSSOP package

• DS90C385 also available in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package

11.13.3. Pin Description

DS90C385 MTD56 (TSSOP) Package Pin Description-FPD Link Transmitter

Pin Name I/O No. Description

TxIN TxOUT+

TxOUT- TxCLKIN R_FB TxCLK OUT+ TxCLK OUT- PWR DOWN

Vcc GND PLL Vcc PLL GND LVDS Vcc LVDS GND

I 28 O 4

O 4 I 1 I 1 O 1 O 1 I 1

I 3 I 4 I 1 I 2 I 1 I 3

TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines —FPLINE, FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable). Positive LVDS differentiaI data output.

Negative LVDS differential data output. TTL Ievel clock input. Pin name TxCLK IN.

Programmable strobe select Positive LVDS differential clock output.

Negative LVDS differential clock output. TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at

power down. Power supply pins for TTL inputs.

Ground pins for TTL inputs. Power supply pin for PLL.

Ground pins for PLL. Power supply pin for LVDS outputs. Ground pins for LVDS outputs.

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DS90C385SLC SLC64A Package Pin Description-FPD Link Transmitter

Pin Name I/O No. Description

TxIN TxOUT+ TxOUT- TxCLKIN R_FB TxCLK OUT+ TxCLK OUT- PWR DOWN

Vcc GND PLL Vcc PLL GND LVDS Vcc LVDS GND NC

I 28 O 4 O 4 I 1 I 1 O 1 O 1 I 1

I 3 I 5 I 1 I 2 I 2 I 4 6

TTL level input. Positive LVDS differentiaI data output. Negative LVDS differential data output. TTL Ievel clock input. The rising edge acts as data strobe. Pin name TxCLK IN. Programmable strobe select. HIGH = rising edge, LOW = falling edge. Positive LVDS differential clock output. Negative LVDS differential clock output. TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low

current at power down. Power supply pins for TTL inputs.

Ground pins for TTL inputs. Power supply pin for PLL.

Ground pins for PLL. Power supply pin for LVDS outputs. Ground pins for LVDS outputs. Pins not connected.

11.14. TDA1308

11.14.1. General Description

The TDA1308 is an integrated class AB stereo headphone driver contained in an SO8 or a DIP8 plastic package. The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital audio applications.

11.14.2. Features

• Wide temperature range

• No switch ON/OFF clicks

• Excellent power supply ripple rejection

• Low power consumption

• Short-circuit resistant

• High performance

• high signal-to-noise ratio

• High slew rate

• Low distortion

• Large output voltage swing.

11.14.3. Pinning

SYMBOL PIN DESCRIPTION PIN VALUE

OUTA 1 Output A (Voltage swing) Min : 0.75V, Max : 4.25V INA(neg) 2 Inverting input A Vo(clip) : Min : 1400mVrms INA(pos) 3 Non-inverting input A 2.5V VSS 4 Negative supply 0V INB(pos) 5 Non-inverting input B 2.5V INB(neg) 6 Inverting input B Vo(clip) : Min : 1400mVrms OUTB 7 Output B (Voltage swing) Min : 0.75V, Max : 4.25V VDD 8 Positive supply 5V, Min : 3.0V, Max : 7.0V

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11.15. TL431

11.15.1. Description

The TL431 is a 3-terminal adjustable shunt voltage regulator providing a highly accurate 1 % band gap reference. TL431 acts as an open-loop error amplifier with a 2.5V temperature compensation reference. The TL431 thermal stability, wide operating current (150mA) and temperature range (0.to 105.makes it suitable for all variety of application that are looking for a low cost solution with high performance. The output voltage may be adjusted to any value between VREF and 36 volts with two external resistors. The TL431 is operating in full industrial temperature range of 0°C to 105°C. The TL431 is available in TO-92, SO-8, SOT-89 and SOT23-5 packages.

11.15.2. Features

• Trimmed Band gap to 1%

• Wide Operating Current 1mA to 150mA

• Extended Temperature Range 0. °C to 105.°C

• Low Temperature Coefficient 30 ppm /°C

• Offered in TO-92, SOIC, SOT-89, SOT-23-5

• Improved Replacement in Performance for TL431

• Low Cost Solution

11.15.3. Pin Configurations

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11.16. 24C16

11.16.1. Description

The AT24C01A/02/04/08/16 provides 1024/2048/4096/8192/16384 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 128/256/512/ 1024/2048 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and lowvoltage operation are essential. The AT24C01A/02/04/08/16 is available in space-saving 8-pin PDIP, (AT24C01A/02/04/08/16), 8-lead TSSOP (AT24C01A/02/04/08/16) and 8-lead JEDEC SOIC (AT24C01A/ 02/04/08/16) packages and is accessed via a 2-wire serial interface. In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V), 2.5V (2.5V to 5.5V) and 1.8V (1.8V to 5.5V) versions.

11.16.2. Features

• Low-voltage and Standard-voltage Operation – 5.0 (V CC = 4.5V to 5.5V) – 2.7 (V CC = 2.7V to 5.5V) – 2.5 (V CC = 2.5V to 5.5V) – 1.8 (V CC = 1.8V to 5.5V)

• Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K), 1024 x 8 (8K) or 2048 x 8 (16K)

• 2-wire Serial Interface

• Schmitt Trigger, Filtered Inputs for Noise Suppression

• Bi-directional Data Transfer Protocol

• 100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility

• Write Protect Pin for Hardware Data Protection

• 8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes

• Partial Page Writes are Allowed

• Self-timed Write Cycle (10 ms max)

• High-reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years

• Automotive Grade and Extended Temperature Devices Available

• 8-lead JEDEC SOIC, 8-pin PDIP and 8-lead TSSOP Packages

11.16.3. Pin Configuration

Pin Name Function

A0 - A2 Address Inputs SDA Serial Data SCL Serial Clock Input WP Write Protect NC No Connect

11.16.4. Pin Description

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and

negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired for the AT24C01A and the AT24C02. As many as eight 1K/2K devices may be addressed on a single bus system. The AT24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be addressed on a single bus system. The A0 pin is a no connect. The AT24C08 only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed on a single bus system. The A0 and A1 pins are no connects. The AT24C16 does not use the device address pins, which limits the number of devices on a single bus to one. The A0, A1 and A2 pins are no connects. WRITE PROTECT (WP): The AT24C01A/02/04/16 has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protect pin is connected to VCC, the write protection feature is enabled and operates as shown in the following table.

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11.17. AL875

11.17.1. General Description

The AL875 is a high-speed triple 8-bit monolithic analog-to-digital converter (ADC) designed for digitizing RGB graphics/video signal or other applications. Its 110 MHz conversion rate can support display resolution of up to 1280x1024 at 60Hz refresh rate. The AL875 accepts 0.6~2.0V analog input range without using pre-amplifiers which may reduce the overall S/N ratio. Digitized data is piped at the full clock rate to the 24-bit output port. The AL875 uses 3.3V power with 5V tolerant I/O and low power dissipation. The sampling clock is provided by an external clock source, usually a PLL, which multiplies the frequency of the input reference clock (usually a HSYNC signal) to generate the sampling clock. The AL875 provides a programmable PLL divider up to 4096. In addition, the input active horizontal and vertical starting and ending positions can be detected to ensure that the whole picture fits into the displayable region of the screen. Through an I2C interface, the AL875 is fully programmable to support various graphic resolutions.

11.17.2. General Features

• High speed 8-bit ADC up to 110MHz conversion rate

• Support display resolution up to 1280x1024 at 60Hz refresh rate

• Low power dissipation (0.9W typical at 3.3V, 110MHz)

• 0.6~2.0V p-p analog input range

• 10k~1MHz CKREF locking range

• Full programmability via I2C interface

• Automatic screen position support

• Programmable clock phase adjustment

• TTL compatible digital inputs and outputs

• High impedance tri-state output

• Power-down mode

• Single 3.3 volt power with 5 volt tolerant I/O

• 100-pin 14x20 mm PQFP package

11.17.3. Pin Definition and Description

AL875 Type Pin# Description

TESTIN3 IN (CMOS) 1 Test signal input 3, can be left open. TESTIN2 IN (CMOS) 2 Test signal input 2, can be left open. TESTIN1 IN (CMOS) 3 Test signal input 1, can be left open. TESTIN0 IN (CMOS) 4 Test signal input 0, can be left open. VDD POWER 5 Digital power supply VRBR IN 6 Red channel bottom voltage reference VNR IN 7 Red channel comparator voltage reference VRTR IN 8 Red channel top voltage reference NC -- 9 Not connected NC -- 10 Not connected VDDAR POWER 11 Red channel analog power supply RIN IN 12 Red channel analog input GNDAR GROUND 13 Red channel analog ground VRBG IN 14 Green channel bottom voltage reference VNG IN 15 Green channel comparator voltage reference VRTG IN 16 Green channel top voltage reference NC -- 17 Not connected NC -- 18 Not connected VDDAG POWER 19 Green channel analog power supply GIN IN 20 Green channel analog input GNDAG GROUND 21 Green channel analog ground VRBB IN 22 Blue channel bottom voltage reference VNB IN 23 Blue channel comparator voltage reference VRTB IN 24 Blue channel top voltage reference NC -- 25 Not connected NC -- 26 Not connected VDDAB POWER 27 Blue channel analog power supply BIN IN 28 Blue channel analog input GNDAB GROUND 29 Blue channel analog ground ADTEST3 IN (CMOSu) 30 Internal ADC test pin 3, to be pulled up. CKINTEN IN (CMOSd) 31 Test pin, pulled down for normal operation.

15” TFT TV Service Manual 24/10/2003

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