VESTEL 11 MB 33 Service Manual
11 AK-33
Service Manual
1. INTRODUCTION ________________________________________________4
2. SMALL SIGNAL PART WITH TDA8885 _____________________________4
2.1. Vision IF amplifier _________________________________________________ 4
2.2. Video Switches_____________________________________________________ 5
2.3. Sound Circuit______________________________________________________ 5
2.4. Synchronisation circuit______________________________________________5
2.5. Chroma and Luminance processing ___________________________________ 6
2.6. Colour Decoder ____________________________________________________ 6
2.7. PICTURE IMPROVEMENT FEATURES______________________________ 7
2.8. RGB output circuit and black-current stabilisation_______________________ 7
2.9. EAST – WEST OUTPUT STAGE_____________________________________ 8
3. TUNER_________________________________________________________8
4. VIDEO SWITCH TEA6415C _______________________________________9
5. MULTI STANDARD SOUND PROCESSOR___________________________9
6. SOUND OUTPUT STAGE WITH TDA 7265___________________________9
7. VERTICAL OUTPUT STAGE WITH STV 9379 _______________________10
8. VIDEO OUTPUT AMPLIFIER TDA6108____________________________10
9. COMBFILTER TDA 9181_________________________________________10
10. POWER SUPPLY (SMPS) _______________________________________10
11. POWER FACTOR CORRECTION ________________________________10
12. MICROCONTROLLER SDA555X ________________________________10
12.1. General Features ________________________________________________ 10
12.2. External Crystal and Programmable clock speed______________________ 10
12.3. Microcontroller Features _________________________________________10
12.4. Memory _______________________________________________________ 11
12.5. Display Features ________________________________________________ 11
12.6. ROM Characters ________________________________________________ 11
12.7. Acquisition Features _____________________________________________ 11
12.8. Ports __________________________________________________________ 11
13. SERIAL ACCESS CMOS 8K (1024*8) EEPROM ST24C08 ____________12
14. CLASS AB STEREO HEADPHONE DRIVER TDA1308 ______________12
15. SAW FILTERS________________________________________________12
16. IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM____________12
16.1. TDA8885:______________________________________________________ 12
16.1.1. GENERAL DESCRIPTION _____________________________________________12
16.1.2. FEATURES__________________________________________________________12
16.1.3. Pin Description _______________________________________________________13
16.2. UV1315, UV1316 ________________________________________________ 15
16.2.1. General description of UV1315: __________________________________________15
16.2.2. Features of UV1315:___________________________________________________15
16.2.3. General description of UV1316: __________________________________________15
16.2.4. Features of UV1316:___________________________________________________15
16.3. TEA6415C:_____________________________________________________ 16
16.3.1. General Description: ___________________________________________________16
16.3.2. Features: ____________________________________________________________16
16.4. TDA7265:______________________________________________________ 17
16.4.1. Features: ____________________________________________________________17
16.4.2. Pinning:_____________________________________________________________17
16.5. TDA6108Q: ____________________________________________________ 17
16.5.1. Features: ____________________________________________________________17
16.6. 74 HCT 32 _____________________________________________________ 18
16.6.1. PINNING ___________________________________________________________18
16.7. MC44608 ______________________________________________________ 18
16.7.1. General description:____________________________________________________18
16.7.2. General Features ______________________________________________________18
16.8. SDA5555: ______________________________________________________ 19
16.8.1. General description:____________________________________________________19
16.9. TDA9181:______________________________________________________ 20
16.9.1. General Features:______________________________________________________20
16.9.2. Limits:______________________________________________________________20
16.10. TCD1102:______________________________________________________ 21
16.10.1. Description ________________________________________________________21
16.10.2. Applications _______________________________________________________21
16.10.3. General features: ____________________________________________________21
16.11. ST24C08: ______________________________________________________ 21
16.11.1. General description:__________________________________________________21
16.11.2. Features: __________________________________________________________21
16.12. TDA1308:______________________________________________________ 22
16.12.1. Features: __________________________________________________________22
16.13. PCF8583: ______________________________________________________ 22
16.13.1. FEATURES________________________________________________________22
16.13.2. GENERAL DESCRIPTION ___________________________________________23
16.14. MC33260:______________________________________________________ 23
16.14.1. General Features:____________________________________________________23
16.14.2. Safety Features:_____________________________________________________23
16.14.3. LIMITS:___________________________________________________________23
16.14.4. PINNING _________________________________________________________23
16.15. STV9379: ______________________________________________________ 24
16.15.1. DESCRIPTION_____________________________________________________24
16.15.2. PINNING _________________________________________________________24
16.16. MSP34XX :_____________________________________________________24
MSP3410D ________________________________________________________24
16.17. LM358N: ______________________________________________________ 26
16.17.1. General Description__________________________________________________26
16.17.2. Unique Characteristics________________________________________________26
16.17.3. Advantages ________________________________________________________26
16.17.4. Features___________________________________________________________26
17. AK33 CHASSIS MANUAL ADJUSTMENTS PROCEDURE ___________26
1. INTRODUCTION
11AK33 is a 110ø chassis capable of driving 28-29”,32”,33” tubes at appropriate currents The chassis is a
Frequency Controlled Tuning (PLL) and control system for multi-standard TV receivers with onscreen-display (OSD) for all relevant control functions. The system is based on the ‘one-chip’ I2C bus
controlled video processing / deflection IC TDA8885 which also controls sound.
German stereo and Nicam is detected and processed by the MSP 3410 G. Dolby sound is processed by
MSP 3452 G, virtual dolby by MSP 3411G, BTSC Stereo by MSP 3430G IC’s by option. All sound
processors also control the sound volume, balance, tone and spatial stereo effect.
The user-interface is menu based control system with cursor keys. Only for some functions the colour
keys are needed: This means that some of the functions can also be operated from the local keyboard
(i.e. Vol -, Vol +, P -, P+ and M).
Teletext is done by the microcontroller on-chip teletext module.
2. SMALL SIGNAL PART WITH TDA8885
The TDA8885 combine all small signal functions required for a colour TV receiver.
2.1. Vision IF amplifier
The IF-amplifier contains 3 ac-coupled control stages with a total gain control range, which is higher
then 66 dB. The sensitivity of the circuit is comparable. The video signal is demodulated by means of
an alignment-free PLL carrier regenerator with an internal VCO. This VCO is calibrated by means of a
digital control circuit, which uses the clock frequency of the m-Controller/Teletext decoder as a
reference. The frequency setting for the various standards (33.4, 33.9, 38, 38.9, 45.75 and 58.75 MHz)
is realised via the I 2 C-bus. To get a good performance for phase modulated carrier signals the control
speed of the PLL can be increased by means of the FFI bit. The AFC output is generated by the digital
control circuit of the IF-PLL demodulator and can be read via the I 2 C bus. For fast search tuning
systems the window of the AFC can be increased with a factor 3. The setting is realised with the AFW
bit. The AGC-detector operates on top sync and top white-level. The demodulation polarity is switched
via the I 2 C-bus. The AGC detector capacitor is integrated. The time-constant can be chosen via the I 2
C-bus. The time-constant of the AGC system during positive modulation is rather long to avoid visible
variations of the signal amplitude. To improve the speed of the AGC system a circuit has been included
which detects whether the AGC detector is activated every frame period. When during 3 field periods
no action is detected the speed of the system is increased. For signals without peak white information
the system switches automatically to a gated black level AGC. Because a black level clamp pulse is
required for this way of operation the circuit will only switch to black level AGC in the internal mode.
The circuit contains a video identification circuit, which is independent of the synchronisation circuit.
Therefore search tuning is possible when the display section of the receiver is used as a monitor.
However, this Ident circuit cannot be made as sensitive as the slower sync Ident circuit (SL) and we use
both Ident outputs to obtain a reliable search system. The Ident output is supplied to the tuning system
via the I 2 C-bus. The input of the identification circuit is connected to pin 24, the internal CVBS input.
This has the advantage that the Ident circuit can also be made operative when a scrambled signal is
received (descrambler connected between the IF video output (pin 16) and pin 24). A second advantage
is that the Ident circuit can be used when the IF amplifier is not used The video Ident circuit can also be
used to identify the selected CBVS or Y/C signal. The switching between the 2 modes can be realised
with the VIM bit. The IC contains a group delay correction circuit, which can be switched between the
BG and a flat group delay response characteristic. This has the advantage that in multi-standard
receivers no compromise has to be made for the choice of the SAW filter. Also the sound trap is
integrated within the IC .The centre frequency of the trap can be switched via the I 2 C-bus. For monoFM versions it is possible to obtain a demodulated IF video signal which has not passed the sound trap
so that an external stereo decoder can be driven. This function is selected by means of the ICO bit (subaddress 28H). The signal is available on pin 27 (audio output pin when ICO = 0). The S/N ratio of the
selected video signal can be read via the bits SN1/SN0 in sub-address 03H.
2.2. Video Switches
The circuit has an input for the internal CVBS signal and 2 inputs for external CVBS or Y signals. The
circuit has only 1 chroma input so that it is not possible to apply 2 separate Y/C inputs. The switch
configuration is given in Fig. A. The selection of the various sources is made via the I 2 C-bus. The
QFP-64 version has 2 independently switchable outputs. The CVBS1O output is identical to the
selected signal that is supplied to the internal video processing circuit and can therefore be used as
source signal for a teletext decoder. Both CVBS outputs have an amplitude of 2.0 VP-P . The CVBS2O
output can for instance be used as drive signal for a PIP decoder. If the Y/C-3 signal is selected for one
of the outputs the luminance and chrominance signals are added so that a CVBS signal is obtained
again.
2.3. Sound Circuit
The sound IF amplifier is similar to the vision IF amplifier and has a gain control range of about 66 dB.
The AGC circuit is related to the SIF carrier levels (average level of AM or FM carriers) and ensures a
constant signal amplitude of the AM demodulator and the QSS mixer. A multiplier realises the single
reference QSS mixer. In this multiplier the SIF signal is converted to the intercarrier frequency by
mixing it with the regenerated picture carrier from the VCO. The mixer output signal is supplied to the
output via a high-pass filter for attenuation of the residual video signals. With this system a high
performance hi-fi stereo sound processing can be achieved. To optimise the performance of the
demodulator the offset can be compensated by means of an I 2 C-bus setting. The AM sound
demodulator is realised by a multiplier. The modulated sound IF signal is multiplied in phase with the
limited SIF signal. The demodulator output signal is supplied to the output via a low-pass filter for
attenuation of the carrier harmonics. The AM signal is supplied to the output (pin 27) via the volume
control. It is possible to get the AM output signal (not controlled on amplitude) on the QSS intercarrier
output. The selection is made by means of the AM bit in sub-address 29H. Another possibility is that
pin 11 can be used as external audio input pin and pin 49 can be used as (non-controlled) AM output
pin. This can be realised by means of the setting the control bits CMB0 and CMB1 in sub-address 22H.
2.4. Synchronisation circuit
The sync separator is preceded by a controlled amplifier, which adjusts the sync pulse amplitude to a
fixed level. These pulses are fed to the slicing stage, which is operating at 50% of the amplitude. The
separated sync pulses are fed to the first phase detector and to the coincidence detector. This
coincidence detector is used to detect whether the line oscillator is synchronised with the incoming
signal and can also be used for transmitter identification. This circuit can be made less sensitive by
means of the STM bit. This mode can be used during search tuning to avoid that the tuning system will
stop at very weak input signals. The first PLL has a very high statically steepness so that the phase of
the picture is independent of the line frequency. The horizontal drive signal is generated by an internal
VCO, which is running at a frequency of 25 MHz. This oscillator is stabilised to that frequency by
using the 12 MHz frequency of the crystal oscillator as a reference. The time-constant of the first loop
can be forced by the I 2 C-bus (fast or slow). If required the IC can select the time-constant depending
on the noise content of the incoming video signal. The horizontal output signal is generated by means
of a second loop, which compares the phase of the internal oscillator signal with the phase of the
incoming flyback pulse. The time-constant of this loop is connected externally and can be used as input
for a dynamic horizontal phase correction. To obtain a smooth switch-on and switch-off behaviour of
the horizontal output stage the horizontal drive signal is switched-on and off via the soft-start/soft-stop
procedure. This function is realised by means of a variation of the TON of the horizontal drive pulse.
When the soft-start procedure is completed the horizontal output is gated with the flyback pulse so that
the horizontal output transistor cannot be switched-on during the flyback time. An additional function
of the IC is the ‘low-power start-up’ feature. For this function a supply voltage with a value between 3
and 5 V must be available at the start-up pin (required current 5 mA typical). When all sub-address
bytes have been sent and the POR and XPR flags have been cleared, the horizontal output can be
switched-on via the STB-bit (sub-address 24H). In this condition the horizontal drive signal has the
nominal TOFF and the TON grows gradually from zero to the nominal value as indicated in the softstart behaviour. As soon as the 8 V supply is present the switch-on procedure (e.g. closing of the
second loop) is continued. The presence of the 8 V supply voltage is indicated by the SUP bit in the I 2
C-bus output byte 02. The circuit generates a vertical sync pulse. This pulse can be selected on pin 49
via the bits CMB1 and CMB0. In the 100 Hz input processor versions the vertical sync pulse is
available on pin 63 and the horizontal pulse on pin 56. Via the I C-bus adjustments can be made of the
horizontal and vertical geometry. The vertical sawtooth generator drives the vertical output drive
circuit, which has a differential output current. For the E-W drive a single ended current output is
available. A special feature is the zoom function for both the horizontal and vertical deflection and the
vertical scroll function. When the horizontal scan is reduced to display 4 : 3 pictures on a 16 : 9 picture
tube an accurate video blanking can be switched on to obtain well-defined edges on the screen.
Overvoltage conditions (X-ray protection) can be detected via the EHT tracking pin. When an
overvoltage condition is detected the horizontal output drive signal will be switched-off via the slow
stop procedure but it is also possible that the drive is not switched-off and that just a protection
indication is given in the I 2 C-bus output bytes. The choice is made via the input bit PRD. When PRD
= 1 and an overvoltage is detected the drive is switched-off and the STB bit is set to 0. Switching on of
the drive is only possible when the XPR flag is cleared. The IC has a second protection input on the j2
filter capacitor pin. When this input is activated the drive signal is switched-off immediately and
switched-on again via the slow start procedure. For this reason this protection input can be used as
‘flash protection’. The drive pulses for the vertical sawtooth generator is obtained from a vertical
countdown circuit. This countdown circuit has various windows depending on the incoming signal (50
Hz or 60 Hz and standard or non-standard). The countdown circuit can be forced in various modes by
means of the I 2 C-bus. During the insertion of RGB signals the maximum vertical frequency is
increased to 72 Hz so that the circuit can also synchronise on signals with a higher vertical frequency
like VGA. To obtain short switching times of the countdown circuit during a channel change the
divider can be forced in the search window by means of the NCIN bit. The vertical deflection can be
set in the de-interlace mode via the I 2 C bus.
2.5. Chroma and Luminance processing
The circuit contains a chroma bandpass and trap circuit. The filters are realised by means of gyrator
circuits and they are automatically calibrated by comparing the tuning frequency with the reference
frequency of the decoder. The luminance delay line and the delay for the peaking circuit are also
realised by means of gyrator circuits. The centre frequency of the chroma bandpass filter is switchable
via the I 2 C-bus so that the performance can be optimised for ‘front-end’ signals and external CVBS
signals. During SECAM reception the centre frequency of the chroma trap is reduced to get a better
suppression of the SECAM carrier frequencies.
2.6. Colour Decoder
The colour decoder can decode PAL, NTSC and SECAM signals. The internal clock signals for the
various colour standards are generated by means of an internal VCO, which uses the 12 MHz crystal
frequency as a reference. Under bad-signal conditions (e.g. VCR-playback in feature mode), it may
occur that the colour killer is activated although the colour PLL is still in lock. When this killing action
is not wanted it is possible to overrule the colour killer by forcing the colour decoder to the required
standard and to activate the FCO-bit (Forced Colour On) in subaddress 21H. The IC contains an
Loading...