VESTEL 11AK46 DVD, 11AK46, AK46 CONTENTS

CONTENTS

1. CHANGE HISTORY .................................................................................................................... 4

2. GENERAL DESCRIPTION .......................................................................................................... 4

2.1 STI5508 ...................................................................................................................................... 4

2.2 M2 .............................................................................................................................................. 5

2.3 DRIVE INTERFACES .................................................................................................................. 5

2.4 FRONT PANEL ........................................................................................................................... 5

2.5 REAR PANEL ............................................................................................................................. 6

3. GPIO, IRQ, AND CHIP SELECT ASSIGNMENTS ........................................................................ 6

4. JUMPER CONFIGURATION ........................................................................................................ 7

5. AUDIO OUTPUT .......................................................................................................................... 8

5.1 AUDIO DACS .............................................................................................................................. 8

5.2 AUDIO MUTE.............................................................................................................................. 8

6 VIDEO INTERFACE .................................................................................................................... 8

6.1 SCART INTERFACE ................................................................................................................... 9

6.2 DIGITAL VIDEO INTERFACE....................................................................................................... 9

7. MPEG DECODER SDRAM MEMORY ........................................................................................ 9

8. PROCESSOR SDRAM MEMORY .............................................................................................. 9

9. FLASH MEMORY ....................................................................................................................... 10

10. SERIAL EEPROM MEMORY ..................................................................................................... 10

11. TMM DRIVE INTERFACE ............................................................................................................ 10

11.1 CONNECTION INFORMATION .................................................................................................... 10

11.2 TMM DRIVE TRAY MOTOR CONTROL AND PUSH AND STALL SENSE CIRCUITRY................. 11

12. ATAPI DRIVE INTERFACE AND EPLD ........................................................................................ 11

13. AUDIO SAMPLING RATE AND EXTERNAL PLL COMPONENT CONFIGURATION ..................... 11

14. UART SERIAL PORT .................................................................................................................. 11

15. FRONT PANEL ........................................................................................................................... 12

15.1 FRONT PANEL MICRO ............................................................................................................... 12

15.2 VFD CONTROLLER .................................................................................................................... 12

15.3 MICROPHONE INPUTS .............................................................................................................. 12

15.4 HEADPHONE OUTPUTS ............................................................................................................ 12

16. MISCELLANEOUS FUNCTIONS ................................................................................................. 12

16.1 POWER DOWN .......................................................................................................................... 12

16.2 RESET CIRCUITRY .................................................................................................................... 13

16.3 VOLTAGE REGULATORS ........................................................................................................... 13

17. CONNECTORS ........................................................................................................................... 13

17.1 ATAPI DRIVE STANDARD CONNECTOR .................................................................................... 13

17.2 TMM DRIVE CONNECTORS....................................................................................................... 14

17.3 STI5508 JTAG INTERFACE ......................................................................................................... 15

17.4 RS232 SERIAL PORT ................................................................................................................. 16

17.5 DIGITAL YUV OUTPUT HEADER ................................................................................................ 16

17.6 ANALOG VIDEO INPUT HEADER .............................................................................................. 16

17.7 SCART CONNECTORS .............................................................................................................. 16

17.8 POWER CONNECTOR ............................................................................................................... 17

18. SCHEMATICS ............................................................................................................................. 17

19. BILL OF MATERIALS .................................................................................................................. 17

20. BOARD LAYOUT ........................................................................................................................ 17

20.1 TOP SIDE ASSEMBLY DRAWING ............................................................................................. 17

20.2 BOTTOM SIDE ASSEMBLY DRAWING ...................................................................................... 17

1 CHANGE HISTORY

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1. CHANGE HISTORY

Revision Date Author Comments

Rev 1.0 7/23/2000 Jim Loughin Initial Release
Rev 1.1 8/23/2000 Jim Loughin Updated to match final design

2. GENERAL DESCRIPTION

Major functional blocks are discussed briefly in this section. A more detailed description is contained later in the document.

2.1 STI5508

The STi5508 provides a highly integrated back-end solution for DVD applications. A host CPU handles both the general
application (the user interface, and the DVD, CD-DA, VCD, SVCD navigation) and the drivers of the different embedded
peripheral (audio/video, karaoke, sub-picture decoders, OSD, PAL/NTSC encoder...). Because of its memory savings,
increased number of internal peripherals, improved development platform and reference design, theSTi5508 offers a cost­effective solution to DVD applications, with rapid time-to-market. These functions include:

Integrated 32-bit host CPU @ 60MHz

- 2 Kbytes of instruction cache, 2 Kbytes of data cache, and 4Kbytes of SRAM configurable as data cache.

Audio decoder

- 5.1 channel Dolby Digital® /MPEG-2 multi-channel decoding, 3 X 2-channel PCM outputs

- IEC60958  IEC61937 digital output

- DTS® digital out 5.1 channel

- SRS®/TruSurround®

- MP3 decoding

Karaoke processor

- Echo, pitch shift, microphone inputs, voice cancellation and multiple other effects

Video decoder

- Supports MPEG-2 MP@ML

- Fully programmable zoom-in and zoom-out

- PAL to NTSC and NTSC to PAL conversion

DVD and SVCD subpicture decoder
High performance on-screen display

- to 8 bits per pixel OSD options

- Anti-flicker, anti-flutter and anti-aliasing filters

PAL/NTSC/SECAM encoder

- RGB, CVBS, Y/C and YUV outputs with 10-bit DACs

- Macrovision® 7.01/6.1 compatible

Shared SDRAM memory interface

- Supports one or two 16Mbit, or one 64Mbit 125 MHZ SDRAMs

Programmable CPU memory interface for SDRAM, ROM, peripherals...
Front-end interface

- DVD, VCD, SVCD and CD-DA compatible

- Serial, parallel and ATAPI interfaces

- Hardware sector filtering

- Integrated CSS decryption and track buffer

Integrated peripherals

- UARTS, 2 SmartCards, I2C controller, 3 PWM outputs, 3 capture timers

- Modem support

- 38 bits of programmable I/O

Please refer to the STi5508 Data Sheets: STi5508 DVD HOST PROCESSOR WITH ENHANCED
AUDIO FEATURES and STi5508 REGISTER MANUAL for more detailed information.

2.2 MEMORY

The STi5508 includes all of the interface signals to connect to industry standard SDRAM, DRAM, ROM, and I2C memory
devices. The system includes one or two SDRAM components. The MPEG decoder unit interfaces to a single 4M x 16bit
SDRAM over the SMI bus. The general purpose processor can share the decoder SDRAM or can access an optional
SDRAM installed on the EMI bus. This EMI SDRAM can be either a 1Mx16 or 4Mx16 chip. The optional EMI SDRAM can
be installed if the system requires higher performance of requires more RAM than is standard system (due to complex trick
modes, advanced GUI, etc). The standard production Ravisent CineMasterCE software will execute without EMI SDRAM
installed, however EMI SDRAM is required to perform debugging and prototyping. A single 1Mx16 FLASH ROM device is
support on the EMI bus. There is also a small I²C serial EEPROM (from 1Kbit to 256Kbit) for storage of user player settings,
software configuration information, title specific information, or other purposes.

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2.3 DRIVE INTERFACES

The system supports either a standard ATAPI drive interface or the SGS Thomson TVM502 drive (simply called TMM).
The TMM drive is supplied with either a three connector interface or a single FFC cable connection. The design supports
either connection method. The TMM three connector interface utilizes separate connectors for power, data, and drive tray
motor control. Circuitry to control the TMM drive tray is located on the decoder board when this TMM drive version is
used. The interface to the ATAPI drive is included within the STi5508. The ATAPI data bus is buffered so that the ATAPI
cable does not interfere with signal quality. An ATAPI drive is connected via the standard 34 pin dual row PC style IDE
header. An IDE power connector is also supported for convenience.

2.4 FRONT PANEL

The front panel is included in the reference design and is based around an inexpensive Futaba VFD and a common NEC
front panel controller chip, (uPD16311). The STi5508 controls the uPD16311 using several control signals, (clock, data,
chip select). The infra-red remote control signal is passed directly to the STi5508 for decoding.
A more advanced front panel is possible with the addition of a front panel microcontroller. A Microchip PIC can be used to
control the 16311, receive the infra-red remote control decoding, and system power down. Communication between the
STi5508 and the front panel PIC is accomplished over an I²C interface.

The front panel connector also supports two microphone inputs and a stereo headphone output.

2.5 REAR PANEL

A typical rear panel is included in the reference design. This rear panel supports:

- Six channel and two channel simultaneous audio outputs

- Optical and coax S/PDIF outputs are supported

- Composite, S-Video, and RBG/YUV outputs

- Dual SCART provides SCART passthrough when DVD output is not supplied

- External video DENC Connections

The six video signals used to provide CVBS, S-Video, and RGB/YUV are generated by the STi5508s internal video DAC.
The video signals are be buffered by external circuitry. The STi5508 can generate either RGB or YUV outputs on three of
the pins by configuring internal STi5508 registers.

Six channel audio output by the STi5508 in the form of three I²S (or similar) data streams. An addition, an I²S stream is
generated by the STi5508 to support simultaneous two-channel output. The S/PDIF serial stream is also generated by
the STi5508 output by the rear panel. A six-channel audio DAC, a stereo DAC, or both can be installed.

3 GPIO, IRQ, AND CHIP SELECT ASSIGNMENTS

PIO Port Bit Pin # STi5508 Alternate Function CineMaster CE Function

Port 0 Bit 0 186 SC0_DATA #SOFT_RESET
Port 0 Bit 1 187 #ATAPI_RD #ATAPI_RD
Port 0 Bit 2 188 #ATAPI_WR #ATAPI_WR
Port 0 Bit 3 189 SC0_CLK DAC_CCLK (Audio DAC control)
Port 0 Bit 4 190 SC0_RST DAC_CCLK (Audio DAC control)
Port 0 Bit 5 191 SC0_CMD_VCC #DAC_CS0 (Audio DAC control)
Port 0 Bit 6 192 SC0_DATA_DIR #DAC_CS1 (Audio DAC control)
Port 0 Bit 7 193 SC0_DETECT Unused (Test Point 39)
Port 1 Bit 0 194 SSC0_DATA SDA (I2C)
Port 1 Bit 1 195 SSC0_CLK SCL (I2C)
Port 1 Bit 2 196 PARA_DVALID/SC_EXT_CLK Unused (Test Point 35)
Port 1 Bit 3 197 TXD2 TXD (Serial Port)
Port 1 Bit 4 200 RXD2 RXD (Serial Port)
Port 1 Bit 5 201 PARA_SYNC/TXD1 SR0 (for PLL1700)
Port 1 Bit 6 202 TRIGIN TRIGIN (JTAG)
Port 1 Bit 7 203 TRIGOUT TRIGOUT (JTAG)
Port 2 Bit 0 204 SC1_DATA FPCLK (Front Panel)
Port 2 Bit 1 205 PARA_REQ/RXD1 FS0 (for PLL1700)
Port 2 Bit 2 206 PARA_STR FS1 (for PLL1700)
Port 2 Bit 3 207 SC1_CLK RTS (Serial Port)
Port 2 Bit 4 208 SC1_RST CTS (Serial Port)
Port 2 Bit 5 1 SC1_CMD_VCC FPDATA (Front Panel)
Port 2 Bit 6 2 DAC_DATA/SC1_DATA_DIR DAC_DATA (Stereo Audýo)

Port 2 Bit 7 3 SC1_DETECT FPSTRB (Front Panel)

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