VersaLogic Viper, VL-EBX-38 Programmer's Reference Manual

REV. November 2017

Viper

Programmer’s
Reference
Manual

(VL-EBX-38)

Intel® Atom™-based Single
Board Computer with Dual
Ethernet, Video, USB, SATA,
Serial I/O, Digital I/ O, Analog
I/O, Trusted Platform Module
security, Counter/Timers, Mini
PCIe, mSATA, PC/104-Plus
Interface, and SPX.

WWW.VERSALOGIC.COM

12100 SW Tualatin Road
Tualatin, OR 97062-7341

[phone]

Fax [phone]

Copyright © 2017 VersaLogic Corp. All rights r eser ved.

Notice:

Although every effort has been made to ensure this document is error-free, VersaLogic makes no
representations or warranties with respect to this product and specifically disclaims any implied warranties
of merchantability or fitness for any particular purpose.

VersaLogic reserves the right to revise this product and associated documentation at any time without
obligation to notify anyone of such changes.

PC/104, PC/104-Plus, and the PC/104 logo are trademarks of the PC/104 Consortium.
* Other names and brands may be claimed as the property of others.
© Copyright 2017 VersaLogic Corporation

ii VL-EBX-38 Programmer’s Reference Manual

Product Release Notes

Release 1.06

Updated AUX_PSEN and GPIO3 register information

Release 1.05

Updated register information

Release 1.00

Initial Release

Support

The EBX-38 support page contains additional information and resources for this product
including:

 Reference Manual (PDF format)
 Operating system information and software drivers
 Data sheets and manufacturers’ links for chips used in this product
 BIOS information and upgrades
 Utility routines and benchmark software

This is a private page for EBX-38 users that can be accessed only be entering this address
directly. It cannot be reached from the VersaLogic homepage.

The VersaTech KnowledgeBase is an invaluable resource for resolving technical issues with
your VersaLogic product.

VersaTech KnowledgeBase

VL-EBX-38 Programmer’s Reference Manual iii

Contents

Introduction ................................................................................................................... 1

Related Documents ............................................................................................................. 1

System Resources and Maps ....................................................................................... 2

Memory Map ...................................................................................................................... 2

Interrupts ............................................................................................................................. 2

FPGA Registers ............................................................................................................. 4

FPGA I/O Space ................................................................................................................. 4

ISA Bus Addressing and LPC I/O and Memory Map ........................................... 4

FPGA Register Descriptions............................................................................................... 6

Product Information Registers .......................................................................................... 11

BIOS and Jumper Status Register ........................................................................ 12

Timer Registers .................................................................................................... 13

SPI Control Registers .......................................................................................... 16

SPI Data Registers ............................................................................................... 18

SPI Debug Control Register and mSATA/PCIe Select Control Register ............ 19

ADM – A/D and D/A SPI Device Control Register ............................................ 20

Miscellaneous FPGA Registers ........................................................................... 21

DIOCR – Digital I/O Control Register ................................................................ 25

8254 Timer Address 0/1/2/3 Registers ................................................................ 36

Programming Information f or Hardware Interfaces .................................................. 38

Processor WAKE# Capabilities........................................................................................ 38

Watchdog Timer ............................................................................................................... 38

Industrial I/O Functions and SPI Interface ....................................................................... 39

Programmable LED .......................................................................................................... 39

Tables

Table 1: Memory Map ........................................................................................................ 2

Table 2: I/O Map ................................................................................................................. 3

Table 3: FPGA I/O Map ...................................................................................................... 4

Table 4: ISA Bus I/O Map .................................................................................................. 5

Table 5: ISA Memory Map ................................................................................................. 5

Table 6: PCR – Product Code and LED Register ............................................................. 11

Table 7: PSR – Product Status Register ............................................................................ 11

Table 8: SCR –Status/Control Register ............................................................................ 12

Table 9: TICR – 8254 Timer Interrupt Mask Register ..................................................... 13

Table 10: TISR – 8254 Timer Interrupt Status Register ................................................... 14

Table 11: TCR – 8254 Timer Control Register ................................................................ 15

iv VL-EBX-38 Programmer’s Reference Manual

Contents

Table 12: SPI Interface Control Register .......................................................................... 16

Table 13: SPI Interface Status Register ............................................................................ 17

Table 14: SPI – SPI Debug Control Register .................................................................... 19

Table 15: MISCR1 – Misc. Control Register #1 .............................................................. 21

Table 16: MISCSR2 – Misc. Control Register #2 ............................................................ 22

Table 17: MISCR3 – Misc. Control Register #3 .............................................................. 23

Table 18: DIOIMASK1 – Digital I/O 8-1 Interrupt Mask Register .................................. 24

Table 19: DIOISTAT1 – Digital I/O 8-1 Interrupt Status Register .................................. 24

Table 20: DIOCR – Digital I/O Control Register ............................................................. 25

Table 21: AUXDIR – AUX GPIO Direction Control Register ........................................ 26

Table 22: AUXPOL – AUX GPIO Polarity Control Register .......................................... 26

Table 23: AUXOUT – AUX GPIO Output Control Register ........................................... 26

Table 24: AUXIN – AUX GPIO Input Status Register .................................................... 27

Table 25: AUXICR – AUX GPIO Interrupt Mask Register ............................................. 27

Table 26: AUXISTAT – AUX GPIO Interrupt Status Register ........................................ 27

Table 27: AUXMODE1 – AUX I/O Mode Register ........................................................ 28

Table 28: WDT_CTL – Watchdog Control Register ........................................................ 29

Table 29: WDT_VAL – Watchdog Control Register ....................................................... 30

Table 30: XCVRMODE – COM Transceiver Mode Register .......................................... 30

Table 31: AUXMODE2 - AUX I/O Mode Register #2 .................................................... 31

Table 32: FANCON – Fan Control Register .................................................................... 31

Table 33: FANTACHLS – FANTACH Status Register Least Significant Bits ............... 32

Table 34: FANTACHMS – FANTACH Status Register Most Significant Bits ............... 32

Table 35: TEMPICR – Temperature Interrupt Control Register ...................................... 33

Table 36: TEMPISTAT – Temperature Interrupt Status Register .................................... 34

Table 37: ISACON1 – ISA Control Register #1 ............................................................... 35

Table 38: ISACON2 – ISA Control Register #2 ............................................................... 36

Table 37: UARTxCR – UART Control Registers ............................................................ 37

VL-EBX-38 Programmer’s Reference Manual v

1

This document provides information for users requiring register-level information for developing
applications with the VL-EBX-38.

Related Documents

The following documents available are on the EBX-38 Product Support Web Page:
 EBX-38 Hardware Reference Manual – provides information on the board’s hardware

features including connectors and all interfaces.

This document is available through the software page:

Introduction

 VersaAPI Installation and Reference Guide

reading and controlling on-board devices on certain VersaLogic products.

– describes the shared library of API calls for

1 VL-EBX-38 Programmer’s Reference Manual

00000h – 9FFFFh

Legacy system (DOS) area

A0000h – B7FFFh

ISA memory area (VGA frame buffer is not accessible)

B8000h – BFFFFh

Text mode buffer

C0000h – CFFFFh

Video BIOS area

D0000h – DFFFFh

PCI ROM expansion area

E0000h – FFFFFh

Legacy BIOS (reserved)

2

Memory Map

Table 1: Memory Map

Interrupts

The LPC SERIRQ is used for interrupt interface to the Bay Trail SoC.

System Resources and Maps

Address Range Description

Each of the following devices can have an IRQ interrupt assigned to it and each with an interrupt
enable control for IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, IRQ9, IRQ10, and IRQ11:

 8254 timers (with three interrupt status bits)
 32 SPI based digital I/Os (with one interrupt status bit)
 8 AUX GPIOs (with one interrupt status bit)
 COM 1 UART (with 16550 interrupt status bits) from the SCH3114
 COM 2 UART (with 16550 interrupt status bits) from the SCH3114
 COM 3 UART (with 16550 interrupt status bits) from the SCH3114
 COM 4 UART (with 16550 interrupt status bits) from the SCH3114
 Watchdog timer (one status bit)
 SPX expansion interface (status is determined by the devices on this interface). This uses

selects from four of the “usual” IRQs.

 Thermal event and battery-low interrupts
 ISA interrupts

The ISA bus supports 11 interrupts: IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, IRQ9, IRQ10, IRQ11,
IRQ12, IRQ14, and IRQ15. There is an interrupt enable control for each and by default they are
all disabled. ISA bus interrupts simply pass through to the SERIRQ (no capture in the FPGA).

Common interrupts can be assigned to multiple devices if software can deal with it (this is
common on UARTs being handled by a common ISR).

Interrupt status bits for everything except the UARTs will “stick” and are cleared by a “write­one” to a status register bit. The 16550 UART interrupts behave as defined for the 16550
registers and are a pass-through to the LPC SERIRQ via the SCH3114.

VL-EBX-38 Programmer’s Reference Manual 2

System Resources and Maps

2E8h – 2EFh

COM4 serial port default

2F8h – 2FFh

COM2 serial port default

3B0h – 3DFh

Legacy VGA registers

3E8h – 3EFh

COM3 serial port default

3F8h – 3FFh

COM1 serial port default

400h – 47Fh

ACPI / Power management (reserved)

500h – 5FFh

PCH GPIO (reserved)

C80h – CBBh

EBX-38 FPGA Board Control Registers

CBCh – CBFh

EBX-38 FPGA 8254 Timer Registers

CC0h – CCFh

EBX-38 FPGA Additional Registers

Per the VersaAPI standard, anytime an interrupt on the SERIRQ is enabled, the slot becomes
active. All interrupts in the SERIRQ are high-true so when the slot becomes active, the slot will
be low when there is no interrupt and high when there is an interrupt.

Table 2: I/O Map

I/O Address Range Device/Owner

3 VL-EBX-38 Programmer’s Reference Manual

0xC80 – 0xCBB

FPGA registers

60 bytes

0xCBC – 0xCBF

8254 timer address registers

4 bytes

0xCC0 – 0xCCF

Additional Registers (for

SCH3114 UART support)

16 Bytes

3

FPGA I/O Space

The FPGA will be mapped into I/O space on the LPC bus. The only other devices on the LPC
bus are the SCH3114 Super I/O and the TPM, but the TPM is a Memory mapped device which is
not allowed to use I/O space anymore (see the main TPM section).

 FPGA Access: LPC I/O Space
 FPGA Access Size: All 8-bit Byte accesses (16-bit like registers are aligned on 16-bit word

boundaries to make word access possible in software but the LPC bus still splits the accesses
into two 8-bit accesses)

 FPGA Address Range: 0xC80 to 0xCCF (80 byte window)
The three 8254 timers only require 4 bytes of addressing and will be put at the end of the first 64-

byte I/O block (staying consistent with other Bay Trail boards). The only requirement is that the
base address must be aligned on a 4-byte block. Some previous FPGAs had the timer base
address programmable but there is no need for that.

FPGA Registers

FPGA Registers

Table 3: FPGA I/O Map

Address Range Device Size

ISA BUS ADDRESSING AND LPC I/O AND MEMORY MAP

The FPGA implements an LPC-to-ISA bridge. The LPC bus only has the FPGA, the SCH3114,
and the TPM device on it. The TPM is a memory mapped device at base address 0xFED40000.
The SCH3114 uses I/O addresses 0x2E/0x2F for its index/data port. It also uses I/O space
0xC00-0xC7F for Runtime Registers. The FPGA uses I/O space 0xC80-0xCCF. The ISA bus
addressing can go up to 16Mbytes (24-bits of address). As such, the following will be the
allowed memory and I/O map for the ISA bus. Basically, all LPC I/O cycles that are unclaimed
by the FPGA will pass through to the ISA bus.

All LPC memory cycles below 16Mbytes will be passed through to the ISA bus. Note that the
actual cycles on the LPC bus are not known.

VL-EBX-38 Programmer’s Reference Manual 4

FPGA Registers

0x2E-0x2F

SCH3114

Index/Data Port

0xC00-0xC7F

SCH3114

Runtime Registers

0xC80-0xCCF

FPGA Registers

80 Bytes

Depends on SoC LPC I/O traffic and

whether COM ports are enabled.

0x0 – 0xFFFFFF LPC memory cycles

ISA bus

Depends on SoC LPC memory traffic

0x1000000 and higher LPC memory

cycles

TPM is the only memory device on the

LPC bus

Table 4: ISA Bus I/O Map

Table 5: ISA Memory Map

Address Range Device Size

All Other LPC I/O Cycles ISA Bus

Address Range Device Size

Ignored by FPGA

5 VL-EBX-38 Programmer’s Reference Manual

FPGA Registers

Register Access Key

WO

Write-Only

ROC

Read-Only and clear-to-0 after reading

If AUX_PSEN is a '0' in MISCSR1 (default setting) then thi s is the same as t he Platform reset. If AUX_PSEN is a

programmed to a '1' then it is the same as t he power-on reset POR.

FPGA Register Descriptions

R/W Read/Write

RO Read-only (status or reserved)

R/WC Read-status/Write-1-to-Clear

RSVD Reserved. Only write 0 to this bit; ignore all read values.

POR Power-on reset (only resets one tim e when input power comes on)

Platform Resets prior to the process or entering the S0 power state (i.e., at power-on and in sleep states)

resetSX

n/a Reset doesn't apply to status or reserved registers

Reset Key

6 VL-EBX-38 Programmer’s Reference Manual

FPGA Registers

VL-EBX-38 Programmer’s Reference Manual 7

Identifier

I/O

Address

Offset

Reset

D7

D6

D5

D4

D3

D2

D1

D0

PCR

C80

0

Platform

PLED

PRODUCT_CODE

PSR

C81

1

n/a

REV_LEVEL

EXTEMP

CUSTOM

BETA

SCR

C82

2

Platform

BIOS_JMP

BIOS_OR

BIOS_SEL

LED_DEBUG

WORKVER

0

GPI_JMP 0 TIMR

C83

3

Platform

IRQEN

IRQSEL2

IRQSEL1

IRQSEL0

0

IMASK_TC5

IMASK_TC4

IMASK_TC3

TISR

C84

4

Platform

INTRTEST

TMRTEST

TMRIN4

TMRIN3

0

ISTAT_TC5

ISTAT_TC4

ISTAT_TC3

TCR

C85

5

Platform

TIM5GATE

TIM4GATE

TIM3GATE

TM45MODE

TM4CLKSEL

TM3CLKSEL

TMROCTST

TMRFULL

Reserved

C86

6

n/a 0 0 0 0 0 0 0 0

Reserved

C87

7

n/a 0 0 0 0 0 0 0 0

SPICONTROL

C88

8

Platform

CPOL

CPHA

SPILEN1

SPILEN0

MAN_SS

SS2

SS1

SS0

SPISTATUS

C89

9

Platform

IRQSEL1

IRQSEL0

SPICLK1

SPICLK0

HW_IRQ_EN

LSBIT_1ST

HW_INT

BUSY

SPIDATA0

C8A

A

Platform

msb

<============>

lsb

SPIDATA1

C8B

B

Platform

msb

<============>

lsb

SPIDATA2

C8C

C

Platform

msb

<============>

lsb

SPIDATA3

C8D

D

Platform

msb

<============>

lsb

SPIMISC

C8E

E

Platform 0 MUXSEL2

MUXSEL1

MUXSEL0

0

SERIRQEN

SPILB 0 ADM

C8F

F

Platform 0 0 0 DACLDA0

0

ADCBUSY0

0

ADCONVST0

MISCSR1

C90

10

POR 0 0 0 0 0 MINI1_PSDIS

AUX_PSEN

MINI0_PSDIS

MISCSR2

C91

11

POR

USB_HUBMODE

W_DISABLE

ETH1_OFF

ETH0_OFF

0

USB_HUBDIS

USB_PBDIS

USB_OBDIS

MISCSR3

C92

12

Platform 0 0 0 0

USB_PBOC

PBRESET

USB_PB_SMBEN

USB_OB_SMBEN

Reserved

C93

13

n/a 0 0 0 0 0 0 0 0

Reserved

C94

14

n/a 0 0 0 0 0 0 0 0

Reserved

C95

15

n/a 0 0 0 0 0 0 0 0

Reserved

C96

16

n/a 0 0 0 0 0 0 0 0

FPGA Registers

8 VL-EBX-38 Programmer’s Reference Manual

Identifier

I/O

Address

Offset

Reset

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

C97

17

n/a 0 0 0 0 0 0 0 0

Reserved

C98

18

n/a 0 0 0 0 0 0 0 0

Reserved

C99

19

n/a 0 0 0 0 0 0 0 0

Reserved

C9A

1A

n/a 0 0 0 0 0 0 0 0

Reserved

C9B

1B

n/a 0 0 0 0 0 0 0 0

DIOIMASK1

C9C

1C

Platform 0 0 0 0 0 0 0 IMASK_DIO1

DIOIMASK2

C9D

1D

n/a 0 0 0 0 0 0 0 0

DIOISTAT1

C9E

1E

Platform 0 0 0 0 0 0 0 ISTAT_DIO1

DIOISTAT2

C9F

1F

n/a 0 0 0 0 0 0 0 0

DIOCR

CA0

20

Platform

IRQEN

IRQSEL2

IRQSEL1

IRQSEL0 0 0 0 0

AUXDIR

CA1

21

resetSX

DIR_GPIO8

DIR_GPIO7

DIR_GPIO6

DIR_GPIO5

DIR_GPIO4

DIR_GPIO3

DIR_GPIO2

DIR_GPIO1

AUXPOL

CA2

22

resetSX

POL_GPIO8

POL_GPIO7

POL_GPIO6

POL_GPIO5

POL_GPIO4

POL_GPIO3

POL_GPIO2

POL_GPIO1

AUXOUT

CA3

23

resetSX

OUT_GPIO8

OUT_GPIO7

OUT_GPIO6

OUT_GPIO5

OUT_GPIO4

OUT_GPIO3

OUT_GPIO2

OUT_GPIO1

AUXIN

CA4

24

n/a

IN_GPIO8

IN_GPIO7

IN_GPIO6

IN_GPIO5

IN_GPIO4

IN_GPIO3

IN_GPIO2

IN_GPIO1

AUXIMASK

CA5

25

Platform

IMASK_GPIO8

IMASK_GPIO7

IMASK_GPIO6

IMASK_GPIO5

IMASK_GPIO4

IMASK_GPIO3

IMASK_GPIO2

IMASK_GPIO1

AUXISTAT

CA6

26

Platform

ISTAT_GPIO8

ISTAT_GPIO7

ISTAT_GPIO6

ISTAT_GPIO5

ISTAT_GPIO4

ISTAT_GPIO3

ISTAT_GPIO2

ISTAT_GPIO1

AUXMODE1

CA7

27

resetSX

MODE_GPIO8

MODE_GPIO7

MODE_GPIO6

MODE_GPIO5

MODE_GPIO4

MODE_GPIO3

MODE_GPIO2

MODE_GPIO1

WDT_CTL

CA8

28

Platform

IRQEN

IRQSEL2

IRQSEL1

IRQSEL0

0

RESET_EN

WDT_EN

WDT_STAT

WDT_VAL

CA9

29

Platform

msb

<============>

lsb

XCVRMODE

CAA

2A

Platform 0 0 0 0

COM4_MODE

COM3_MODE

COM2_MODE

COM1_MODE

AUXMODE2

CAB

2B

Platform

IRQEN

IRQSEL2

IRQSEL1

IRQSEL0 0 0 0 0

FANCON

CAC

2C

Platform 0 0 0 0 0 0 0 FAN_OFF

Reserved

CAD

2D

n/a 0 0 0 0 0 0 0 0

FANTACHLS

CAE

2E

Platform

msb

<============>

lsb

FPGA Registers

9 VL-EBX-38 Programmer’s Reference Manual

Identifier

I/O

Address

Offset

Reset

D7

D6

D5

D4

D3

D2

D1

D0

FANTACHMS

CAF

2F

Platform

msb

<============>

lsb

TEMPICR

CB0

30

Platform

IRQEN

IRQSEL2

IRQSEL1

IRQSEL0

IMASK_BATTLO

W

IMASK_EVENT

IMASK_THERM

IMASK_ALERT

TEMPISTAT

CB1

31

Platform

BATTLOW 0 0 0 ISTAT_BATTLOW

ISTAT_EVENT

ISTAT_THERM

ISTAT_ALERT

Reserved

CB2

32

n/a 0 0 0 0 0 0 0 0

Reserved

CB3

33

n/a 0 0 0 0 0 0 0 0

Reserved

CB4

34

n/a 0 0 0 0 0 0 0 0

Reserved

CB5

35

n/a 0 0 0 0 0 0 0 0

UARTMODE1

CB6

36

n/a 0 0 0 0 0 0 0 0

UARTMODE2

CB7

37

n/a 0 0 0 0 0 0 0 0

ISACON1

CB8

38

Platform

ISA_IRQ11

ISA_IRQ10

ISA_IRQ9

ISA_IRQ7

ISA_IRQ6

ISA_IRQ5

ISA_IRQ4

ISA_IRQ3

ISACON2

CB9

39

Platform

ISA_ACCESS

0 0 ISA_16MODE

0

ISA_IRQ15

ISA_IRQ14

ISA_IRQ12

Reserved

CBA

3A

n/a 0 0 0 0 0 0 0 0

Reserved

CBB

3B

n/a 0 0 0 0 0 0 0 0

8254 Timers

Address 0

CBC

3C

Platform

msb

<============>

lsb

8254 Timers

Address 1

CBD

3D

Platform

msb

<============>

lsb

8254 Timers

Address 2

CBE

3E

Platform

msb

<============>

lsb

8254 Timers

Address 3

CBF

3F

Platform

msb

<============>

lsb

Reserved

CC0

40

n/a 0 0 0 0 0 0 0 0

Reserved

CC1

41

n/a 0 0 0 0 0 0 0 0

Reserved

CC2

42

n/a 0 0 0 0 0 0 0 0

Reserved

CC3

43

n/a 0 0 0 0 0 0 0 0

UART1CR

CC4

44

Platform

UART1_EN 0 0 0 UART1_BASE3

UART1_BASE2

UART1_BASE1

UART1_BASE0

UART2CR

CC5

45

Platform

UART2_EN 0 0 0 UART2_BASE3

UART2_BASE2

UART2_BASE1

UART2_BASE0