VersaLogic SandCat Programmer's Reference Manual

REV. November 2018

SandCat

Programmer’s
Reference
Manual

(VL-EPM-39)

Intel® Atom™-based Single
Board Computer with Ethernet ,
Video, USB, SATA, Serial I/O,
Digital I/O, Counter/Timers, Mini
PCIe, mSATA and
PCI/104-Plus Interface.

WWW.VERSALOGIC.COM

12100 SW Tualatin Road
Tualatin, OR 97062-7341

[phone]

Fax [phone]

Copyright © 2018 VersaLogic Corp. All right s r es er ved.

Notice:

Although every effort has been made to ensure this document is error-free, VersaLogic makes no
representations or warranties with respect to this product and specifically disclaims any implied warranties
of merchantability or fitness for any particular purpose.

VersaLogic reserves the right to revise this product and associated documentation at any time without
obligation to notify anyone of such changes.

PC/104, PC/104-Plus, and the PC/104 logo are trademarks of the PC/104 Consortium.

EPM-39 Programmer’s Reference Manual ii

Product Release Notes

Release 1

First release of this document.

Support

The EPM-39 support page contains additional information and resources for this product
including:

 Reference Manual (PDF format)
 Operating system information and software drivers
 Data sheets and manufacturers’ links for chips used in this product
 BIOS information and upgrades
 Utility routines and benchmark software

The VersaTech KnowledgeBase is an invaluable resource for resolving technical issues with
your VersaLogic product.

VersaTech KnowledgeBase

EPM-39 Programmer’s Reference Manual iii

Contents

Introduction ................................................................................................................... 1

Related Documents ............................................................................................................. 1

System Resources and Maps ....................................................................................... 2

Memory Map ...................................................................................................................... 2

Interrupts ............................................................................................................................. 2

FPGA Registers ............................................................................................................. 4

FPGA I/O Space ................................................................................................................. 4

ISA Bus Addressing and LPC I/O and Memory Map ........................................... 4

FPGA Register Map ........................................................................................................... 5

FPGA Register Descriptions............................................................................................... 8

Product Information Registers ............................................................................... 8

BIOS and Jumper Status Register .......................................................................... 9

Timer Registers .................................................................................................... 10

Miscellaneous FPGA Registers ........................................................................... 13

Programming Information f or Hardware Interfaces .................................................. 28

Processor WAKE# Capabilities........................................................................................ 28

Watchdog Timer ............................................................................................................... 28

Programmable LED .......................................................................................................... 28

Tables

Table 1: Memory Map ........................................................................................................ 2

Table 2: I/O Map ................................................................................................................. 3

Table 3: FPGA I/O Map ...................................................................................................... 4

Table 4: ISA Bus I/O Map .................................................................................................. 4

Table 5: ISA Memory Map ................................................................................................. 4

Table 6: PCR – Product Code and LED Register ............................................................... 8

Table 7: PSR – Product Status Register .............................................................................. 8

Table 8: SCR –Status/Control Register .............................................................................. 9

Table 9: TICR – 8254 Timer Interrupt Control Register .................................................. 10

Table 10: TISR – 8254 Timer Interrupt Status Register ................................................... 11

Table 11: TCR – 8254 Timer Control Register ................................................................ 12

Table 12: MISCR1 – Misc. Control Register #1 .............................................................. 13

Table 13: MISCSR2 – Misc. Control Register #2 ............................................................ 14

Table 14: MISCR3 – Misc. Control Register #3 .............................................................. 15

Table 15: AUXDIR – AUX GPIO Direction Control Register ........................................ 16

Table 16: AUXPOL – AUX GPIO Polarity Control Register .......................................... 16

EPM-39 Programmer’s Reference Manual iv

Contents

Table 17: AUXOUT – AUX GPIO Output Control Register ........................................... 16

Table 18: AUXIN – AUX GPIO Input Status Register .................................................... 17

Table 19: AUXICR – AUX GPIO Interrupt Mask Register ............................................. 17

Table 20: AUXISTAT – AUX GPIO Interrupt Status Register ........................................ 17

Table 21: AUXMODE1 – AUX I/O Mode Register ........................................................ 18

Table 22: WDT_CTL – Watchdog Control Register ........................................................ 19

Table 23: WDT_VAL – Watchdog Value Register .......................................................... 20

Table 24: XCVRMODE – COM Transceiver Mode Register .......................................... 20

Table 25: AUXMODE2 - AUX I/O Mode Register #2 .................................................... 21

Table 29: TEMPICR – Temperature Interrupt Control Register ...................................... 22

Table 30: TEMPISTAT – Temperature Interrupt Status Register .................................... 22

Table 31: UART1CR – UART1 Control Register (COM1) ............................................. 23

Table 32: UARTMODE1 – UART MODE Register #1 ................................................... 24

Table 33: UARTMODE2 – UART MODE Register #2 ................................................... 26

Table 34: ISACON1 – ISA Control Register #1 ............................................................... 27

Table 35: ISACON2 – ISA Control Register #2 ............................................................... 27

EPM-39 Programmer’s Reference Manual v

1

This document provides information for users requiring register-level information for developing
applications with the VL-EPM-39.

Related Documents

The following documents available are on the EPM-39 Product Support Web Page:
 EPM-39 Hardware Reference Manual – provides information on the board’s hardware

features including connectors and all interfaces.

Introduction

EPM-39 Programmer’s Reference Manual 1

00000h – 9FFFFh

Legacy system (DOS) area

A0000h – B7FFFh

ISA memory area (VGA frame buffer is not accessible)

B8000h – BFFFFh

Text mode buffer

C0000h – CFFFFh

Video BIOS area

D0000h – DFFFFh

PCI ROM expansion area

E0000h – FFFFFh

Legacy BIOS (reserved)

2

Memory Map

Table 1: Memory Map

Interrupts

The LPC SERIRQ is used for interrupt interface to the BayTrail SoC.

System Resources and Maps

Address Range Description

Each of the following devices can have an IRQ interrupt assigned to it and each with an interrupt
enable control for IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, IRQ9, IRQ10, and IRQ11:

 8254 timers (with three interrupt status bits)
 8 AUX GPIOs (with one interrupt status bit)
 COM 1 UART (with 16550 interrupt status bits)
 Watchdog timer (one status bit)
 Thermal event interrupts
 ISA interrupts

The ISA bus supports 11 interrupts: IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, IRQ9, IRQ10, IRQ11,
IRQ12, IRQ14, and IRQ15. There is an interrupt enable control for each and by default they are
all disabled. ISA bus interrupts simply pass through to the SERIRQ (no capture in the FPGA).

Common interrupts can be assigned to multiple devices if software can deal with it (this is
common on UARTs being handled by a common ISR).

Interrupt status bits for everything except the UARTs will “stick” and are cleared by a “write­one” to a status register bit. The 16550 UART interrupts behave as defined for the 16550
registers and are a pass-through to the LPC SERIRQ.

Per the VersaAPI standard, anytime an interrupt on the SERIRQ is enabled, the slot becomes
active. All interrupts in the SERIRQ are high-true so when the slot becomes active, the slot will
be low when there is no interrupt and high when there is an interrupt.

EPM-39 Programmer’s Reference Manual 2

Table 2: I/O Map

3F8h – 3FFh

COM1 serial port default

400h – 47Fh

ACPI / Power management (reserved)

500h – 5FFh

PCH GPIO (reserved)

C80h – CBBh

EPM-39 FPGA Board Control Registers

CBCh – CBFh

EPM-39 FPGA 8254 Timer Registers

I/O Address Range Device/Owner

System Resources and Maps

EPM-39 Programmer’s Reference Manual 3

0xC80 – 0xCBB

FPGA registers

60 bytes

0xCBC – 0xCBF

8254 timer address registers

4 bytes

0xC80 - 0xCBF

FPGA registers

64 bytes

All other LPC I/O cycles

ISA bus

Depends on SoC LPC I/O traffic

0x0 – 0xFFFFFF LPC memory cycles

ISA bus

Depends on SoC LPC memory traffic

0x1000000 and higher LPC memory

cycles

TPM is the only memory device on the

LPC bus

3

FPGA I/O Space

The FPGA is mapped into I/O space on the LPC bus

 FPGA access: LPC I/O space
 FPGA access size: All 8-bit byte accesses (16-bit like registers are aligned on 16-bit word

boundaries to make word access possible in software but the LPC bus still splits the accesses
into two 8-bit accesses)

 FPGA address range: 0xC80 to 0xCBF (64-byte window)
The three 8254 timers only require four bytes of addressing and are located at the end of the

64-byte I/O block. The only requirement is that the base address must be aligned on a 4-byte
block. The table below lists the FPGA’s I/O map.

FPGA Register s

Table 3: FPGA I/O Map

Address Range Device Size

ISA BUS ADDRE S S ING AND LPC I/O AND MEMORY MAP

The FPGA implements an LPC-to-ISA bridge. The LPC bus only has the he FPGA uses I/O
space 0xC80-0xCBF. The ISA bus memory address space is16 Mbytes (24-bits of address); ISA
busy I/O addressing is limited to 64 Kbytes (16 bits of address). As such, the following will be
the allowed memory and I/O map for the ISA bus.

All LPC I/O cycles that are unclaimed by the FPGA will pass through to the ISA bus. Similarly,
all LPC memory cycles below 16 Mbytes will be passed through to the ISA bus.

Table 4: ISA Bus I/O Map

Address Range Device Size

Table 5: ISA Memory Map

Address Range Device Size

EPM-39 Programmer’s Reference Manual 4

Ignored by FPGA

EPM-39 Programmer’s Reference Manual 5

FPGA Register Map

Register Access Key

Reset Status Key

R/W Read/Write POR Power-on reset (only resets one time when input power comes on)

RO Read-only (status or reserved) Platform

Resets prior to the processor entering t he S0 power state (that is, at power-on

and in sleep states)

R/WC Read-status/Write-1-to-Clear resetSX

• If FPGA_PSEN is a '0' in MISCSR1 (default setting), t hen this is the
same as the Platform reset.

• If FPGA_PSEN is a programmed to a '1', then it is the same as the
Power-On Reset (POR).

RSVD Reserved. Only write 0 to this bit; ignore all read values. n/a Reset doesn't apply to status or res erved registers

Identifier

I/O

Address

Offset

Reset

Type

D7 D6 D5 D4 D3 D2 D1 D0

PCR C80 0 Platform PLED PRODUCT_CODE
PSR C81 1 n/a REV_LEVEL EXTEMP CUSTOM BETA
SCR C82 2 Platform LED_DEBUG WORKVER

RSVD

RSVD RSVD
TICR C83 3 Platform IRQEN IRQSEL2 IRQSEL1 IRQSEL0 RSVD IMASK_TC5 IMASK_TC4 IMASK_TC3
TISR C84 4 Platform RSVD RSVD RSVD RSVD RSVD ISTAT_TC5 ISTAT_TC4 ISTAT_TC3
TCR C85 5 Platform TIM5GATE TIM4GATE TIM3GATE TM45MODE TM4CLKSEL TM3CLKSEL RSVD TMRFULL

Reserved C86 6 n/a RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
Reserved C87 7 n/a RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

Reserved

C88 8 n/a RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

Reserved

C89 9 n/a RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

Reserved

C8A A n/a RSVD RSVD RSVD

Reserved

C8B B n/a RSVD RSVD RSVD

Reserved

C8C C n/a RSVD RSVD RSVD

Reserved C8D D n/a RSVD RSVD RSVD

Reserved

C8E E n/a RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD