VersaLogic Osprey, VL-EPU-3311 Programmer's Reference Manual

Programmer’s

Reference

Manual

REV. May 2018

Osprey

(VL-EPU-3311)

Intel® Atom™ E38xx-based
Embedded Processing Unit with
SATA, Ethernet, USB, Serial,
Video, Mini PCIe Sockets, and
microSD.

WWW.VERSALOGIC.COM

12100 SW Tualatin Road
Tualatin, OR 97062-7341

[phone]

Fax [phone]

Copyright © 2016-2018 VersaLogic Corp. All rights reserved.

Notice:

Although every effort has been made to ensure this document is error-free, VersaLogic makes no
representations or warranties with respect to this product and specifically disclaims any implied warranties
of merchantability or fitness for any particular purpose.

VersaLogic reserves the right to revise this product and associated documentation at any time without
obligation to notify anyone of such changes.

PC/104, PC/104-Plus, and the PC/104 logo are trademarks of the PC/104 Consortium.

EPU-3311 Programmer’s Reference Manual ii

Product Release Notes

VersaTech KnowledgeBase

Release 1.3

Updated the Uartmode1 – Uart Mode Register #1 section

Release 1.2

Updated the UART Base Addresses in Tables 23 and 24.

Release 1.1

Updated Related Documents section.

Release 1

First release of this document.

Support

The EPU-3311 support page, at www.versalogic.com/private/ospreysupport.asp contains additional
information and resources for this product including:

 Reference Manual (PDF format)

 Operating system information and software drivers

 Data sheets and manufacturers’ links for chips used in this product

 BIOS information and upgrades

 Utility routines and benchmark software

The VersaTech KnowledgeBase is an invaluable resource for resolving technical issues with
your VersaLogic product.

EPU-3311 Programmer’s Reference Manual iii

Contents

Introduction ................................................................................................................... 1

Related Documents ............................................................................................................. 1

System Resources ........................................................................................................ 2

Interrupts ............................................................................................................................. 2

FPGA I/O Space ................................................................................................................. 2

FPGA Registers ............................................................................................................. 3

Register Access Key ........................................................................................................... 3

Reset Status Key ................................................................................................................. 3

FPGA Register Map ........................................................................................................... 4

FPGA Register Descriptions............................................................................................... 7

Product Information Registers ............................................................................... 7

BIOS and Jumper Status Register .......................................................................... 8

Timer Registers ...................................................................................................... 8

Miscellaneous FPGA Registers ........................................................................... 11

Programming Information for Hardware Interfaces .................................................. 24

Watchdog Timer ............................................................................................................... 24

Programmable LED .......................................................................................................... 24

Processor WAKE# Capabilities........................................................................................ 25

Tables

Table 1: FPGA I/O Map ...................................................................................................... 2

Table 2: FPGA Register Map.............................................................................................. 4

Table 3: PCR – Product Code and LED Register ............................................................... 7

Table 4: PSR – Product Status Register .............................................................................. 7

Table 5: SCR –Status/Control Register .............................................................................. 8

Table 6: TICR – 8254 Timer Interrupt Control Register .................................................... 8

Table 7: TISR – 8254 Timer Interrupt Status Register ....................................................... 9

Table 8: TCR – 8254 Timer Control Register .................................................................. 10

Table 9: MISCSR1 – Misc. Control Register #1 .............................................................. 11

Table 10: MISCSR2 – Misc. Control Register #2 ............................................................ 12

Table 11: MISCSR3 – Misc. Control Register #3 ............................................................ 13

Table 12: AUXDIR – AUX GPIO Direction Control Register ........................................ 14

Table 13: AUXPOL – AUX GPIO Polarity Control Register .......................................... 14

Table 14: AUXOUT – AUX GPIO Output Control Register ........................................... 14

Table 15: AUXIN – AUX GPIO Input Status Register .................................................... 15

Table 16: AUXICR – AUX GPIO Interrupt Mask Register ............................................. 15

EPU-3311 Programmer’s Reference Manual iv

Contents

Table 17: AUXISTAT – AUX GPIO Interrupt Status Register ........................................ 15

Table 18: AUXMODE1 – AUX I/O Mode Register ........................................................ 16

Table 19: WDT_CTL – Watchdog Control Register ........................................................ 17

Table 20: WDT_VAL – Watchdog Control Register ....................................................... 18

Table 21: XCVRMODE – COM Transceiver Mode Register .......................................... 18

Table 22: AUXMODE2 - AUX I/O Mode Register #2 .................................................... 19

Table 23: UART1CR – UART1 Control Register (COM1) ............................................. 20

Table 24: UART2CR – UART2 Control Register (COM2) ............................................. 21

Table 25: UARTMODE1 – UART MODE Register #1 ................................................... 22

Table 26: UARTMODE2 – UART MODE Register #2 ................................................... 23

EPU-3311 Programmer’s Reference Manual v

1

This document provides information for users requiring register-level information for developing
applications with the VL-EPU-3311.

Related Documents

The following documents available are on the EPU-3311 Product Support Web Page:

 VL-EPU-3311 Hardware Reference Manual – provides information on the board’s hardware

features including connectors and all interfaces.

This document is available through the software page:

 VersaAPI Installation and Reference Guide – describes the shared library of API calls for

reading and controlling on-board devices on certain VersaLogic products.

Introduction

EPU-3311 Programmer’s Reference Manual 1

Address Range

Device

Size

0x1C80 – 0x1CBB

FPGA registers

60 bytes

0x1CBC – 0x1CBF

8254 timer address registers

4 bytes

2

Interrupts

The LPC SERIRQ is used for interrupt interface to the BayTrail SoC.

Each of the following devices can have an IRQ interrupt assigned to it and each with an interrupt
enable control for IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, IRQ9, IRQ10, and IRQ11:

 8254 timers (with three interrupt status bits)

 8x GPIOs (with one interrupt status bit per GPIO)

 COM 1 UART (with 16550 interrupt status bits)

 COM 2 UART (with 16550 interrupt status bits)

 Watchdog timer (one status bit)

Common interrupts can be assigned to multiple devices if software can deal with it (this is
common on UARTs being handled by a common ISR).

System Resources

Interrupt status bits for everything except the UARTs will “stick” and are cleared by a “write­one” to a status register bit. The 16550 UART interrupts behave as defined for the 16550
registers and are a pass-through to the LPC SERIRQ.

Per the VersaAPI standard, anytime an interrupt on the SERIRQ is enabled, the slot becomes
active. All interrupts in the SERIRQ are high-true so when the slot becomes active, the slot will
be low when there is no interrupt and high when there is an interrupt.

FPGA I/O Space

The FPGA is mapped into I/O space on the LPC bus. The address range is mapped into a 64 byte
I/O window.

 FPGA access: LPC I/O space

 FPGA access size: All 8-bit byte accesses (16-bit like registers are aligned on 16-bit word

boundaries to make word access possible in software but the LPC bus still splits the accesses
into two 8-bit accesses)

 FPGA address range: 0x1C80 to 0x1CBF (a 64-byte window)

The three 8254 timers only require four bytes of addressing and are located at the end of the
64-byte I/O block. The only requirement is that the base address must be aligned on a 4-byte
block. Table 1 lists the FPGA’s I/O map.

EPU-3311 Programmer’s Reference Manual 2

Table 1: FPGA I/O Map

Register Access Key

R/W

Read/Write

RO

Read-only (status or reserved)

R/WC

Read-status/Write-1-to-Clear

RSVD

Reserved. Only write 0 to this bit; ignore all read values.

Reset Status Key

POR

Power-on reset (only resets one time when input power comes on)

Platform

Resets prior to the processor entering the S0 power state (that is, at power-on and in sleep states)

resetSX

 If AUX_PSEN is a '0' in MISCSR1 (default setting), then this is the same as the Platform reset.
 If AUX_PSEN is a programmed to a '1', then it is the same as the Power-On Reset (POR).

n/a

Reset doesn't apply to status or reserved registers

3

This chapter describes the FPGA registers.

 Table 2 (beginning on the following page) lists all 64 FPGA registers

 Table 3 (refer to page 7) through Table 26 provide bit-level information on the individual

FPGA registers

Register Access Key

FPGA Registers

Reset Status Key

EPU-3311 Programmer’s Reference Manual 3

EPU-3311 Programmer’s Reference Manual 4

FPGA Register Map

Table 2: FPGA Register Map

Identifier

I/O

Address

Offset

Reset

Type

D7

D6

D5

D4

D3

D2

D1

D0

PCR

1C80 0 Platform

PLED

PRODUCT_CODE

PSR

1C81 1 n/a

REV_LEVEL

EXTEMP

CUSTOM

BETA

SCR

1C82 2 Platform 0 0

0

LED_DEBUG

WORKVER 0 0 0 TICR

1C83 3 Platform

IRQEN

IRQSEL2

IRQSEL1

IRQSEL0

0

IMASK_TC5

IMASK_TC4

IMASK_TC3

TISR

1C84 4 Platform

INTRTEST

TMRTEST

TMRIN4

TMRIN3

0

ISTAT_TC5

ISTAT_TC4

ISTAT_TC3

TCR

1C85 5 Platform

TIM5GATE

TIM4GATE

TIM3GATE

TM45MODE

TM4CLKSEL

TM3CLKSEL

TMROCTST

TMRFULL

Reserved

1C86 6 n/a 0 0 0 0 0 0 0 0

Reserved

1C87 7 n/a 0 0 0 0 0 0 0 0

Reserved

1C88 8 n/a 0 0 0 0 0 0 0 0

Reserved

1C89 9 n/a 0 0 0 0 0 0 0 0

Reserved

1C8A A n/a 0 0 0 0 0 0 0 0

Reserved

1C1B B n/a 0 0 0 0 0 0 0 0

Reserved

1C8C C n/a 0 0 0 0 0 0 0 0

Reserved

1C8D D n/a 0 0 0 0 0 0 0 0

Reserved

1C8E E n/a 0 0 0 0 0 0 0 0

Reserved

1C8F F n/a 0 0 0 0 0 0 0 0

MISCSR1

1C90

10

POR 0 0 0 0

0

MINI2_PSDIS

AUX_PSEN

MINI1_PSDIS

MISCSR 2

1C91

11

POR

0

W_DISABLE

0

ETH0_OFF

USB_USBID

USB_PB2DIS

USB_PB1DIS

USB_OBDIS

MISCSR 3

1C92

12

Platform

PROCHOT

LVDS_OC 0 0 0 PBRESET 0 0

Reserved

1C93

13

n/a 0 0 0 0 0 0 0 0

Reserved

1C94

14

n/a 0 0 0 0 0 0 0 0

Reserved

1C95

15

n/a 0 0 0 0 0 0 0 0

Reserved

1C96

16

n/a 0 0 0 0 0 0 0 0