VersaLogic Lion VL-EPMe-42 Reference Manual

Lion

PCIe/104™ OneBank™ Inter face

Programmer’s
Reference
Manual

REV. May 2018

(VL-EPMe-42)

Intel® Core™-based Single Board Computer with
Dual Ethernet, Video, USB, S A TA, Serial I/O,
Digital I/O, Trust ed P latform Module security,
Counter/Timers, Mini PCIe, mSATA, SPX, and

WWW.VERSALOGIC.COM

12100 SW Tualatin Road
Tualatin, OR 97062-7341

[phone]

Fax [phone]

Copyright © 2017-2018 VersaLogic Corp. All rights reserved.

Notice:

Although every effort has been made to ensure this document is error-free, VersaLogic makes no representations or
warranties with respect to this product and specifically disclaims any implied warranties of merchantability or fitness
for any particular purpose.

VersaLogic reserves the right to revise this product and associated documentation at any time without obligation to
notify anyone of such changes.

*

Other names and brands may be claimed as the property of others.

Lion (VL-EPMe-42) Programmer’s Reference Manual ii

Product Release Notes

Release 1.3- Updated Uartmode1 – Uart Mode Register #1 section
Release 1.2- Added descriptions to the FPGA table
Release 1.1- Updated Processor Wake# section
Release 1.0- Initial Production Draft

Support

The EPMe-42 support page contains additional information and resources for this product including:

 Reference Manual (PDF format)
 Operating system information and software drivers
 Data sheets and manufacturers’ links for chips used in this product
 BIOS information and upgrades
 Utility routines and benchmark software

The VersaTech KnowledgeBase is an invaluable resource for resolving technical issues with
your VersaLogic product.

VersaTech KnowledgeBase

Lion (VL-EPMe-42) Programmer’s Reference Manual iii

Contents

Overview ........................................................................................................................ 1

Related Documents ............................................................................................................. 1

System Resources and Maps ....................................................................................... 2

Memory Map ...................................................................................................................... 2

Interrupts ............................................................................................................................. 2

FPGA Registers ............................................................................................................. 4

FPGA I/O Space ................................................................................................................. 4

FPGA Register Map ........................................................................................................... 5

FPGA Register Descriptions............................................................................................... 8

Product Information Registers ............................................................................... 8

BIOS and Jumper Status Register .......................................................................... 9

Timer Registers .................................................................................................... 11

SPI Control Registers .......................................................................................... 14

SPI Data Registers ............................................................................................... 16

SPI Debug Control Register and mSATA/PCIe Select Control Register ............ 17

Miscellaneous FPGA Registers ........................................................................... 18

Programming Information f or Hardware Interfaces .................................................. 33

Processor WAKE# Capabilities........................................................................................ 33

Watchdog Timer ............................................................................................................... 33

Industrial I/O Functions and SPI Interface ....................................................................... 34

Programmable LED .......................................................................................................... 34

Lion (VL-EPMe-42) Programmer’s Reference Manual iv

1

1

This document provides information for users requiring register-level information for develop ing
applications as it relates the FPGA functionality with the VL-EPMe-42.

Related Documents

The following documents available are on the EPMe-42 Product Support Web Page:
 EPMe-42 Hardware Reference Manual – provides information on the board’s hardware features

including connectors and all interfaces.

 EPMe-42 BIOS Reference Manual – provides information on acc essing and configuring s ettings in the

BIOS Setup utility. All BIOS menus, submenus, and configuration options ar e described.

This document is available through the software page:

VersaAPI Installation and Reference Guide – d escribes the shared library of API calls for reading



and contro l ling on-board devices on certain VersaLogic products.

Overview

Lion (VL-EPMe-42) Programmer’s Reference Manual 1

2

Memory Map

Table 1: Memory Map

00000h – 9FFFFh Legacy system (DOS) area
A0000h – B7FFFh ISA memory area (VGA f rame buffer is not accessible)
B8000h – BFFFFh Text mode buffer
C0000h – CFFFFh Video BIOS area
D0000h – DFFFFh PCI ROM expansion area
E0000h – FFFFFh Legacy BIOS (reserved)

Interrupts

System Resources and Maps

Address Range Description

The LPC SERIRQ is used for interrupt interface to the Kaby Lake SoC.
Each of the following devices can have an IRQ interrupt assigned to it and each with an interrupt enable

control for IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, IRQ9, IRQ10, and IRQ11:

 8254 timers (with three interrupt status bits)
 8 AUX GPIOs (with one interrupt status bit)
 COM 1 UART (with 16550 interrupt status bits)
 COM 2 UART (with 16550 interrupt status bits)
 Watchdog timer (one interrupt status bit)
 SPX expansion interface (interrupt sta tus is determined by the devices on this interface). The interface

supports two interrupts.

 Thermal event and battery-low interrupts
Note:

The EPMe-42 also has two COM ports (COM3, COM4) that are supported by the HSUARTs in the

processor.

The FPGA supports 11 interrupts via the LPC SERIRQ interface: IRQ3, IRQ4, IRQ5, IRQ 6, IRQ7, IRQ9,
IRQ10, IRQ11, IRQ12, IRQ14, and IRQ15. There is an interrupt enable control for each and by default
they are all disabled.

Common interrupts can be assigned to multiple devices (this is common on UARTs being handled by a
common ISR).

Interrupt status bits for everything except the UARTs will “stick” and are cleared by a “write-one” to a
status register bit. The 16550 UART interrupts behave as defined for the 16550 registers and are a pass­through to the LPC SERIRQ.

Per the VersaAPI standard, anytime an interrupt on the SERIRQ is enabled, the slot becomes active. All
interrupts in t he SERIRQ are high-true so when the slot becomes active, the slot will be low when there is
no interrupt and high when there is an interrupt.

Lion (VL-EPMe-42) Programmer’s Reference Manual 2

Table 2: I/O Map

I/O Address Range Device/Owner

2F8h – 2FFh COM2 serial port default
3B0h – 3DFh Legacy VGA registers
3F8h – 3FFh COM1 serial port default
400h – 47Fh ACPI / P ower m anagement (reserved)
500h – 5FFh PCH GPIO (reserved)
C80h – CBBh EPMe-42 FPGA Board Control Registers
CBCh – CBFh EPMe-42 FPGA 8254 Timer Registers

System Resources and Maps

Lion (VL-EPMe-42) Programmer’s Reference Manual 3

3

FPGA I/O Space

The FPGA is mapped into I/O space on the LPC bus. The address range is mapped into 64 byte I/O
window.

 FPGA access: LPC I/O space
 FPGA access size: All 8-bit byte accesses (16-bit like registers are aligned on 16-bit word boundaries

to make word access possible in software but the LPC bus still splits the accesses into two 8-bit
accesses)

 FPGA address range: 0xC80 to 0xCBF (64-byte window)
The three 8254 timers only require four bytes of addressing and are located at the end of the 64-byte I/O

block. The only requirement is that the base address must be aligned on a 4-byte block. Table 4 lists the
FPGA’s I/O map.

FPGA Registers

FPGA Registers

Table 3: FPGA I/O Map

Address Range Device Size

0xC80 – 0xCBB FPGA registers 60 bytes
0xCBC – 0xCBF 8254 timer address regist ers 4 bytes

Lion (VL-EPMe-42) Programmer’s Reference Manual 4

FPGA Registers

Lion (VL-EPMe-42) Programmer’s Reference Manual 5

FPGA Register Map

Register Access Key

Reset Status Key

R/W Read/Write POR Power-on reset (only resets one time when input power comes on)

RO Read-only (status or reserved) Platform

Resets prior to the processor entering the S0 power state (that is, at power-on
and in sleep states)

R/WC Read-status/Write-1-to-Clear resetSX

• If AUX_PSEN is a '0' in MISCSR1 (default sett i ng), then this is the same
as the Platform reset.

• If SUX_PSEN is a programmed to a '1', then i t is the same as the
Power-On Reset (POR).

WO Write-Only n/a

• Reset doesn't apply to status or reserved regis ters

ROC Read-Only and clear-to-0 after readi ng

RSVD Reserved. Only write 0 to this bit; ignore all read values.

I/O

Address

Offset Reset D7 D6 D5 D4 D3 D2 D1 D0 Description

C80 0 Platform PLED PRODUCT_CODE

PCR - Product Code & PLED

C81 1 n/a REV_LEVEL EXTEMP CUSTOM BETA

PSR - Rev, Ext Tmp, Custom, Beta

C82 2 Platform BIOS_JMP BIOS_OR BIOS_SEL LED_DEBUG WORKVER 0 GPI_JMP 0

SCR - BIOS & Jumper status

C83 3 Platform IRQEN IRQSEL2 IRQSEL1 IRQSEL0 0 IMASK_TC5 IMASK_TC4 IMASK_TC3

TICR - Timer Interrupt Control Register

C84 4 Platform INTRTEST TMRTEST TMRIN4 TMRIN3 0 ISTAT_TC5 ISTAT_TC4 ISTAT_TC3

TISR - Interrupt Status Reg (& timer debug test)

C85 5 Platform TIM5GATE TIM4GATE TIM3GATE TM45MODE TM4CLKSEL TM3CLKSEL TMROCTST TMRFULL

TCR - Timer Control Reg (also see AUX GPIO Secondary Modes later)

C86 6 n/a 0 0 0 0 0 0 0 0

Reserved

C87 7 n/a 0 0 0 0 0 0 0 0

Reserved

C88 8 Platform CPOL CPHA SPILEN1 SPILEN0 MAN_SS SS2 SS1 SS0

SPICONTROL (traditional location for SPX regs)

C89 9 Platform IRQSEL1 IRQSEL0 SPICLK1 SPICLK0 HW_IRQ_EN LSBIT_1ST HW_INT BUSY

SPISTATUS

C8A A Platform msb <============> lsb

SPIDATA0 Least Significant Byte

C8B B Platform msb <============> lsb

SPIDATA1

FPGA Registers

Lion (VL-EPMe-42) Programmer’s Reference Manual 6

C8C C Platform msb <============> lsb

SPIDATA2

C8D D Platform msb <============> lsb

SPIDATA3 Most Significant Byte and Start SPI Cycle when written

C8E E Platform 0 MUXSEL2 MUXSEL1 MUXSEL0 0 SERIRQEN SPILB 0

SPIMISC - Custom SPI I/F controls, mSATA/PCIe Mux Select

C8F F n/a 0 0 0 0 0 0 0 0

Reserved

C90 10 POR 0 0 0 0 0 0 AUX_PSEN MINI_PSDIS

MISCSR1 - Power Control Regs

C91 11 POR 0 W _DISABLE ETH1_OFF ETH0_OFF 0 0 0 0

MISCSR2 - USB, Ethernet Control, misc.

C92 12 Platform 0 0 0 0 0 PBRESET 0 0

MISCSR3 - Misc Control Reg

C93 13 n/a 0 0 0 0 0 0 0 0

Reserved to align 16-bit regs on even byte boundaries

C94 14 n/a 0 0 0 0 0 0 0 0

Reserved for Digital I/O registers used on other products

C95 15 n/a 0 0 0 0 0 0 0 0

Reserved for Digital I/O registers used on other products

C96 16 n/a 0 0 0 0 0 0 0 0

Reserved for Digital I/O registers used on other products

C97 17 n/a 0 0 0 0 0 0 0 0

Reserved for Digital I/O registers used on other products

C98 18 n/a 0 0 0 0 0 0 0 0

Reserved for Digital I/O registers used on other products

C99 19 n/a 0 0 0 0 0 0 0 0

Reserved for Digital I/O registers used on other products

C9A 1A n/a 0 0 0 0 0 0 0 0

Reserved for Digital I/O registers used on other products

C9B 1B n/a 0 0 0 0 0 0 0 0

Reserved for Digital I/O registers used on other products

C9C 1C n/a 0 0 0 0 0 0 0 0

Reserved for Digital I/O registers used on other products

C9D 1D n/a 0 0 0 0 0 0 0 0

Reserved for Digital I/O registers used on other products

C9E 1E n/a 0 0 0 0 0 0 0 0

Reserved for Digital I/O registers used on other products

C9F 1F n/a 0 0 0 0 0 0 0 0

Reserved for Digital I/O registers used on other products

CA0 20 n/a 0 0 0 0 0 0 0 0

Reserved for Digital I/O registers used on other products

CA1 21 resetSX DIR_GPIO8 DIR_GPIO7 DIR_GPIO6 DIR_GPIO5 DIR_GPIO4 DIR_GPIO3 DIR_GPIO2 DIR_GPIO1

AUXDIR - AUX GPIO I/O Direction Control

CA2 22 resetSX POL_GPIO8 POL_GPIO7 POL_GPIO6 POL_GPIO5 POL_GPIO4 POL_GPIO3 POL_GPIO2 POL_GPIO1

AUXPOL - AUX GPIO I/O Polarity Control

CA3 23 resetSX OUT_GPIO8 OUT_GPIO7 OUT_GPIO6 OUT_GPIO5 OUT_GPIO4 OUT_GPIO3 OUT_GPIO2 OUT_GPIO1

AUXOUT - AUX GPIO I/O Output Value

CA4 24 n/a IN_GPIO8 IN_GPIO7 IN_GPIO6 IN_GPIO5 IN_GPIO4 IN_GPIO3 IN_GPIO2 IN_GPIO1

AUXIN - AUX GPIO I/O Input Value

CA5 25 Platform IMASK_GPIO8 IMASK_GPIO7 IMASK_GPIO6 IMASK_GPIO5 IMASK_GPIO4 IMASK_GPIO3 IMASK_GPIO2 IMASK_GPIO1

AUXIMASK- AUX GPIO I/O Interrupt Mask and Control

CA6 26 Platform ISTAT_GPIO8 ISTAT_GPIO7 ISTAT_GPIO6 ISTAT_GPIO5 ISTAT_GPIO4 ISTAT_GPIO3 ISTAT_GPIO2 ISTAT_GPIO1

AUXISTAT - AUX GPIO I/O Interrupt Mask and Status

FPGA Registers

Lion (VL-EPMe-42) Programmer’s Reference Manual 7

CA7 27 resetSX MODE_GPIO8 MODE_GPIO7 MODE_GPIO6 MODE_GPIO5 MODE_GPIO4 MODE_GPIO3 MODE_GPIO2 MODE_GPIO1

AUXMODE1 - AUX GPIO I/O Mode Register

CA8 28 Platform IRQEN IRQSEL2 IRQSEL1 IRQSEL0 0 RESET_EN WDT_EN WDT_STAT

WDT_CTL - Watchdog Control

CA9 29 Platform msb <============> lsb

WDT_VAL - Watchdog Value (in seconds)

CAA 2A Platform 0 0 0 0 0 0 COM2_MODE COM1_MODE

XCVRMODE - COM Port Transceiver Mode Register (all ports)

CAB 2B Platform IRQEN IRQSEL2 IRQSEL1 IRQSEL0 0 0 0 0

AUXMODE2

CAC 2C Platform 0 0 0 0 0 0 0 FAN_OFF

FANCON - Fan Control

CAD 2D n/a 0 0 0 0 0 0 0 0

Reserved for future fan control

CAE 2E Platform msb <============> lsb

FANTACHLS - Fan TACH LS 8 Bits

CAF 2F Platform msb <============> lsb

FANTACHMS - Fan TACH MS 8 Bits

CB0 30 Platform IRQEN IRQSEL2 IRQSEL1 IRQSEL0 IMASK_BATTLOW IMASK_EVENT IMASK_THERM IMASK_ALERT

TEMPICR - Temperature (HW Monitor) Interrupt Mask and Control

CB1 31 Platform BATTLOW 0 0 0 ISTAT_BATTLOW ISTAT_EVENT ISTAT_THERM ISTAT_ALERT

TEMPISTAT - Temperature Interrupt Mask and Status

CB2 32 Platform IRQEN IRQSEL2 IRQSEL1 IRQSEL0 UART1_BASE3 UART1_BASE2 UART1_BASE1 UART1_BASE0

UART1CR - Internal UART1 Control Register

CB3 33 Platform IRQEN IRQSEL2 IRQSEL1 IRQSEL0 UART2_BASE3 UART2_BASE2 UART2_BASE1 UART2_BASE0

UART2CR - Internal UART2 Control Register

CB4 34 n/a 0 0 0 0 0 0 0 0

Reserved for UART3CR

CB5 35 n/a 0 0 0 0 0 0 0 0

Reserved for UART4CR

CB6 36 Platform 0 0 UART2_485ADC UART1_485ADC 0 0 UART2_EN UART1_EN

UARTMODE1 - UART Mode register #1

CB7 37 Platform 0 0 0 0 0 0 0 FAST_MODE

UARTMODE2 - UART Mode register #2

CB8 38 n/a 0 0 0 0 0 0 0 0

Reserved

CB9 39 n/a 0 0 0 0 0 0 0 0

Reserved

CBA 3A n/a 0 0 0 0 0 0 0 0

Reserved

CBB 3B n/a 0 0 0 0 0 0 0 0

Reserved

CBC 3C Platform msb <============> lsb

8254 Timers Address 0

CBD 3D Platform msb <============> lsb

8254 Timers Address 1

CBE 3E Platform msb <============> lsb

8254 Timers Address 2

CBF 3F Platform msb <============> lsb

8254 Timers Address 3

Register Access Key

1 – LED is on (can be used by software)

1 – Custom Product or P LD/ F PGA

FPGA Register Descriptions

R/W Read/Write

RO Read-only (status or reserved)

R/WC Read-status/Write-1-to-Clear
RSVD Reserved. Only write 0 to this bit; ignore all read values.

Product Information Registers

This register drives the PLED on the paddleboard. It also provides read access to the product code.

Table 4: PCR – Product Code and LED Register

Bit Identifier Access Default Description

7 PLED R/W 0

FPGA Registers

Drives the programm abl e LED on the paddleboard.
0 – LED is off (default)

6-0 PRODUCT_CODE

RO

0010101 P roduct Code for the EPMe-42 (0x15)

Table 5: PSR – Product Status Register

Bit Identifier Access Default Description

7:3 REV_LEVEL[4:0]

2 EXTEMP

1 CUSTOM

0 BETA

RO

RO

RO

RO

N/A

N/A

N/A

N/A

Revision level of the PLD (incremented every FPGA release)

Extended or Standard Temp Status (set via external resistor):
0 – Standard Temp
1 – Extended Temp (probably always set)
Custom or Standard Product Status
0 – Standard Product

Beta or Production Status
1 – Beta (or Debug)
0 – Production

Lion (VL-EPMe-42) Programmer’s Reference Manual 8

BIOS and Jumper Status Register

0 – Secondary BIOS selected

Note:

Note: See Table 7

1 – FPGA is in a working stat e (not rel eased)

2

N/A

Reserved. Writes are ignored; reads always return 0.

0

0

Reserved. Writes are ignored; reads always return 0.

EPMe-42 Hardware Reference Manual for more information regarding the configuration switches.

Table 6: SCR –Status/Control Register

Bit Identifier Access Default Description

Status of the external BIOS switch (jumper):

7

6

5

4

3

BIOS_JMP

BIOS_OR

BIOS_SEL

LED_DEBUG

WORKVER

RO

R/W

R/W

R/W

RO

N/A

0

0

0

N/A

1 – Primary BIOS sel ected

BIOS Switch (jumper) Override
0 – BIOS Select will f ol l ow the BI O S _JMP switch setting. (Note)
1 – BIOS Select will f ol l ow the BI O S _SEL register setting

See Table 7
BIOS Select (see B I O S _OR):
1 – Primary BIOS sel ected
0 – Backup BIOS s el ected

Debug LED (controls the yellow LED):
0 – LED is off and follows it s pri mary function (MSATA_DAS)
1 – LED is on (indicates FPGA is programmed by defaul t)
Status used to indic at e that the FPGA is not off i cially released

and is still in a working st at e.
0 – FPGA is released

FPGA Registers

RESERVED RO

Status of the GPI Jumper (switch):

GPI_JMP

1

RESERVED RO

Note: This corresponds to the setting of position 6 of the SW1 Configuration Switch block. Refer to the

RO

N/A

0 – Switch is Off
1 – Switch is On

The table below summar izes the modes related to BIOS_OR and BIOS_SEL and the BIOS Configuration
Switch 6. The external BIOS selection is determined by the combination of the FPGA BIOS selection
signals and the BIOS Configuration Switch. This allows the BIOS Configuration switch to still be used to
select the Secondary BIOS no matter what the internal FPGA settings are or when the FPGA is not
programmed (i.e., setting the BIOS Configuration to the “ON” position will always select the Secondary).

Lion (VL-EPMe-42) Programmer’s Reference Manual 9

BIOS (BIOS_SEL ignored)

‘1’

‘1’

“ON”

Secondary

Configuration Switch select s BIOS

‘1’

‘0’

“OFF”

Secondary

BIOS_SEL selects BIOS

‘1’

‘0’

“ON”

Secondary

Configuration Switch select s BIOS

Table 7: BIOS Selection

FPGA Registers

BIOS_OR

(Bit 6)

‘0’ ‘X’ (don’t care) “OFF” Primary Configuration Switch selects the

‘0’ ‘X’ (don’t care) “ON” Secondary Configuration Switch selects the

‘1’ ‘1’ “OFF” Primary BIOS_SEL selects BIOS

BIOS_SEL

(Bit 5)

BIOS

Configuration

Switch #6

Position

BIOS Selected Comments

BIOS (BIOS_SEL ignored)

Lion (VL-EPMe-42) Programmer’s Reference Manual 10

Timer Registers

111 – IRQ11

3

RESERVED

0

Reserved. Writes are ignored; reads always return 0.

1 – Interrupt enabled

1 – Interrupt enabled

The FPGA implements an 8 254-compatible timer/counter that includes three 16-bit timers.

Table 8: TICR – 8254 Timer Interrupt Control Register

Bit Identifier Access Default Description

8254 Timer interrupt enable/dis abl e:

7 IRQEN

6-4 IRQSEL(2:0)

R/W

R/W

0

000

0 – Interrupts disabled
1 – Interrupts enabled
8254 Timer interrupt IRQ s elect in LPC SERIRQ :
000 – IRQ3
001 – IRQ4
010 – IRQ5
011 – IRQ10
100 – IRQ6
101 – IRQ7
110 – IRQ9

FPGA Registers

2 IMSK_TC5

1 IMSK_TC4

0 IMSK_TC3

RO

R/W

R/W

R/W

8254 timer #5 interrupt mask:

0

0 – Interrupt disabled

8254 timer #4 interrupt mask:

0

0 – Interrupt disabled

8254 timer #3 interrupt mask:

0

0 – Interrupt disabled
1 – Interrupt enabled

Lion (VL-EPMe-42) Programmer’s Reference Manual 11

Debug/Test Only -- 8254 Timer I nterrupt Test (test m ode onl y):

to be set for this)

ICTC3, ICTC4 timer input s are ignored.

1 – asserted

3

RESERVED

0

Reserved. Writes are ignored; reads always return 0.

1 level

1 level

1 level

Table 9: TISR – 8254 Timer Interrupt Status Register

Bit Identifier Access Default Description

0 – No test interrupt

7 INTRTEST R/W 0

1 – If IRQEN is a 1 then an int errupt will assert in the selected
IRQ in the LPC SERIRQ st ream (no timer interrupt mask needs

FPGA Registers

TMRTEST

6

TMRIN4

5

TMRIN3

4

2 ISTAT_TC5

1 ISTAT_TC4

R/W 0 Debug/T est Only -- 8254 Timer Test Mode:

0 – Normal operation
1 – Timer test mode. In the mode the OCTC3, OCT C4 (and

OCTC5 is ever implemented) outputs are set to Hi-Z and the

R/W 0 Debug/T est Only -- 8254 Timer #4 test signal. When

R/W 0 Debug/T est Only -- 8254 Timer #3 test signal. When

RO

RW/C

RW/C

N/A

N/A

INTRTEST = 1 this si gnal i s used for the timer input control
instead of the external ICTC4 signal . When INTRTEST = 0 t hi s
is ignored.

0 – deasserted
1 – asserted

INTRTEST = 1 this si gnal i s used for the timer input control
instead of the external ICTC3 signal . When INTRTEST = 0 t hi s
is ignored.

0 – deasserted

Status for the 8254 Timer #5 output (terminal count) i nt errupt
when read. This bit is read-status and a write-1-to-clear.

0 – Timer output (term i nal count) has not transitioned f rom 0 to
a 1 level

1 – Timer output (term i nal count) has transitioned from a 0 to a

Status for the 8254 Timer #4 output (terminal count) i nt errupt
when read. This bit is read-status and a write-1-to-clear.

0 – Timer output (terminal count) has not transitioned from 0 to
a 1 level

1 – Timer output (term i nal count) has transitioned from a 0 to a

0 ISTAT_TC3

Lion (VL-EPMe-42) Programmer’s Reference Manual 12

RW/C

N/A

Status for the 8254 Timer #3 output (terminal count) i nt errupt
when read. This bit is read-status and a write-1-to-clear.

0 – Timer output (term i nal count) has not transitioned f rom 0 to
a 1 level

1 – Timer output (term i nal count) has transitioned from a 0 to a

Table 10: TCR – 8254 Timer Control Register

clocking.

clocking.

Timer #5 is always on internal cl ock if configured as a 16-bit c l ock

registers (e.g., OCTC4 with TMR4GATE ) for continuity testing.

0

Reserved

R/W

0

Reserved. Writes are i gnored; reads always return 0.

Bit Identifier Access Default Description

Controls the “gate” signal on 8254 timer #5 when not using an external
gate signal:

7 TMR5GATE

6 TMR4GATE

5 TMR3GATE

R/W

R/W

R/W

0 – Gate on signal GCTC5 is disabl ed

0

1 – Gate on signal GCTC5 is enabled
Always set to 0 when configuring timer modes. Set to a ‘1’ if using

external clocking. It can be turned on and off when using internal

Controls the “gate” signal on 8254 timer #4 when not using an external
gate signal:

0 – Gate on signal GCTC4 is disabl ed

0

1 – Gate on signal GCTC4 is enabled
Always set to 0 when configuring timer modes. Set to a ‘1’ i f using

external clocking. It can be turned on and off when using internal
clocking.

Controls the “gate” signal on 8254 timer #3 when not using an external
gate signal:

0 – Gate on signal GCTC3 is disabl ed

0

1 – Gate on signal GCTC3 is enabled
Always set to 0 when configuring timer modes. Set to a ‘1’ i f using

external clocking. It can be turned on and off when using internal

FPGA Registers

4 TM45MODE

3 TM4CLKSEL

2 TM3CLKSEL

1 TMROCTST R/W 0

R/W

R/W

R/W

Mode to set timers #4 and #5 i n:
0 – Timer #4 and #5 form one 32-bit timer controlled by timer #1 signals

1 – Timer #4 and Timer #5 are separate 16-bit timers with their own

0

control signals.
Almost always used in 32-bit mode especially when TMRFULL is a ‘0’

(the 16-bit timer #5 if of l i mited use)
Timer #4 Clock Selec t :
0 – Use internal 4.125 MHz clock (derived f rom PCI clock)

0

1 – Use external ICTC4

Timer #3 Clock Selec t :

0

0 – Use internal 4.125 MHz clock (derived f rom PCI clock)
1 – Use external ICTC3 assigned to Digital I/O

Debug/Test Only: Used to derive OCTCx outputs with T I MxGATE
signals for continuit y t esting only:

0 – Normal operation
1 – Drive OCTCx outputs with corresponding TMRxGATE control

Lion (VL-EPMe-42) Programmer’s Reference Manual 13

FPGA Registers

SPI clock polarity – Sets the SCLK idle state.

1 – SCLK idles high

11 – 32-bit

111 – Undefined (ignored)

SPI Control Registers

These are placed at the traditional offset 0x8 location. Only external SPX interface devices use this
interface. Because the board uses a 9-pin SPX connector, only two devices are supported.

SPICONTROL

Table 11: SPI Interface Control Register

Bit Identifier Access Default Description

7 CPOL

6 CPHA

5-4

SPILEN(1:0)

3 MAN_SS

2-0 SS(2:0)

R/W 0

R/W 0

R/W 00

R/W 0

R/W 000

0 – SCLK idles low

SPI clock phase – Sets the SCLK edge on which valid data will be read.
0 – Data is read on rising edge

1 – Data is read on falling edge
Determines the SPI frame length. This sel ection works in manual and

auto slave select m odes.
00 – 8-bit

01 – 16-bit
10 – 24-bit

Determines whether the slave select lines are asserted through the
user software or are automatical l y as serted by a write to SPIDATA3.

0 - The slave select operates aut omatically
1 - The slave select line is controlled manually through SPICONTROL
bits SS[2:0]

SPI slave device selec t i on:
000 – None

001 – SS0#
010 – SS1#
011 – Undefined (ignored)
100 – Undefined (ignored)
101 – Undefined (ignored)
110 – Undefined (ignored)

Lion (VL-EPMe-42) Programmer’s Reference Manual 14

FPGA Registers

11 – 6 Mhz (24Mhz /4)

1 - Data is right-shifted (LS B first)

when the external hardware interrupt is no longer present.

is, busy)

SPISTATUS

The SPX interrupt is not connected on t hi s product. T he control bits and status associated are still defined in
the register set but the SPX interrupt will always be de-asserted.

Table 12: SPI Interface Status Register

Bits Identifier Access Default Description

Select which IRQ will be enabled if HW_IRQ_EN = 1, interrupts
are not used on this board so this j ust becomes a read/write non­functional field.

00 – IRQ3

7-6 IRQSEL[1:0] R/W 00

5-4 SPICLK[1:0] R/W 00

01 – IRQ4
10 – IRQ5
11 – IRQ10
Note: These are the first 4 i nt errupts in the “usual” LPC SERIRQ

group of 8 interrupts.
Select one of four SCLK frequencies. This is based on a 24Mhz

LPC clock.
00 – 0.75 Mhz (24Mhz /32)
01 – 1.5 Mhz (24Mhz /16)
10 – 3 Mhz (24Mhz /8)

3 HW_IRQ_EN R/W 0

2 LSBIT_1ST R/W 0

1 HW_INT RO 0

0 BUSY

RO

N/A

This enables the select ed IRQ to be activated by a SPI device
that is configured to use interrupt capability. SPX I/F interrupts
are not supported on this product.

0 - IRQ’s are disabled for SPI operations.
1 - the IRQ can be asserted
Controls the SPI shif t direction from the SPIDATA(x) registers.
0 - Data is left-shifted (MSB first).

Status flag which indicat es when the hardware SPX signal SINT#
is asserted. SPX I/F i nt errupts are not supported on this product
so this always returns a 0

0 - the hardware interrupt SINT# is de-asserted.
1 - an interrupt is present on SI NT #
If HW_IRQ_EN= 1, then the selected IRQ will als o be asserted

by the hardware interrupt. HW_INT i s read-only and is cleared

Status flag which indicat es when an SPI transaction is underway.

2

I

C is so slow that there is no reas on t o ever poll this.
0 - The SPI bus is idle.
1 - SCLK is clocki ng data in/out of the SPIDATA(x) registers (that

Lion (VL-EPMe-42) Programmer’s Reference Manual 15

FPGA Registers

D7

D6

D5

D4

D3

D2

D1

D0

SPI Data Registers

There are four data registers used on the SPI interface. How many are used depends on the device being
communicated with. SPIDATA0 is typically the least significant byte a nd SPIDATA3 is the most
significant byte. Any write to the most significant byte SPIDATA3 initiates the SCLK and, dep ending on
the MAN_SS state, will assert a slave select to begin an SPI bus transaction.

Data is sent according to the LSBIT_1ST setting. When LSBIT_1ST = 0, the MSbit of SPIDATA3 is sent
first and received data will be shifted in the LSbit of the selected frame size determined by SPILEN1 and
SPILEN0. When LSBIT_1ST = 1, the LSbit of the selected frame size is sent first and the received data will
be shifted in the MSbit of SPIDATA3.

SPIDATA0 (Least Significant Byte)

MSB LSB

SPIDATA1

D7 D6 D5 D4 D3 D2 D1 D0

MSB LSB

SPIDATA2

D7 D6 D5 D4 D3 D2 D1 D0

MSB LSB

SPIDATA3 (Most Significant Byte) [Cycle Trigger Register]

D7 D6 D5 D4 D3 D2 D1 D0

MSB LSB

Lion (VL-EPMe-42) Programmer’s Reference Manual 16

FPGA Registers

mSATA/PCIe Mux selection for Minicard slot (and 2nd SATA connector):

to the SATA connector.

3

Reserved

0

Reserved. Writes are ignored; reads always return 0.

using IRQ3).

Debug/Test Only: Used to loop SPI output data back to the i nput (debug/test

1 – Loop SPI output data back to the SPI input data (data output still active)

SPI Debug Control Register and mSATA/PCIe Select Control Register

This register is only used to set an SPI loopback (de bug/test only) but is also used for the mSATA/PCIe
Minicard Mux select.

Table 13: SPI – SPI Debug Control Register

Bit

Identifier Access Default

7

Reserved

6-4 MUXSEL(2:0)

RO

R/W

Description

0 Reserved. Writes are ignored; reads always return 0.

• 000 – Select mSATA using only pin 43 (MSATA_DETECT). This is an
Intel-mode that is reli abl e for PCIe Minicards but not for mSATA modules
that inadvertently ground this si gnal .

• 001 – Use only Pin 51 (PRES_DISABLE2#). This is the default method
and is defined in the Draft m S ATA spec but some Minicards use it as a
second wireless disable.

• 010 – Use either Pin 43 or Pin 51. This will work just l i ke 001 because Pin

000

43 is disabled by an FPGA pull-down.

• 011 – Force PCIe mode on the Minicard

• 100 – Force mSATA m ode on the Minicard.

• 101 – Undefined (same as 000)

• 110 – Undefined (same as 000)

• 111 – Undefined (same as 000)

Note: When the Mini card uses PCIe, the SATA channel automatically switches

RO

When an IRQ is as signed a slot in the SERIRQ, i t will drive the slot with the
interrupt state, but t hi s bi t must be set to a ‘1’ t o do that.

0 – Slots assigned to SERIRQ are not driven (available for other devices).

2

SERIRQEN

1 SPILB

0

RESERVED

R/W

R/W

RO

1 – Slots assigned to SERIRQ are driven with their current interrupt state (which

0

is low since interrupts are high-true).
This is because the defaul t interrupt settings in t hi s FPGA can conflict with

other interrupts if the Vers aAPI is not being used (for example, console redirect

mode).

0

0 – Normal operation

0 Reserved. Writes are ignored; reads always return 0.

Lion (VL-EPMe-42) Programmer’s Reference Manual 17

FPGA Registers

7-2

Reserved

000000

Reserved. Writes are ignored; reads always return 0.

AUX GPIO Bank I/O Power Enable

AUX_PSEN

power control signal and the inverse of MINI_PSDIS.

Miscellaneous FPGA Registers

MISCR1 – Miscellaneous Control Register #1

This is a register in the always-on power well of the FPGA. It holds its state during sleep modes and can
only be reset by a power cycle. This is a placeholder register for features like pushing the power-button and
also for software initiated resets should those be needed. This register is only reset by the main power-on
reset since it must maintain its state in Sleep modes (for example, S3).

Table 14: MISCR1 – Misc. Control Register #1

Bits Identifier Access Default Description

RO

0 – The AUX GPIO bank will be powered down in sleep modes (only
power in S0)
1 – The AUX GPIO bank will not be powered down in sleep modes and

1 AUX_PSEN

0 MINI_PSDIS

R/W

R/W

the configuration will remain.

0

The GPIO bank power switch is controlled by the “OR” of the S0 power
control signal and FPGA_PSEN.

Note: Some register res et s are conditional on the state of

Minicard 3.3 V power disable
0 – Minicard 3.3 V power stays on always (this is normally how

minicards operate if they support any Wake events )

0

1 – Minicard 3.3 V power will be turned off when not in S0 (in sleep
modes).

The Minicard 3.3 V power switch is control l ed by t he “OR” of the S0

MISCR2 – Miscellaneous Control Register #2

This is a register in the always-on power well of the FPGA. It holds its state during sleep mo des and can
only be reset by a power cycle. It is primarily used for control signals for the always-power ed Ethernet
controllers and the USB hubs. This register is only reset by the main power-on reset since it must maintain
its state in sleep modes (for example, S3).

Lion (VL-EPMe-42) Programmer’s Reference Manual 18

Table 15: MISCSR2 – Misc. Control Register #2

7

RESERVED

0’s

Reserved – Writes are i gnored. Reads always return 0

this signal and if enabled the control becomes the “OR” of al l sources

1 – Ethernet controller is di s abl ed (O f f)

1 – Ethernet Phy controller is di sabled (Off)

2

RESERVED

0’s

Reserved – Writes are i gnored. Reads always return 0

1

RESERVED

0’s

Reserved – Writes are i gnored. Reads always return 0

7-4

Reserved

0

Reserved. Writes are ignored; reads always return 0.

3

Reserved

0

Reserved. Writes are i gnored; reads always return 0.

“write-only”.

Bit

Identifier

6 W_DISABLE

5 ETHOFF1

4 ETHOFF0

Access Default

RO

R/W

R/W

R/W

0

0

0

Description

Used to control the W_DISABLE (Wireless Disable) signal goi ng t o the
PCIe Mincard:

0 – W_DISAB LE signal is not asserted (E nabl ed)
1 – W_DISAB LE signal is asserted (Dis abl ed)

Note: There are other control sourc es that can be configured to control

Used to disable the Ethernet controller #1 (controls the ETH_OF F #
input to the I210-IT):

0 – Ethernet controller is enabl ed (On)

Used to disable the Ethernet controller #0 (controls the ETH_OF F #
input to the I219 Ethernet PHY ):

0 – Ethernet Phy controller is enabled (On)

FPGA Registers

3 RESERVED

0 RESERVED

RO
RO
RO
RO

0’s Reserved – Wri t es are ignored. Reads always return 0

0’s Reserved – Wri t es are ignored. Reads always return 0

MISCR3 – Miscellaneous Control Register #3

This register sets the SMBus addresses on the 4 -P ort PCIe Switch.

Table 16: MISCR3 – Misc. Control Register #3

Bits Identifier Access Default Description

RO
RO

When written to, thi s will do the same thing as pushi ng the reset
button, which could be useful f or a s oftware-initiated watchdog.

2 PBRESET

1-0 Reserved

R/W

RO

---

0 – No action
1 – Activate the reset push-button

Note: Because this generat es a reset that will reset this register, it
isn’t likely a value of a ‘1’ can ever be read-back, so it is somewhat

0 Reserved. Writes are ignored; reads always return 0.

Lion (VL-EPMe-42) Programmer’s Reference Manual 19

FPGA Registers

1 – Output

edge used.

1 – Asserts the output (1 i f polarity not-inverted, 0 if inverted)

AUXDIR – AUX GPIO Direction Control Register

This register controls the direction of the eight AUX GPIO signals.
This reset depends on the state of the FPGA_PSEN signal. If FPGA_PSEN is a ‘0’ then the reset is the

power-on and Platform Reset. If FPGA_PSEN is a ‘1’ then this register is only reset at power-on.

Table 17: AUXDIR – AUX GPIO Direction Control Register

Bit Identifier Access Default Description

Sets the direction of the AUX GPIOx lines. For each bit:

7-0 DIR_GPIO[8:1]

R/W

0

0 – Input

AUXPOL – AUX GPIO Polarity Control Register

This register controls the polarity of the eight AUX GPIO signals.
This reset depends on the state of the FPGA_PSEN signal. If FPGA_PSEN is a ‘0’ then the reset is the

power-on and Platform Reset. I f FPGA_PSEN is a ‘1’ then this register is only reset at power-on.

Table 18: AUXPOL – AUX GPIO Polarity Control Register

Bits Identifier Access Default Description

Sets the polarity of the A UX GPIOx lines . F or each bit:
0 – No inversion

7-0 POL_GPIO[8:1]

R/W

0

1 – Invert

Note: This impac ts the polarity as well as the interrupt status

AUXOUT – AUX GPIO Output Control Register

This register sets the AUX GPIO output value. This value will only set the actual output if the GPIO
direction is set as an output. Reading thi s register does not return the actual input value of the GPIO (us e the
AUXIN register for that). As such, this register can actually be used to detect input/output conflicts.

This reset depends on the state of the FPGA_PSEN signal. I f FPGA_PSEN is a ‘0’ then the reset is the
power-on and Platform Reset. If FPGA_PSEN is a ‘1’ then this register is only reset at power-on.

Table 19: AUXOUT – AUX GPIO Output Control Register

Bits Identifier Access Default Description

Sets the AUX GPIOx output values. For eac h bi t :

7-0 OUT_GPIO[8:1]

R/W

0 – De-asserts the output (0 if polarity not-inverted, 1 if i nvert ed)

0

Lion (VL-EPMe-42) Programmer’s Reference Manual 20

FPGA Registers

1 – Interrupt enabled

AUXIN – AUX GPIO I/O Input Status Register

This registers sets the AUX GPIO input va lue. It will read the input value regardless of the setting on the
direction (that is, it always reads the input). This reads the actual state of the GPIO pin into the part.

Table 20: AUXIN – AUX GPIO Input Status Register

Bits Identifier Access Default Description

Reads the GPIOx input status. For each bit:

7-0 IN_GPIOIO[8:1]

RO

N/A

0 – Input de-asserted if polarit y not -inverted;
assert ed i f polarity inverted

1 Input asserted if polarit y not-inverted;
de-assert ed i f pol ari ty inverted

AUXIMASK – AUX GPIO Interrupt Mask Register

This is the interrupt mask registers for the AUX GPIOs and the interrupt enable selection. The reset type is
Platform Reset because interrupts always have to be setup after exiting sleep states.

Table 21: AUXICR – AUX GPIO Interrupt Mask Register

Bits Identifier Access Default Description

GPIOx interrupt mask. For each bit:

7-0

IMASK_GPIO[8:1]

R/W

0

0 – Interrupt disabled

AUXISTAT – AUX GPIO I/O Interrupt Status Registe r

Table 22: AUXISTAT – AUX GPIO Interrupt Status Register

Bits Identifier Access Default Description

GPIOx interrupt status. A read returns t he i nterrupt status. Writing

7-0

ISTAT_GPIO[8:1]

RW/C

N/A

a ‘1’ clears the interrupt s tatus.
This bit is set t o a ‘ 1’ on a t ransition from low-to-high

(POL_DIOx=0) or high-to-low (POL_DIOx=1).

Lion (VL-EPMe-42) Programmer’s Reference Manual 21

FPGA Registers

1 – ICTC3 (input)

1 – ICTC4 (input)

1 – OCTC4 (output)

1 – WDOG_RESET # (Output)

1 – WAKE# (I nput)

1 – W_DISAB LE# (Input)

AUXMODE1– AUX I/O Mode Register #1

These two registers selected the mode on each AUX GPIO. T his reset depends on the state of the
FPGA_PSEN signal. If FPGA_PSEN is a ‘0’ then the reset is the power-on and Platform Reset. If
FPGA_PSEN is a ‘1’ then this register is only reset at power-on.

Table 23: AUXMODE1 – AUX I/O Mode Register

Bit Identifier Access Default Description

GPIO 8 Mode:

7 MODE_GPIO8

6 MODE_GPIO7

5 MODE_GPIO6

4 MODE_GPIO5

R/W

R/W

R/W

R/W

0

0 – GPIO (I/O)

GPIO 7 Mode:

0

0 – GPIO (I/O)

GPIO 6 Mode:

0

0 – GPIO (I/O)
1 – OCTC3 (output)
GPIO 5 Mode:

0

0 – GPIO (I/O)

3 MODE_GPIO4

2 MODE_GPIO3

1 MODE_GPIO2

0 MODE_GPIO1

R/W

R/W

R/W

R/W

0

0

0

0

GPIO 4 Mode:
0 – GPIO (I/O)

GPIO 3 Mode:
0 – GPIO (I/O)

GPIO 2 Mode:
0 – GPIO (I/O)

GPIO 1 Mode:
0 – GPIO (I/O)
1 – PWM (output)

Lion (VL-EPMe-42) Programmer’s Reference Manual 22

WDT_CTL – Watchdog Control Register

1 – Interrupts enabled

111 – IRQ11

3

Reserved

0

Reserved. Writes are ignored; reads always return 0.

Note: The WDT_V AL register must be set before enabling.

Reset type is Platform.

Table 24: WDT_CTL – Watchdog Control Register

Bits Identifier Access Default Description

Watchdog int errupt enable/disable:

7 IRQEN

6-4 IRQSEL(2:0)

R/W

R/W

0

000

0 – Interrupts disabled

Watchdog int errupt IRQ select in LPC SERI RQ:
000 – IRQ3
001 – IRQ4
010 – IRQ5
011 – IRQ10
100 – IRQ6
101 – IRQ7
110 – IRQ9

FPGA Registers

2 RESET_EN

1 WDT_EN

0 WDT_STAT

RO

R/W

R/W

RO

Enable the Watchdog to assert the push-button res et if it “fires”.

0

0 – Watchdog will not reset the board
1 – Board will be reset if the Watchdog “fires”
Watchdog Enable:
0 – Watchdog is disabled

0

1 – Watchdog is enabled

Watchdog St at us:
0 – Watchdog disabled or watchdog has not “fired”
1 – Watchdog f i red.
Note: Once set to a ‘1’ , it will remain so until any of the following

0

occurs:

• the WDT_VAL register is written to

• the WDT_EN is disabled

• a reset occurs

Lion (VL-EPMe-42) Programmer’s Reference Manual 23

FPGA Registers

7-4

Reserved

0000

Reserved. Writes are ignored; reads always return 0.

3-2

Reserved

00

Reserved. Writes are ignored; reads always return 0.

1 – RS422/485

WDT_VAL – Watchdog Value Register

This register sets the number of seconds for a Watchdog prior to enabling the watchdog. By writing this
value, the watchdog can be prevented from “firing”. A watchdog fires whenever this registers value is all 0s,
so it must be set to a non-zero value before enabling the watchdog to prevent an immediate “firing”. Reset
type is Platform.

The value written should always be 1 greater than the desired timeout value due to a 0-1 second “tick” error
band (values writ ten should range from 2-255 because a 1 could cause an immed iate trigger); that is, the
actual timeout is WDT_VAL seconds with a -1 second to 0 second error band.

Table 25: WDT_VAL – Watchdog Control Register

Bits Identifier Access Default Description

7-0 WDT_VAL(7:0)

R/W

0x00

Number of seconds before the Watchdog fires . By default, it is
set to zero which results in an immediate watchdog if WDT_EN is
set to a ‘1’.

XCVRMODE – COM Transceiver Mode Register

Sets the RS232 vs RS422/485 mode on the COM port Transceivers. These drive the UART_ S EL signals
from the FPGA to the Transceivers.

Reset type is Platform.

Note: The values shown are for the default BIOS configuration.

Table 26: XCVRMODE – COM Transceiver Mode Register

Bits Identifier Access Default Description

RO
RO

COM2 Transceiver mode:

1 COM2_MODE

0 COM1_MODE

R/W

R/W

0

0 – RS232
1 – RS422/485
COM1 Transceiver mode:

0

0 – RS232

Lion (VL-EPMe-42) Programmer’s Reference Manual 24

AUXMODE2– AUX I/O Mode Register #2

1 – Interrupts enabled

111 – IRQ11

3-0

Reserved

0000

Reserved. Writes are ignored; reads always return 0.

1 – Fan is off

This registe r defines the interrupt mapping for the AUX GPIOs. Reset type is Platform.

Table 27: AUXMODE2 - AUX I/O Mode Register #2

Bits Identifier Access Default Description

AUX GPIO interrupt enable/disable:

7 IRQEN

6-4 IRQSEL(2:0)

R/W

R/W

0

000

0 – Interrupts disabled

AUX GPIO interrupt IRQ select in LPC SERIRQ:
000 – IRQ3
001 – IRQ4
010 – IRQ5
011 – IRQ10
100 – IRQ6
101 – IRQ7
110 – IRQ9

FPGA Registers

RO

FANCON – Fan Control Reg ister

The fan is always off in any sleep mode. When the processor comes out of a sleep state, this register must
be setup again since it will be reset to default by the platform reset signal. The fan is always turned “off” in
sleep modes. No PWM fan control is supported on the EPMe-42.

Reset type is Platform.

Note: The BIOS (via ACPI) may modify this register when in an ACPI-capable operating system. The

register can be read for status purposes but do not write to it unless you are using a non-ACPI operating
system.

Table 28: FANCON – Fan Control Register

Bits Identifier Access Default Description

7-1 Reserved

0 FAN_OFF

RO

R/W

0000000 Reserved. Writes are ignored; reads always return 0.

Fan enable:

0

0 – Fan is on

Lion (VL-EPMe-42) Programmer’s Reference Manual 25

FPGA Registers

Read this register after reading FA NT A CHLS .



The FANTACHLS register must be read first. It will latch a copy of the MS bits so that when
on the LPC bus reads the even (LS) address before the odd (MS) address.

FANTACHLS, FANTACHMS – Fan Tach Status Registers

These registers contain the number of fan tach output samples over a one-second sampling period. The
value is always valid after the fan speed stabilizes and is updated every 1 second (after a delay of 1 second).
Currently, only the lower 10-bits have a valid tach reading (that is, the upper 6 bits will always be zero).
The fan tach count should never overflow in the one second period, but it if does, the value will “stick” at
0x03FF.

The board can handle up at least a 10,000 RPM fan with a fan tach o utput of up to four uniform pulses per
revolution. The duty cycle of the fan tach output pulse can be as low as 25% (typically they are very close
to 50%). The conversion to RPM is as follows:

RPM = (FANTACH x 60) / PPR

Where…

 FANTACH - the 16-bit register reading
 PPR – fan tach pulses per revolution (typically either 1, 2, or 4)

Reset type is n/a.

Table 29: FANTACHLS – FANTACH Status Register Least Significant Bits

Bits Identifier Access Default Description

Least significant ei ght bits of FANTACH.

7-0 FANTACH[7:0]

RO

N/A

Read this register first since it latches the val ue f or the most
significant eight bits.

Table 30: FANTACHMS – FANTACH Status Register Most Significant Bits

Bits Identifier Access Default Description

7-0 FANTACH[15:8]

RO

N/A

Most significant eight bi ts of FANTACH.

Integrator’s Note:

FANTACHMS is read, it is based on the same 16-bit value. This assumes that a 16-bit word read

Lion (VL-EPMe-42) Programmer’s Reference Manual 26

FPGA Registers

1 – Interrupts enabled

1 – Interrupt enabled.

1 – Interrupt enabled.

1 – Interrupt enabled.

1 – Interrupt enabled.

TEMPICR – Temperature Interrupt Control Register

This is the interrupt mask r egister for the temperature sensor thermal alerts and the DDR3 SODIMM
EVENT signals and the interrupt enable and selection. The SODIMM may not have any temperature event
capability.

Reset type is Platform.

Table 31: TEMPICR – Temperature Interrupt Control Register

Bits Identifier Access Default Description

7 IRQEN

6-4 IRQSEL(2:0)

3 IMASK_BATTLOW

R/W

R/W

R/W

000

Temperature interrupt enable/di sable:

0

0 – Interrupts disabled

Temperature interrupt IRQ s el ect in LPC SERIRQ:
000 – IRQ3

001 – IRQ4
010 – IRQ5
011 – IRQ10
100 – IRQ6
101 – IRQ7
110 – IRQ9
111 – IRQ11

Battery-low interrupt mask:

0

0 – Interrupt disabled

2 IMASK_EVENT

1 IMASK_THERM

0 IMASK_ALERT

R/W

R/W

R/W

SODIMM EVENT output interrupt mask:

0

0 – Interrupt disabled

Temperature Sensor THERM output i nterrupt mask:

0

0 – Interrupt disabled

Temperature Sensor ALERT output interrupt mask:

0

0 – Interrupt disabled

Lion (VL-EPMe-42) Programmer’s Reference Manual 27

1 – battery-low is asserted (battery is low)

transition from de-asserted-to-asserted

status. Writing a ‘1’ will clear the interrupt status

interrupt status. Writing a ‘1’ clears the interrupt status

TEMPISTAT – Temperature Interrupt Status Register

Reset type: n/a.

Table 32: TEMPISTAT – Temperature Interrupt Status Register

Bits Identifier Access Default Description

Reads the battery low input status.

7 IN_BATTLOW

RO

N/A

0 – battery-low is de-asserted (battery is OK)

FPGA Registers

6-4 Reserved

3

ISTAT_BATTLOW

2 ISTAT_EVENT

1 ISTAT_THERM

0 ISTAT_ALERT

RO

RW/C

RW/C

RW/C

RW/C

000 Reserved. Writes are ignored; reads al ways return 0.

N/A

N/A

N/A

N/A

Battery-Low interrupt status. A read returns the interrupt status .
Writing a ‘1’ c l ears the interrupt status. This bit is set to a ‘ 1’ on a

SODIMM EVENT interrupt stat us. A read returns the interrupt

Temperature Sensor THERM interrupt status. A read returns the
interrupt status. Writing a ‘1’ clears the interrupt status

Temperature Sensor ALERT i nterrupt status. A read returns t he

Lion (VL-EPMe-42) Programmer’s Reference Manual 28

FPGA Registers

1 – Interrupts enabled

1010-1111 – Reserved, do not use

UART1CR – UART1 Control Register (COM1)

Reset type is Platform.

The BIOS (via ACPI) may modify this register when in an ACPI-capable operating system. The

Note:

register can be read for status purposes but do not write to it unless you are using a non-ACPI operating
system.

Table 33: UART1CR – UART1 Control Register (COM1)

Bits Identifier Access Default Description

UART interrupt enable/disable:

7 IRQEN

6-4 IRQSEL(2:0)

3-0 UART1_BASE(3:0)

R/W

R/W

R/W

0

001

0000

0 – Interrupts disabled

UART Interrupt IRQ Select i n LP C S ERIRQ:
000 – IRQ3
001 – IRQ4 <= COM1 Default
010 – IRQ5
011 – IRQ10
100 – IRQ6
101 – IRQ7
110 – IRQ9
111 – IRQ11
UART Base Address:
0000 - 3F8h <= COM1 Default
0001 - 2F8h
0010 - 220h
0011 - 228h
0100 - 238h
0101 - 2E8h
0110 - 338h
0111 - 3E8h
1000 - 200h (requires using LPC generic I/O) Reserved to

Customer
1001 - 208h (requires using LPC generic I/O) Reserved to

Customer

Lion (VL-EPMe-42) Programmer’s Reference Manual 29

FPGA Registers

1 – Interrupts enabled

1010-1111  These values are reserved; do no t u se.

UART2CR – UART2 Control Register (COM2)

Reset type is Platform.

The BIOS (via ACPI) may modify this register when in an ACPI-capable operating system. The

Note:

register can be read for status purposes but do not write to it unless you are using a non-ACPI operating
system.

Table 34: UART2CR – UART2 Control Register (COM2)

Bits Identifier Access Default Description

UART interrupt enable/disabl e:

7 IRQEN

6-4 IRQSEL(2:0)

3-0 UART2_BASE(3:0)

R/W

R/W

R/W

0

000

0001

0 – Interrupts disabled

UART interrupt IRQ selec t in LPC SERIRQ:
000 – IRQ3 [ COM2 Default]
001 – IRQ4
010 – IRQ5
011 – IRQ10
100 – IRQ6
101 – IRQ7
110 – IRQ9
111 – IRQ11
UART Base Address:
0000 - 3F8h
0001 - 2F8h <= COM2 Default
0010 - 220h
0011 - 228h
0100 - 238h
0101 - 2E8h
0110 - 338h
0111 - 3E8h
1000 - 200h (requires using LPC generic I/O) Reserved to

Customer
1001 - 208h (requires using LPC generic I/O) Reserved to

Customer

Lion (VL-EPMe-42) Programmer’s Reference Manual 30

FPGA Registers

7-6

Reserved

00

Reserved. Writes are ignored; reads always return 0.

XCVRMODE register must also be set to a ’1’

3-2

Reserved

00

Reserved. Writes are ignored; reads always return 0.

1 – Tx and RTS outputs are enabled

1 – Tx and RTS outputs are enabled

UARTMODE1 – UART MODE REGISTER #1

When the COM Transceiver Mode is set to RS422/485 (in the XCVRMODE register) and the RS-485
Automatic Direction Control is enabled (e.g., UART1_48 5ADC set to ‘1’) then the transceiver Tx output is
enabled. When there are bytes to transmit and the transceiver Tx output is disabled (i.e., tri-stated) when
there are no bytes to transmit.

When the COM Transceiver Mode is set to RS422 /485 and Automatic Direction Control is disabled (e.g.,
UART1_485ADC set to ‘0’) then the UART is in Manual Direction Control mode and the transceiver Tx
output enable is controlled by software using the RTS bit in the UART Modem Control Register.

RTS = '0' - Transceiver Tx output is enabled.
RTS = '1' - Transceiver Tx output is disabled (i.e., tri-stated).
Warning: Terminal software, expecting an RS-232 port, may set RTS to '1' and disable the transmitter

when initializing an RS-422/485 port in Manual Direction Control mode. Application software that handles
the RS-422/485 po r t should set RTS to '0' to enable transmitting when in Manual Direction Control mode.

Reset type is Platform.

The values shown are for the default BIOS configuration.

Note:

Table 35: UARTMODE1 – UART MODE Register #1

Bits Identifier Access Default Description

RO

COM2 RS-485 Automatic Direc tion Control:
0 – Disabled

5 UART2_485ADC

4 UART1_485ADC

1 UART2_EN

0 UART1_EN

R/W

R/W

RO

R/W

R/W

0

1 – Enabled
Note: Only enable in RS-485 mode. The COM2_MODE in

XCVRMODE register must also be set to a ’1’
COM1 RS-485 Automatic Direc tion Control:
0 – Disabled

0

1 – Enabled
Note: Only enable in RS-485 mode. The COM1_MODE in

UART #2 Output Enable:
0 – Tx and RTS outputs are disabled and UART I/ O accesses

1

are ignored.

UART #1 Output Enable:
0 – Tx and RTS outputs are disabled and UART I/ O accesses

1

are ignored

When a UART is disabled, there will be no decoding of the UART I/O address range and any I/O

Note:

activity will be passed to the ISA bus (this allows COM ports to be on the ISA bus if the FPGA UARTs are
not used). This means that the UART must be enabled before accessing registers. If this is an issue,
separate control bits can be added in UARTMODE2 or make one of the unused UART Base addresses a
no-decode.

Lion (VL-EPMe-42) Programmer’s Reference Manual 31

FPGA Registers

Note: This must be set to ‘1’ to use baud rates above 115,200.

UARTMODE2 – UART MODE REGISTER #2

Standard software (the BIOS and the operating system) assumes the baud-rate clock is 1.8432 MHz and
programs the divisors accordingly; however, a faster oscillator is needed for baud rates higher than 115,200.

The FAST_MODE bit in this register is used to shift the divisor b y 4 bits (multiply by 16) so that the legacy
baud rate comes out correctly for the 16x UART clo ck. T his bit must be set to use rates above 115,200 and
may require custom software.

Reset type is Platform.

The values shown are for the default BIOS configuration.

Note:

Table 36: UARTMODE2 – UART MODE Register #2

Bits Identifier Access Default Description

7-1 Reserved

0 FAST_MODE

RO

R/W

0000000 Reserved. Writes are i gnored; reads always return 0.

Sets how the baud-rate divisor for the 16550 UARTs are
interpreted (applies to all ports ):

0

0 – Divisor is multi pl i ed by 16 (legacy mode for 1.8432 MHz
clock)

1 – Divisor is not modified (fast mode for 16x 1.8432 MHz clock)

Lion (VL-EPMe-42) Programmer’s Reference Manual 32

4

Programming Information for Hardware

Processor WAKE# Capabilities

The following devices can wake up the processor using the PCIE_WAKE# signal to the SoC:

 Ethernet port 1 controller
 Minicard (when always-powered)
 FPGA via either a Digital I/O or AUX connector GPIO

The following nine USB devices can wake up the processor using the in-band SUSPEND
protocol:

 The 2 On-Board USB 3.0 Ports

Interfaces

 Any of the 4 CBR-4005 Paddleboard USB Ports
 Either of the 2 PCI104/Express “A” Connector (1-Blade) USB Ports
 Minicard (when always-powered)

Watchdog Timer

A Watchdog timer is implemented within the FPGA. When triggered, the Watchdog timer can set
a status bit, generate an interrupt and/or hit the push-button-reset. The Watchdog timer
implements a 1-255 second timeout.

The Watchdog time out is set in an 8-bit register (WDT_VAL). When the Watchdog is enabled,
the WDT_VAL will start to count down. If the Watchdog is enabled and whenever WDT_VAL
is zero, the Watchdog is triggered (so a non-zero value must be written before enabling the
watchdog). Software must periodically write a non-zero value to WDT_VAL to prevent this
trigger. The value written should always be 1 greater than the desired timeout value due to a 0-1
second error band. Values written should be from 2-255 because a 1 could cause an immediate
trigger); that is, the actual timeout is WDT_VAL seconds with a -1 second to 0 second error
band.

The Watchdog control/status register(s) have bits for the following:

 Watchdog enable/disable (disabled by default)
 Watchdog timeout status (This is cleared when the Watchdog is disabled or when a new

value is written to WDT_VAL. Writing WDT_VAL would be the interrupt-acknowledge.)

 Watchdog interrupt IRQ select (from the same list of eight interrupts supported on the LPC

SERIRQ)

 Interrupt enable
 Board reset enable (when set, the board will be reset when the Watchdog timer expires).

Lion (VL-EPMe-42) Programmer’s Reference Manual 33

Industrial I/O Functions and SPI Interface

The EPMe-42 employs a set of I/O registers for controlling external serial peripheral interface
(SPI) devices. Refer to the descriptions of the SPICONTROL (page 14), SPISTATUS (page 15),
and SPIDATA[0:3] (page 16) registers for more information.

The SPI bus specifies four logic signals:

 SCLK – Serial clock (output from master)
 MOSI – Master output, slave input (output from master)
 MISO – Master input, slave output (output from slave)
 SS – Slave select (output from master)

The EPMe-42 SPI implementation adds additional features, such as hardware interrupt input to
the master. The master initiates all SPI transactions. A slave device responds when its slave
select is asserted and it receives clock pulses from the master.

Slave selects are controlled in one of two modes: manual or automatic. In automatic mode, the
slave select is asserted by the SPI controller when the most significant data byte is written. This
initiates a transaction to the specified slave device. In manual mode, the slave select is controlled
by the user and any number of data frames can be sent. The user must command the slave select
high to complete the transaction.

Thermal Considerations

The SPI clock rate can be software configured to operate at speeds between 1 MHz and 8 MHz.
All four common SPI modes are supported through the use of clock polarity and clock phase
controls.

To initiate an SPI transaction, configure SPI registers SPICONTROL and SPISTATUS as shown
in Table 12 and Table 13 for the desired I/O device. For additional information on
communicating with specific SPI devices, refer to their respective manufacturer’s datasheets.

Programmable LED

User I/O connector J4 includes an output signal for attaching a software controlled LED.
Connect the cathode of the LED to J4, pin 16; connect the anode to +3.3 V. An on-board resistor
limits the current when the circuit is turned on. A programmable LED is provided on the
CBR-4005B paddleboard. Refer to the EPMe-42 Hardware Reference Manual for the location of
the Programmable LED on the CBR-4005B paddleboard.

To switch the PLED on and off, refer to Table 4: PCR – Product Code and LED Register, on

8.

page

*** End of document ***

Lion (VL-EPMe-42) Programmer’s Reference Manual 34