VersaLogic Lion VL-EPMe-42 Reference Manual

Lion

PCIe/104™ OneBank™ Inter face

Programmer’s Reference Manual

REV. May 2018

(VL-EPMe-42)

Intel® Core™-based Single Board Computer with Dual Ethernet, Video, USB, S A TA, Serial I/O, Digital I/O, Trust ed P latform Module security, Counter/Timers, Mini PCIe, mSATA, SPX, and

WWW.VERSALOGIC.COM

12100 SW Tualatin Road Tualatin, OR 97062-7341

(503) 747-2261

Fax (971) 224-4708

Notice:

Although every effort has been made to ensure this document is error-free, VersaLogic makes no representations or warranties with respect to this product and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose.

VersaLogic reserves the right to revise this product and associated documentation at any time without obligation to notify anyone of such changes.

Other names and brands may be claimed as the property of others.

Lion (VL-EPMe-42) Programmer’s Reference Manual ii

Product Release Notes

Release 1.3- Updated Uartmode1 – Uart Mode Register #1 section Release 1.2- Added descriptions to the FPGA table Release 1.1- Updated Processor Wake# section Release 1.0- Initial Production Draft

Support

The EPMe-42 support page contains additional information and resources for this product including:

 Reference Manual (PDF format)  Operating system information and software drivers  Data sheets and manufacturers’ links for chips used in this product  BIOS information and upgrades  Utility routines and benchmark software

The VersaTech KnowledgeBase is an invaluable resource for resolving technical issues with your VersaLogic product.

VersaTech KnowledgeBase

Lion (VL-EPMe-42) Programmer’s Reference Manual iii

Contents

Overview ........................................................................................................................ 1

Related Documents ............................................................................................................. 1

System Resources and Maps ....................................................................................... 2

Memory Map ...................................................................................................................... 2

Interrupts ............................................................................................................................. 2

FPGA Registers ............................................................................................................. 4

FPGA I/O Space ................................................................................................................. 4

FPGA Register Map ........................................................................................................... 5

FPGA Register Descriptions............................................................................................... 8

Product Information Registers ............................................................................... 8

BIOS and Jumper Status Register .......................................................................... 9

Timer Registers .................................................................................................... 11

SPI Control Registers .......................................................................................... 14

SPI Data Registers ............................................................................................... 16

SPI Debug Control Register and mSATA/PCIe Select Control Register ............ 17

Miscellaneous FPGA Registers ........................................................................... 18

Programming Information f or Hardware Interfaces .................................................. 33

Processor WAKE# Capabilities........................................................................................ 33

Watchdog Timer ............................................................................................................... 33

Industrial I/O Functions and SPI Interface ....................................................................... 34

Programmable LED .......................................................................................................... 34

Lion (VL-EPMe-42) Programmer’s Reference Manual iv

This document provides information for users requiring register-level information for develop ing applications as it relates the FPGA functionality with the VL-EPMe-42.

Related Documents

The following documents available are on the EPMe-42 Product Support Web Page:  EPMe-42 Hardware Reference Manual – provides information on the board’s hardware features

including connectors and all interfaces.

 EPMe-42 BIOS Reference Manual – provides information on acc essing and configuring s ettings in the

BIOS Setup utility. All BIOS menus, submenus, and configuration options ar e described.

This document is available through the software page:

VersaAPI Installation and Reference Guide – d escribes the shared library of API calls for reading



and contro l ling on-board devices on certain VersaLogic products.

Overview

Lion (VL-EPMe-42) Programmer’s Reference Manual 1

Memory Map

Table 1: Memory Map

00000h – 9FFFFh Legacy system (DOS) area A0000h – B7FFFh ISA memory area (VGA f rame buffer is not accessible) B8000h – BFFFFh Text mode buffer C0000h – CFFFFh Video BIOS area D0000h – DFFFFh PCI ROM expansion area E0000h – FFFFFh Legacy BIOS (reserved)

Interrupts

System Resources and Maps

Address Range Description

The LPC SERIRQ is used for interrupt interface to the Kaby Lake SoC. Each of the following devices can have an IRQ interrupt assigned to it and each with an interrupt enable

control for IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, IRQ9, IRQ10, and IRQ11:

 8254 timers (with three interrupt status bits)  8 AUX GPIOs (with one interrupt status bit)  COM 1 UART (with 16550 interrupt status bits)  COM 2 UART (with 16550 interrupt status bits)  Watchdog timer (one interrupt status bit)  SPX expansion interface (interrupt sta tus is determined by the devices on this interface). The interface

supports two interrupts.

 Thermal event and battery-low interrupts Note:

The EPMe-42 also has two COM ports (COM3, COM4) that are supported by the HSUARTs in the

processor.

The FPGA supports 11 interrupts via the LPC SERIRQ interface: IRQ3, IRQ4, IRQ5, IRQ 6, IRQ7, IRQ9, IRQ10, IRQ11, IRQ12, IRQ14, and IRQ15. There is an interrupt enable control for each and by default they are all disabled.

Common interrupts can be assigned to multiple devices (this is common on UARTs being handled by a common ISR).

Interrupt status bits for everything except the UARTs will “stick” and are cleared by a “write-one” to a status register bit. The 16550 UART interrupts behave as defined for the 16550 registers and are a passthrough to the LPC SERIRQ.

Per the VersaAPI standard, anytime an interrupt on the SERIRQ is enabled, the slot becomes active. All interrupts in t he SERIRQ are high-true so when the slot becomes active, the slot will be low when there is no interrupt and high when there is an interrupt.

Lion (VL-EPMe-42) Programmer’s Reference Manual 2

Table 2: I/O Map

I/O Address Range Device/Owner

2F8h – 2FFh COM2 serial port default 3B0h – 3DFh Legacy VGA registers 3F8h – 3FFh COM1 serial port default 400h – 47Fh ACPI / P ower m anagement (reserved) 500h – 5FFh PCH GPIO (reserved) C80h – CBBh EPMe-42 FPGA Board Control Registers CBCh – CBFh EPMe-42 FPGA 8254 Timer Registers

System Resources and Maps

Lion (VL-EPMe-42) Programmer’s Reference Manual 3

FPGA I/O Space

The FPGA is mapped into I/O space on the LPC bus. The address range is mapped into 64 byte I/O window.

 FPGA access: LPC I/O space  FPGA access size: All 8-bit byte accesses (16-bit like registers are aligned on 16-bit word boundaries

to make word access possible in software but the LPC bus still splits the accesses into two 8-bit accesses)

 FPGA address range: 0xC80 to 0xCBF (64-byte window) The three 8254 timers only require four bytes of addressing and are located at the end of the 64-byte I/O

block. The only requirement is that the base address must be aligned on a 4-byte block. Table 4 lists the FPGA’s I/O map.

FPGA Registers

Table 3: FPGA I/O Map

Address Range Device Size

0xC80 – 0xCBB FPGA registers 60 bytes 0xCBC – 0xCBF 8254 timer address regist ers 4 bytes

Lion (VL-EPMe-42) Programmer’s Reference Manual 4

FPGA Registers

Lion (VL-EPMe-42) Programmer’s Reference Manual 5

FPGA Register Map

Reset Status Key

R/W Read/Write POR Power-on reset (only resets one time when input power comes on)

RO Read-only (status or reserved) Platform

Resets prior to the processor entering the S0 power state (that is, at power-on and in sleep states)

R/WC Read-status/Write-1-to-Clear resetSX

• If AUX_PSEN is a '0' in MISCSR1 (default sett i ng), then this is the same as the Platform reset.

• If SUX_PSEN is a programmed to a '1', then i t is the same as the Power-On Reset (POR).

WO Write-Only n/a

• Reset doesn't apply to status or reserved regis ters

ROC Read-Only and clear-to-0 after readi ng

RSVD Reserved. Only write 0 to this bit; ignore all read values.

I/O

Address

Offset Reset D7 D6 D5 D4 D3 D2 D1 D0 Description

C80 0 Platform PLED PRODUCT_CODE

PCR - Product Code & PLED

C81 1 n/a REV_LEVEL EXTEMP CUSTOM BETA

PSR - Rev, Ext Tmp, Custom, Beta

C82 2 Platform BIOS_JMP BIOS_OR BIOS_SEL LED_DEBUG WORKVER 0 GPI_JMP 0

SCR - BIOS & Jumper status

C83 3 Platform IRQEN IRQSEL2 IRQSEL1 IRQSEL0 0 IMASK_TC5 IMASK_TC4 IMASK_TC3

TICR - Timer Interrupt Control Register

C84 4 Platform INTRTEST TMRTEST TMRIN4 TMRIN3 0 ISTAT_TC5 ISTAT_TC4 ISTAT_TC3

TISR - Interrupt Status Reg (& timer debug test)

C85 5 Platform TIM5GATE TIM4GATE TIM3GATE TM45MODE TM4CLKSEL TM3CLKSEL TMROCTST TMRFULL

TCR - Timer Control Reg (also see AUX GPIO Secondary Modes later)

C86 6 n/a 0 0 0 0 0 0 0 0

Reserved

C87 7 n/a 0 0 0 0 0 0 0 0

Reserved

C88 8 Platform CPOL CPHA SPILEN1 SPILEN0 MAN_SS SS2 SS1 SS0

SPICONTROL (traditional location for SPX regs)

C89 9 Platform IRQSEL1 IRQSEL0 SPICLK1 SPICLK0 HW_IRQ_EN LSBIT_1ST HW_INT BUSY

SPISTATUS

C8A A Platform msb <============> lsb

SPIDATA0 Least Significant Byte

C8B B Platform msb <============> lsb

SPIDATA1

FPGA Registers

Lion (VL-EPMe-42) Programmer’s Reference Manual 6

C8C C Platform msb <============> lsb

SPIDATA2

C8D D Platform msb <============> lsb

SPIDATA3 Most Significant Byte and Start SPI Cycle when written

C8E E Platform 0 MUXSEL2 MUXSEL1 MUXSEL0 0 SERIRQEN SPILB 0

SPIMISC - Custom SPI I/F controls, mSATA/PCIe Mux Select

C8F F n/a 0 0 0 0 0 0 0 0

Reserved

C90 10 POR 0 0 0 0 0 0 AUX_PSEN MINI_PSDIS

MISCSR1 - Power Control Regs

C91 11 POR 0 W _DISABLE ETH1_OFF ETH0_OFF 0 0 0 0

MISCSR2 - USB, Ethernet Control, misc.

C92 12 Platform 0 0 0 0 0 PBRESET 0 0

MISCSR3 - Misc Control Reg

C93 13 n/a 0 0 0 0 0 0 0 0

Reserved to align 16-bit regs on even byte boundaries

C94 14 n/a 0 0 0 0 0 0 0 0