Although every effort has been made to ensure this document is error-free, VersaLogic makes no
representations or warranties with respect to this product and specifically disclaims any implied warranties
of merchantability or fitness for any particular purpose.
VersaLogic reserves the right to revise this product and associated documentation at any time without
obligation to notify anyone of such changes.
* Other names and brands may be claimed as the property of others.
VL-EPU-4562/4462 Reference Manual ii
Page 3
Product Revision Notes
Revision 1.00 Initial release
Revision 1.01 Replaced block diagram
Revision 1.02 Updated Web links and WDT information
Revision 1.03 Updated Power Connector Pinout diagram (Figure 7)
Revision 1.04 Replaced Power Connector Pinout diagram (Figure 7)
Support Page
The Blackbird Support Page contains additional information and resources for this product
including:
Operating system information and software drivers
Data sheets and manufacturers links for chips used in this product
BIOS information and upgrades
VersaTech KnowledgeBase
The VersaTech KnowledgeBase contains useful technical information about VersaLogic
products, along with product advisories.
Customer Support
If you are unable to solve a problem after reading this manual, visiting the product support page,
or searching the KnowledgeBase, contact VersaLogic Technical Support at (503) 747-2261.
VersaLogic support engineers are also available via e-mail at Support@VersaLogic.com.
Repair Service
If your product requires service, you must obtain a Returned Material Authorization (RMA)
number by calling 503-747-2261. Be ready to provide the following information:
Your name, the name of your company, your phone number, and e-mail address
The name of a technician or engineer that can be contacted if any questions arise
The quantity of items being returned
The model and serial number (barcode) of each item
A detailed description of the problem
Steps you have taken to resolve or recreate the problem
The return shipping address
Warranty Repair All parts and labor charges are covered, including return shipping
Non-warranty Repair All approved non-warranty repairs are subject to diagnosis and labor
charges for UPS Ground delivery to United States addresses.
charges, parts charges and return shipping fees. Specify the shipping
method you prefer and provide a purchase order number for invoicing
the repair.
VL-EPU-4562/4462 Reference Manual iii
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Note:
Electrostatic discharge (ESD) can damage circuit boards, disk drives, and other
not slide the board over any surface.
After removing the board from its protective wrapper, place the board on a grounded,
static-free surface, component side up. Use an antistatic foam pad if available.
The board should also be protected inside a closed metallic antistatic envelope during
Avoid touching the exposed circuitry with your fingers when handling the board. Though
defaults.
All mounting standoffs should be connected to earth ground (chassis ground). This
provides proper grounding for EMI purposes.
Mark the RMA number clearly on the outside of the box before returning.
Cautions
Electrostatic Discharge
Note: The exterior coating on some metallic antistatic bags is sufficiently conductive to cause
excessive battery drain if the bag comes in contact with the bottom side of the Blackbird.
CAUTION:
components. The circuit board must only be handled at an ESD workstation. If an
approved station is not available, some measure of protection can be provided by
wearing a grounded antistatic wrist strap. Keep all plastic away from the board, and do
shipment or storage.
Handling Care
CAUTION:
it will not damage the circuitry, it is possible that small amounts of oil or perspiration on
the skin could have enough conductivity to cause the contents of CMOS RAM to
become corrupted through careless handling, resulting in CMOS resetting to factory
Earth Ground Requirement
CAUTION:
VL-EPU-4562/4462 Reference Manual iv
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Contents
Cautions ............................................................................................................................. iv
Electrostatic Discharge ......................................................................................... iv
Handling Care ....................................................................................................... iv
Earth Ground Requirement ................................................................................... iv
The Blackbird (VL-EPU-4562/4462) is a compact, rugged x86 type board-level embedded
computer. It is designed and tested to meet military and medical requirements for smaller, lighter,
low power embedded systems. The Blackbird is a member of the VersaLogic family of ultrarugged embedded x86 computers. This embedded computer, equipped with a 6th Generation
Intel Core
vibration.
This embedded computer, equipped with an Intel Core processor, is designed to withstand
extreme temperature, impact, and vibration. Its features include:
Introduction
Introduction
* “Skylake” processor, is designed to withstand extreme temperature, impact, and
dual and quad core processors with
clock rates up to 2.0 GHz
Integrated high-performance video.
Intel HD 520 and 530 - Gen-9
compute architecture, 24 execution
units, and GPU Turbo Boost.
Supports DirectX 12, OpenGL 4.4,
OpenCL 2.0.
Dual Mini DisplayPort and LVDS
video outputs. LVDS backlight
control
Up to 32 GB DDR4 memory
Dual Gigabit Ethernet ports
Dual USB 3.0 port and four USB 2.0
ports support keyboard, mouse, and
other devices
Four RS-232/422/485 serial ports,
audio output, and I
The Blackbird is compatible with popular operating systems including Microsoft
Windows
*
10/WES7, and Linux (see the VersaLogic OS Compatibility Chart).
2
C support
Three 8254 timer/counters
On-board data acquisition support.
Eight multi-range analog inputs, four
analog outputs, and twenty four 3.3V
digital I/O lines
Dual 6 Gb/s SATA ports support
bootable SATA hard drives
Two Full and one half-sized Mini PCIe
Card sockets. Supports Wi-Fi modems,
GPS, MIL-STD-1553, Ethernet, flash
data storage with auto-detect mSATA
flash storage support, and other mini
PCIe modules.
Support for SPI and SPX devices,
including low cost analog and digital
modules.
Customization available
*
Blackbird EPUs receive 100% functional testing and are backed by a limited five-year warranty.
Careful parts sourcing and US-based technical support ensure the highest possible quality,
reliability, service, and product longevity for this exceptional EPU.
VL-EPU-4562/4462 Reference Manual 9
Page 10
Technical Specifications
Refer to the Blackbird Data Sheet for complete specifications. Specifications are subject to
change without notification.
Introduction
VL-EPU-4562/4462 Reference Manual 10
Page 11
PCIe Port 1
Ethernet
InterfaceOn-Board
Key :
COMc-44/COMb-45
COMe Type 6 AB,CD Conn
P08-P13
PCIe Port 0
DualLVDS (A,B)
USB 2.0 Port 2
USB 2.0 Port 3
USB 2.0 Port 4
USB 2.0 Port 5
The figure below provides the board’s dimensions (COM Express Basic size base).
Figure 2. Blackbird Dimensions and Mounting Holes
(Not to scale. All dimensions in millimeters.)
Introduction
VL-EPU-4562/4462 Reference Manual 12
Page 13
2
Initial Configuration
The following components are recommended for a typical development system with the
Blackbird EPU:
ATX power supply
VL-CBR-4005B paddleboard and VL-CBR-4005A cable. Refer to the chapter titled “VL-
CBR-4005B Paddleboard”, beginning on page 56 for details on the VL-CBR-4005B
paddleboard.
USB keyboard and mouse
SATA hard drive
USB CD-ROM drive
Configuration and Setup
VGA monitor and a VL-CBR-2032 Mini DisplayPort-to-VGA adapter
A thermal solution (using either VersaLogic accessories or a customer-designed solution)
You will also need an operating system (OS) installation CD-ROM.
Basic Setup
The following steps outline the procedure for setting up a typical development system. The
Blackbird should be handled at an ESD workstation or while wearing a grounded antistatic wrist
strap.
Before you begin, unpack the Blackbird and accessories. Verify that you received all the items
you ordered. Inspect the system visually for any damage that may have occurred in shipping.
Contact Support@VersaLogic.com
Gather all the peripheral devices you plan to attach to the Blackbird as well as their interface and
power cables. Attach standoffs to the board to stabilize it and make it easier to work with.
The next figure shows a typical setup for the Blackbird in the development environment.
immediately if any items are damaged or missing.
VL-EPU-4562/4462 Reference Manual 13
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Figure 3. Typical Development Configuration
Configuration and Setup
1. Attach Cables and Peripherals
Attach a VGA monitor to either of the baseboard’s Mini DisplayPort++ connectors using a
VL-CBR-2032.
Attach a SATA hard disk to the either of the baseboard’s SATA connectors using a VL-
CBR-0701 or VL-CBR-0702 cable.
Attach a VL-CBR-4005B paddleboard to the baseboard’s User I/O connector.
Connect a USB keyboard and USB mouse to one of the USB Type-A connectors on the VL-
CBR-4005B paddleboard.
Attach a USB CD-ROM drive to one of the USB Type-A connectors on the VL-CBR-4005B
paddleboard.
2. Connect Power Source
Plug the power adapter cable VL-CBR-0809 into the main power connector on the
baseboard. Attach the motherboard connector of the ATX power supply to the adapter.
Attach an ATX power cable to any 3.5-inch drive that is not already attached to the power
supply (hard drive or CD-ROM drive).
VL-EPU-4562/4462 Reference Manual 14
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3. Install Thermal Solution
CAUTION: If BIOS default settings make the system unbootable and prevent the user
from entering the BIOS Setup utility, the Blackbird must be serviced by the factory.
See Installing VersaLogic Thermal Solutions.
4. Review Configuration
Before you power up the system, double-check all the connections. Make sure all cables are
oriented correctly, that adequate power is supplied to the Blackbird and all attached
peripheral devices.
5. Power On
Turn on the ATX power supply and the video monitor. If the system is correctly configured,
a video signal should be present.
6. Install Operating System
Install the operating system according to the instructions provided by the operating system
manufacturer.
BIOS Setup Utility
Configuration and Setup
Refer to the VersaLogic System Utility Reference Manual for information on how to configure
the Blackbird BIOS.
The Blackbird permits you to store user-defined BIOS settings. This enables you to retrieve those
settings from cleared or corrupted CMOS RAM, or battery failure. All BIOS defaults can be
changed, except the time and date. BIOS defaults can be updated with the BIOS Update Utility.
Default BIOS Setup Values
After CMOS RAM clears, the system loads default BIOS parameters the next time the board
powers on. The default CMOS RAM setup values are used in order to boot the system whenever
the main CMOS RAM values are blank, or when the system battery is dead or has been removed
from the board.
Operating System Installation
The standard PC architecture used on the Blackbird makes the installation and use of most of the
standard x86-based operating systems very simple. The operating systems listed on the
VersaLogic Software Support
maker of the operating system. Special optimized hardware drivers for a particular operating
system, or a link to the drivers, are available on the
page use the standard installation procedures provided by the
Blackbird Support Page.
VL-EPU-4562/4462 Reference Manual 15
Page 16
Jumper Blocks
Jumper
Block
Jumper Out: Not terminated (RS-232) (default)
Jumper Out: Not terminated (RS-232) (default)
Jumper Out: Not terminated (RS-232) (default)
Jumper Out: Not terminated (RS-232) (default)
Jumper As-Shipped Configuration
Figure 4. Jumpers As-Shipped Configuration
Configuration and Setup
Jumper Configuration Summary
Table 1: Jumper Block Configurations
Pins Function Description
1-2
V1
3-4
1-2
V2
3-4
VL-EPU-4562/4462 Reference Manual 16
COM1 Endpoint
Termination
COM2 Endpoint
termination
COM3 Endpoint
Termination
COM4 Endpoint
termination
Jumper In: Endpoint termination (for RS-485 or RS-422)
Jumper In: Endpoint termination (for RS-485 or RS-422)
Jumper In: Endpoint termination (for RS-485 or RS-422)
Jumper In: Endpoint termination (for RS-485 or RS-422)
Page 17
Configuration and Setup
Jumper
Module (default)
Jumper Out: Backup BIOS is not write-protected
Block
V3 1-2
V4 1-2
Pins Function Description
Primary/Backup
BIOS Select
Backup BIOS
Write Protect
Jumper In: Use Backup BIOS on the base board
Jumper Out: Use Primary BIOS on the COM Express
Jumper In: Backup BIOS is write-protected (default)
Note: Backup BIOS write protection is not currently implemented
VL-EPU-4562/4462 Reference Manual 17
Page 18
CPU
3
Board Features
Board Features
The Intel Core* SoC features integrated 3D graphics, video encode and decode, and memory and
display controllers in one package. The following CPU configurations are available:
** Note: Special Order Product – Contact VersaLogic Sales for more information
CPU Die Temperature
The CPU die temperature is affected by numerous conditions, such as CPU utilization, CPU
speed, ambient air temperature, airflow, thermal effects of adjacent circuit boards, external heat
sources, and many others.
VL-EPU-4562/4462 Reference Manual 18
Page 19
The thermal management for the Intel Core series of processors consists of a sensor located in
VL-EPU-4462-SAP-08
VL-EPU-4462-SBP-16
VL-EPU-4462-EBP-16**
VL-EPU-4562-SBP-16
VL-EPU-4562-SCP-16
DDR4
VL-EPU-4562-SCP-32
DDR4
VL-EPU-4462-EAP-08
DDR4
VL-EPU-4462-EBP-16
DDR4
2133 MT/s – Single Channel
VL-EPU-4562-EBP-16
DDR4
2133 MT/s – Single Channel
VL-EPU-4562-ECP-16
DDR4
2133 MT/s – Single Channel
VL-EPU-4562-ECP-32
DDR4
2133 MT/s – Dual Channel
the core processor area. The processor contains multiple techniques to help better manage
thermal attributes of the processor. It implements thermal-based clock throttling and thermalbased speed step transitions. There is one thermal sensor on the processor that triggers Intel's
thermal monitor (the temperature at which the thermal sensor triggers the thermal monitor is set
during the fabrication of the processor). Triggering of this sensor is visible to software by means
of the thermal interrupt LVT entry in the local APIC.
System RAM
The Blackbird has DDR4 memory with the following characteristics:
Table 2: Blackbird Memory Characteristics
Board Model Memory Type Capacity Data Rate
VL-EPU-4462-EBP-16**:
** Note: Special Order Product – Contact VersaLogic Sales for more information
Board Features
DDR4 8 GB 2133 MT/s – Single Channel
DDR4 16 GB 2133 MT/s – Single Channel
DDR4 16 GB 2133 MT/s – Single Channel
DDR4 16 GB 2133 MT/s – Single Channel
16 GB 2133 MT/s – Single Channel
32 GB 2133 MT/s – Dual Channel
8 GB 2133 MT/s – Single Channel
DDR4
16 GB
16 GB
16 GB
16 GB
32 GB
2133 MT/s – Single Channel
I/O Interfaces
Later chapters describe the Blackbird’s I/O interfaces and their associated connectors as follows:
Mass Storage Interfaces (SATA) beginning on page 31
Multi-purpose I/O (USB, Mini PCIe / mSATA, User I/O), beginning on page 33
Serial I/O, beginning on page 44
Video Interfaces (Mini DisplayPort++ and LVDS), beginning on page 47
Network Interfaces, beginning on page 53
Real-Time Clock (RTC)
The Blackbird features a real-time clock/calendar (RTC) circuit. The Blackbird supplies RTC
voltage in S5, S3, and S0 states, but requires an external +2.75 V to +3.3 V battery connection.
Refer to the section titled Battery Power Options on page 25 for more information. The BIOS
Setup utility sets the RTC.
VL-EPU-4562/4462 Reference Manual 19
Page 20
External Connectors
Baseboard Connector Locations
Figure 5. Top Baseboard Connector Locations
Board Features
VL-EPU-4562/4462 Reference Manual 20
Page 21
Figure 6. Bottom Baseboard Connector Locations
Board Features
VL-EPU-4562/4462 Reference Manual 21
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Power Delivery
Main Power Connector
An 8-pin power connector applies the Main input power to the Blackbird. The figure below
shows the location and the pin orientation of the main power connector. Table 3 lists the pinout
of the main power connector.
Figure 7. Main Power Connector Pin Orientation
Board Features
VL-EPU-4562/4462 Reference Manual 22
Page 23
Table 3: Main Power Connector Pinout
Main input voltage
(+8V to +30V)
Main input voltage
(+8V to +30V)
Main input voltage
(+8V to +30V)
An open-drain signal
power fault (Note)
The power input is under or over-voltage (not in the 8 - 30V range).
Board Features
Pin Signal Description
1 PWRIN_POS
3 EARTH_GND Earth ground
5 POWER_FAULT
7 PWRIN_NEG Power return
Note: A power fault can be due any of the following conditions:
• The input power is off.
• The main input regulator has failed.
•
• Low if power is OK
• Open if there is a
Pin Signal Description
2 PWRIN_POS
4 PWRIN_POS
6 PWRIN_NEG Power return
8 PWRIN_NEG Power return
Cabling
An adapter cable, part number VL-CBR-0809, is available for connecting the Blackbird to an
ATX power supply.
If your application requires a custom cable, the following information will be useful:
VL-EPU-4562/4462 Board Connector Mating Connector
Molex 055959-0830 Molex 051353-0800
Power Requirements
The Blackbird requires a single +8 to +30 VDC supply capable of providing at least 35 W
average power that can also provide a peak power of 60 W. The input DC supply creates both the
standby and payload voltages provided to the CPU module.
The exact power requirements for the Blackbird depend on several factors, including CPU
configuration (the number of cores, CPU clock rate), memory configuration, peripheral
connections, and attached devices, and others.
The VersaLogic VL-PS-ATX12-300A is a 1U size ATX power supply suitable for use with the
Blackbird. Use the VL-CBR-0809 adapter cable to attach the power supply to the main power
connector.
Power Delivery Considerations
Using the VersaLogic approved power supply (VL-PS-ATX12-300A) and power cable
(VL-CBR-0809) will ensure high quality power delivery to the board. Customers who design
their own power delivery methods should take into consideration the guidelines below to ensure
good power connections.
The specifications for typical operating current do not include any off-board power usage that
fed through the Blackbird power connector. Expansion boards and USB devices plugged into the
board will source additional power through the Blackbird power connector.
VL-EPU-4562/4462 Reference Manual 23
Page 24
Board Features
All processor caches are flushed and the CPUs stop executing instructions. Power to
may be powered down.
Hibernation or Suspend-to-Disk. All content of main memory is saved to non-volatile
memory, such as a hard drive, and is powered down.
Soft Off. Almost the same as G3 Mechanical Off, except that the power supply still
A full reboot is
device.
Do not use wire smaller than 22 AWG. Use high quality UL 1007 compliant stranded wire.
The length of the wire should not exceed 18 inches.
Avoid using any additional connectors in the power delivery system.
The power and ground leads should be twisted together, or as close together as possible to
reduce lead inductance.
A separate conductor must be used for each of the power pins.
All power input pins and all ground pins must be independently connected between the
power source and the power connector.
Use a high quality power supply that can supply a stable voltage while reacting to widely
varying current draws.
Power Button
The User I/O connector (shown in Figure 16 on page 38) includes an input for a power button. A
momentary short to ground or assertion of pin 17 will cause a power button ACPI event. The
button event can be configured in Windows to enter an S3 power state (Sleep, Standby, or
Suspend-to-RAM), an S4 power state (Hibernate or Suspend-to-Disk), or an S5 power state
(Shutdown or Soft-Off). This connector uses IEC 61000-4-2-rated TVS components to help
protect against ESD damage.
A power button is provided on the VL-CBR-4005B paddleboard. Refer to the chapter titled VLCBR-4005B Paddleboard, beginning on page 56 for more information.
Supported Power States
The next table lists the Blackbird’s supported power states.
Table 4: Supported Power States
Power State Description
S0 (G0) Working
S1 (G1-S1)
S3 (G1-S3) Commonly referred to as Standby, Sleep, or Suspend-to-RAM. RAM remains powered.
S4 (G1-S4)
S5 (G2)
G3 Mechanical off (ATX supply switch turned off).
the CPUs and RAM is maintained. Devices that do not indicate they must remain on
provides power, at a minimum, to the power button to allow return to S0.
required. No previous content is retained. Other components may remain powered so
the computer can "wake" on input from the keyboard, clock, modem, LAN, or USB
VL-EPU-4562/4462 Reference Manual 24
Page 25
Board Features
Battery Power Options
The battery circuit on the Blackbird provides power for the Real-Time Clock (RTC) and power
to store BIOS Setup utility settings in non-volatile RAM.
The Blackbird has multiple options for providing battery power:
Use an external battery (the VL-CBR-0203, for example) connected to the board through the
battery connector.
Use the battery supplied with the CBR-4005B paddleboard
The figure below shows the location and pin orientation of the battery connector.
Figure 8. Location and Pin Orientation of the Battery Connector
VL-EPU-4562/4462 Reference Manual 25
Page 26
Board Features
Cabling
If your application requires a custom cable, the following information will be useful:
VL-EPU-4562/4462 Board Connector Mating Connector
Molex 501331-0207 Molex 501330-0200
VL-CBR-0203 External Battery Module
The VL-CBR-0203 external battery module is compatible with the Blackbird. For more
information, contact Sales@VersaLogic.com
Figure 9. VL-CBR-0203 Latching Battery Module
.
External Speaker
The User I/O connector (shown in Figure 16 on page 38) includes a speaker output signal at pin
15. The VL-CBR-4005B paddleboard provides a piezoelectric speaker. Figure 25 on page 56
shows the location of the piezoelectric speaker on the VL-CBR-4005B paddleboard.
Push-button Reset
The User I/O connector (shown in Figure 16 on page 38) includes an input for a push-button
reset switch. Shorting pin 18 to ground causes the Blackbird to reboot. This must be a
mechanical switch or an open-collector or open-drain active switch with less than a 0.5V lowlevel input when the current is 1 mA. There must be no pull-up resistor on this signal. This
connector uses IEC 61000-4-2-rated TVS components to help protect against ESD damage.
A reset button on the VL-CBR-4005B paddleboard is provided. Refer to the chapter titled VLCBR-4005B Paddleboard, beginning on page 56 for more information.
VL-EPU-4562/4462 Reference Manual 26
Page 27
CPU Fan Connector
Pin
Signal
1
Ground
2
+12 VDC (Note)
3
FAN_TACH
4
FAN_CONTROL
Note: There is a stuffing option to change
Pin 2 to V12_S0 for custom products
The Blackbird provides a four-pin CPU fan connector. The figure below shows the location and
pin orientation of the CPU fan connector.
Figure 10. Location and Pin Orientation of the CPU Fan Connector
Board Features
The table below provides the pinout of the CPU fan connector.
Table 5: CPU Fan Connector Pinout
VL-EPU-4562/4462 Reference Manual 27
Page 28
Cabling
LED
Status Indication
Position
If your application requires a custom cable, the following information will be useful:
LEDs
The figure below shows the locations of the status indicator LEDs
Figure 11. Location of Status Indicator LEDs
EPU-4562/4462 Board Connector Mating Connector
Molex 502386-0470 Molex 502380-0400
Wireless WAN/LAN activity for module installed in Mini
D7
PCIe Socket #3 (WWAN is Green, WLAN is Yellow)
Board Features
D8 SATA/mSATA (blue) activity
D9 Power good (green) and fault indicator (yellow) dual-LED
D10 Link activity (green) for Ethernet port 0
D11 Link activity (green) for Ethernet port 1
D12
Wireless WAN/LAN activity for module installed in Mini
PCIe Socket #1 (WWAN is Green, WLAN is Yellow)
VL-EPU-4562/4462 Reference Manual 28
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Board Features
Wireless WAN/LAN activity for module installed in Mini
PCIe Socket #2 (WWAN is Green, WLAN is Yellow)
LED Status Indication Position
Status of power and wireless PAN activity for module
D13
installed in Mini PCIe Socket #1 (Power Status is yellow,
wireless PAN activity is green)
D14
Status of power and wireless PAN activity for module
D15
installed in Mini PCIe Socket #2 (Power Status is yellow,
wireless PAN activity is green)
D16
Status of power and wireless PAN activity for module
installed in Mini PCIe Socket #3 (Power Status is yellow,
wireless PAN activity is green)
VL-EPU-4562/4462 Reference Manual 29
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Board Features
Power-Good/Fault Indicator LEDs
A dual-color (green/yellow) LED (D9) provides the following status:
Green – indicates power good when the Blackbird in an S0 state. When in sleep modes, the
LED pulses every 2 seconds.
Yellow – indicates a fault. If this LED remains lit after power-cycling the Blackbird, contact
VersaLogic Customer Support.
VL-EPU-4562/4462 Reference Manual 30
Page 31
SATA Interface
4
The Blackbird provides three serial ATA 3.0 (SATA 3.0) ports that communicate at a rate of up
to 6.0 Gbits/s. Two ports connect to right-angle SATA connectors with latching capability. The
third port connects to Minicard #1 when an mSATA module is installed.
The ATX power supplies Power to the SATA drive. Note that the standard SATA drive power
connector is different from the common 4-pin Molex connector used on IDE drives. Most current
ATX power supplies provide SATA connectors, and many SATA drives provide both types of
power connectors. If the power supply you are using does not provide SATA connectors,
adapters are available.
Figure 12. Location of the SATA Connectors
Mass Storage Interfaces
Mass Storage Interfaces
VL-EPU-4562/4462 Reference Manual 31
Page 32
Mass Storage Interfaces
Table 6. SATA Port Configuration
COM Port Port Speed Destination
0 SATA 3.0 On-board SATA right-angle latching connector J1 (VL P/N
XE1SATASA)
1 SATA 3.0 On-board SATA right-angle latching connector J3 (VL P/N
XE1SATASA)
2 SATA 3.0 Electronically mux’d to the minicard #1 when selected for mSATA
mode (otherwise this port is not used).
VL-EPU-4562/4462 Reference Manual 32
Page 33
USB Interfaces
5
As shown below, the Blackbird supports four USB 2.0 Host ports and two USB 3.0 Super-Speed
ports.
Figure 13. Location of the USB Ports
Multi-purpose I/O
Multi-purpose I/O
VL-EPU-4562/4462 Reference Manual 33
Page 34
Mini PCIe Sockets
The figure below shows the location of the three Mini PCIe sockets. All three minicards support
USB and SMBus interfaces. Minicard 1 is full-size and supports either a PCIe Minicard or an
mSATA module. Minicard 2 is also full-size and supports PCIe. Minicard 3 is half-size and
supports PCIe. For information on Mini PCIe modules available from VersaLogic, contact
Sales@VersaLogic.com
The VL-MPEs-F1E series of mSATA modules provide flash storage of 4 GB, 16 GB, or 32 GB.
To secure a Mini PCIe card or mSATA module to the on-board standoffs, use two M2.5 x 6 mm
pan head Philips nylon screws. These screws are available in quantities of 10 in the VL-HDW108 hardware kit from VersaLogic.
Figure 14. Location of Mini PCIe Sockets
Multi-purpose I/O
.
VL-EPU-4562/4462 Reference Manual 34
Page 35
Mini PCIe
Signal Name
mSATA
Signal Name
Table 7: Mini PCIe / mSATA Socket Pinout
Multi-purpose I/O
Pin
1 WAKE# Wake Reserved Not connected
2 3.3VAUX 3.3 V auxiliary source +3.3V 3.3 V source
3 NC Not connected Reserved Not connected
4 GND Ground GND Ground
5 NC Not connected Reserved Not connected
6 1.5V 1.5 V power +1.5V 1.5 V power
7 CLKREQ# Reference clock request Reserved Not connected
8 NC Not connected Reserved Not connected
9 GND Ground GND Ground
10 NC Not connected Reserved Not connected
11 REFCLK- Reference clock input – Reserved Not connected
12 NC Not connected Reserved Not connected
13 REFCLK+ Reference clock input + Reserved Not connected
14 NC Not connected Reserved Not connected
15 GND Ground GND Ground
16 NC Not connected Reserved Not connected
17 NC Not connected Reserved Not connected
18 GND Ground GND Ground
19 NC Not connected Reserved Not connected
20 W_DISABLE# Wireless disable Reserved Not connected
30 SMB_CLK SMBus clock Two Wire I/F Two wire I/F clock
31 PETn0 PCIe transmit –
32 SMB_DATA SMBus data Two Wire I/F Two wire I/F data
33 PETp0 PCIe transmit +
34 GND Ground GND Ground
35 GND Ground GND Ground
36 USB_D- USB data – Reserved Not connected
Mini PCIe Function
mSATA Function
-A Host transmitter diff. pair
–
+A Host transmitter diff. pair
+
VL-EPU-4562/4462 Reference Manual 35
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Multi-purpose I/O
Mini PCIe
Signal Name
mSATA
Signal Name
Pin
37 GND Ground GND Ground
38 USB_D+ USB data + Reserved Not connected
39 3.3VAUX 3.3V auxiliary source +3.3V 3.3 V source
40 GND Ground GND Ground
41 3.3VAUX 3.3 V auxiliary source +3.3V 3.3 V source
42
43 GND
44 LED_WLAN# Wireless LAN LED Reserved Not connected
45 NC Not connected Vendor Not connected
46 LED_WPAN# Wireless PAN LED Reserved Not connected
47 NC Not connected Vendor Not connected
48 1.5V 1.5 V power +1.5V 1.5 V power
49 Reserved Reserved DA/DSS Device activity
50 GND Ground GND Ground
51 Reserved Reserved
52 3.3VAUX 3.3 V auxiliary source +3.3V 3.3 V source
LED_WW AN
#
Mini PCIe Function
Wireless WAN LED
mSATA Detect (Note 1)
mSATA Function
Reserved Not connected
GND/NC Ground/Not connected
GND
Ground (Note 2)
Notes:
1. Some mSATA modules do not leave Pin 43 open.
2. Some Mini PCIe cards use this signal as a second Mini PCIe card wireless disable input. On the
Blackbird, this signal is available for use for mSATA versus Mini PCIe card detection. There is an
option on the VersaLogic Features BIOS Setup utility screen for setting the mSATA detection
method.
W_DISABLE# Signal
The W_DISABLE# signal is for use with optional wireless Ethernet Mini PCIe cards. The signal
enables you to disable a wireless card’s radio operation in order to meet public safety regulations
or when otherwise desired. W_DISABLE# is an active low signal that when driven low (shorted
to ground) disables radio operation on the Mini PCIe card wireless device. When W_DISABLE#
is not asserted, or in a high impedance state, the radio may transmit if not disabled by other
means such as software. The W_DISABLE# signals for each of the three Minicards are
controlled by registers in the FPGA.
VL-EPU-4562/4462 Reference Manual 36
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Multi-purpose I/O
Mini PCIe Card Status LEDs
These LEDs provide status for modules installed in the Mini PCIe sockets. The table below lists
the states of the LEDs. The Power On LED is an important warning to not hot-plug the minicard.
It is intentionally yellow to indicate “caution”. Figure 15 shows their location on the Blackbird.
Table 8: Mini PCIe Card Status LEDs
LED Ref Des State Description
Green (WWAN) D12 (#1)
D14 (#2)
D7 (#3)
Yellow (WLAN) D12 (#1)
D14 (#2)
D7 (#3)
Green (WPAN) D13 (#1)
D15 (#2)
D16 (#3)
Yellow
(Power On)
D13 (#1)
D15 (#2)
D16 (#3)
On WWAN active
Off W WAN inactive
On WLAN active
Off W LAN inactive
On W PAN active
Off W PAN inactive
On Minicard Power is On
Off Minicard Power is Off
Figure 15. Mini PCIe Status LEDs
VL-EPU-4562/4462 Reference Manual 37
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User I/O Connector
The 40-pin user I/O connector incorporates the signals for the following:
Four USB ports
Eight GPIO lines (these are functionally muxed with six timer I/O signals per FPGA
registers). There are eight timer signals and they share digital I/Os 16-9. The eight GPIO
lines on the paddleboard each have an alternate mode, accessible using the FPGA’s
AUXMODE1 register. Refer to the EPU-4562/4462 Programmer’s Reference Manual for
more information on FPGA registers.
Three LEDs (two Ethernet link status LEDs and a programmable LED)
Two I
Push-button power switch
Push-button reset switch
Speaker output
2
C signals (clock and data)
Multi-purpose I/O
This connector uses IEC 61000-4-2-rated TVS components to help protect against ESD damage.
The following figure shows the location and pin orientation of the user I/O connector.
Figure 16. Location and Pin Orientation of the User I/O Connector
VL-EPU-4562/4462 Reference Manual 38
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The following table provides the pinout of the user I/O connector.
Pin
Signal
Pin
Signal
1
+5 V (Note 1)
2
GND
3
USB1_P
4
USB2_P
5
USB1_N
6
USB2_N
7
+5V (Note 2)
8
GND
9
USB3_P
10
USB4_P
11
USB3_N
12
USB4_N
13
+3.3 V (Note 3)
14
GND
15
SPKR#
16
PLED#
17
PWR_BTN#
18
RST_BTN#
19
GND
20
GND
21
I2C Clock
22
V_BATT
23
I2C Data
24
V_BATT Return
25
GND
26
GND
27
GPIO1
28
GPIO2
29
GPIO3
30
GPIO4
31
GND
32
GND
33
GPIO5
34
GPIO6
35
GPIO7
36
GPIO8
37
+3.3 V (Note 4)
38
GND
39
ETH LED0
40
ETH LED1
Notes:
be powered by a 3.3 V power source.
Table 9: User I/O Connector Pinout and Pin Orientation
Multi-purpose I/O
1. This is the +5V VBUS power for USB Port 1 and 2.
2. This is the +5V VBUS power for USB Port 3 and 4.
3. This 3.3 V power goes off in sleep modes. The SPKR# uses this power as
should the PLED# (there is no requirement for PLED# to use this power, but the
VL-CBR-4005B paddleboard does).
4. This 3.3 V power can be turned on or off similar to the 3.3V power to the Mini
Card via the FPGA (can go off in sleep modes or always stay on; by default it
goes off in sleep modes). It is used for the 10 kΩ pullup resistor power on the 8x
GPIOs and usually for the 2x Ethernet LEDs, however, the Ethernet LEDs can
Cabling
An adapter cable, part number VL-CBR-4005A, is available for connecting the CBR-4005B
paddleboard to the VL-EPU-4562/4462. This is a 12-inch, Pico-Clasp 40-pin to 40-pin cable.
If your application requires a custom cable, the following information will be useful:
EPU-4562/4462 Board Connector Mating Connector
Molex 501571-4007 Molex 501189-4010
VL-EPU-4562/4462 Reference Manual 39
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Multi-purpose I/O
Analog-to-Digital and Digital to Analog Converter Interface
The Analog-to-Digital and Digital to Analog converter interface provides eight single-ended
analog input channels. The figure below shows the location and pin orientation of the Analog-toDigital and Digital to Analog connector.
The 20-pin I/O connector (J30) incorporates 16 Digital I/O (DIO) lines that are independently
configurable as an input or output. DIO inputs can be set for normal or inverted level. DIO
outputs can be set to be normal HIGH or LOW state. There are pull-up resistors to +3.3 V on all
DIO lines. The pull-ups implemented — in the FPGA — can range in value from 20 kΩ to 40 kΩ. After reset, the DIO lines are set as inputs with pull-ups that will be detected as a HIGH state
to external equipment.
VersaLogic provides a set of application programming interface (API) calls for managing the
DIO lines. See the VersaAPI Support Page for information
Figure 17. Location and Pin Orientation of the Analog-to-Digital Input Connector
VL-EPU-4562/4462 Reference Manual 40
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Multi-purpose I/O
±0.64 V
0 to 1.28 V
±1.28 V
0 to 2.56 V
±2.56 V
0 to 5.12 V
±5.12 V
0 to 10.24 V
±10.24 V
The EPU-4562/4462 uses a Texas Instruments ADS8668 eight-channel 12-bit A/D converter.
The converter has a 500 kilo-samples-per-second (ksps) aggregate sampling rate, with a 1.115 μs
acquisition time, high-impedance The converter is per-channel programmable for the following
input ranges:
Communications with the A/D converter are handled by the FPGA, which uses the SPX slave
selection signal for SPI device 5 to enable the A/D read strobe for the SPI interface. Refer to the
VL-EPU-4562/4462 Programmer’s Reference Manual (available on the EPU-4562/4462 Product
Support Web Page) for information on configuring the SPX registers for A/D access.
Refer to the Texas Instruments ADS8668 A/D Converter Datasheet
for programming
information.
This table provides the pinout of the Analog-to-Digital and Digital to Analog Input connector.
Table 10: Analog-to-Digital and Digital to Analog Input Connector Pinout
Pin Signal Pin Signal
1 Analog Input 1 2 Analog Input 2
3 Analog Ground 4 Analog Ground
5 Analog Input 3 6 Analog Input 4
7 Analog Ground 8 Analog Ground
9 Analog Input 5 10 Analog Input 6
11 Analog Ground 12 Analog Ground
13 Analog Input 7 14 Analog Input 8
15 Analog Ground 16 Analog Ground
17 Analog Output #1 18 Analog Output #2
19 Analog Output #3 20 Analog Output #4
VL-EPU-4562/4462 Reference Manual 41
Cabling
The VL-CBR-2004 paddleboard is bundled with an adapter cable for connecting the Blackbird to
the VL-CBR-2004 paddleboard. This is a 12-inch, Pico-Clasp 20-pin to 20-pin cable.
If your application requires a custom cable, the following information will be useful:
EPU-4562/4462 Board Connector Mating Connector
Molex 501571-2007 Molex 501189-2010
Page 42
SPX™ Expansion Bus
Up to two serial peripheral expansion (SPX) devices can be attached to the Blackbird at
connector using a CBR-0901 cable. The SPX interface provides the standard serial peripheral
interface (SPI) signals: CLK, MISO, and MOSI, as well as two chip selects, SS0# and SS1#. The
+5 V power provided to pin 1 of the SPX connector is protected by a 1 A resettable fuse.
The figure below shows the location and pin orientation of the SPX connector.
Figure 18. SPX Connector Location and Pin Configuration
Multi-purpose I/O
VL-EPU-4562/4462 Reference Manual 42
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Multi-purpose I/O
Note)
The table below lists the pinout of the SPX connector.
Table 11: SPX Connector Pinout
Pin Signal Function
1 VCC
2 CLK SPX Clock
3 GND Ground
4 MISO Master input, Slave output
5 GND Ground
6 MOSI Master output, Slave input
7 GND Ground
8 SS0# Chip Select 0
9 SS1# Chip Select 1
Note. This power is off in sleep mode
+5.0 V (
SPI is, in its simplest form, a three wire serial bus. One signal is a clock, driven only by the
permanent master device on-board. The others are Data In and Data Out with respect to the
master. The SPX implementation on the Blackbird supports chip selects. The master device
initiates all SPI transactions. A slave device responds when its chip select is asserted and it
receives clock pulses from the master. All four common SPI modes are supported through the use
of clock polarity and clock idle state controls.
Cabling
An adapter cable, part number CBR-0901, is available. This is a 9-inch, 9-pin Pico-Clasp to Dual
SPX cable.
If your application requires a custom cable, the following information will be useful:
EPU-4562/4462 Board Connector Mating Connector
Molex 501568-0907 Molex 501330-0900
VL-EPU-4562/4462 Reference Manual 43
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Serial Ports
6
The Blackbird provides four serial ports. All ports can operate in either RS-232, RS-422, or RS485 mode. IRQ interrupts are chosen in the BIOS Setup utility. The UARTs are 16550-based
serial ports implemented in the FPGA.
The figure below shows the location and pin orientation of the two serial I/O connectors.
Figure 19. Location and Pin Orientation of the Serial I/O Connectors
Serial I/O
Serial I/O
VL-EPU-4562/4462 Reference Manual 44
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Serial Port Connector Pinout
Table 12: COM1/COM2 Connector Pinout
Serial I/O
Pin RS-232 Signal
1 RTS1 TXD1_P
2 TXD1# TXD1_N
3 CTS1 RXD1_P
4 RXD1# RXD1_N
5 GND GND —
6 RTS2 TXD2_P
7 TXD2# TXD2_N
8 CTS2 RXD2_P
9 RXD2# RXD2_N
10 GND GND —
Table 13: COM3/COM4 Connector Pinout
Pin RS-232 Signal
1 RTS3 TXD3_P
2 TXD3# TXD3_N
3 CTS3 RXD3_P
4 RXD3# RXD3_N
5 GND GND —
6 RTS4 TXD4_P
7 TXD4 TXD4_N
8 CTS4 RXD4_P
9 RXD4# RXD4_N
10 GND GND —
RS-422/RS-485
Signal
RS-422/RS-485
Signal
Port
COM1
COM2
Port
COM3
COM4
Cabling
An adapter cable, part number CBR-1014, is available for routing the serial I/O signals to 9-pin
D-sub connectors. This is a 12-inch, Pico-Clasp 10-pin to two 9-pin D-sub connector cable.
VL-EPU-4562/4462 Reference Manual 45
Page 46
If your application requires a custom cable, the following information will be useful:
EPU-4562/4462 Board Connector Mating Connector
Molex 501331-1007 Molex 501330-1000
COM Port Configuration
Jumper blocks V1 and V2 configure the serial ports for RS-232 or RS-485/RS-422 operation. See
the section titled “Jumper Blocks” on page 16 for details. The termination resistor should only be
enabled for RS-485 or RS-422 endpoint stations and not for intermediate stations. Termination
must not be used for RS-232.
Console Redirection
The Blackbird can be configured for remote access by redirecting the console to a serial
communications port. The BIOS Setup utility and some operating systems (such as MS-DOS)
can use this console for user interaction. The default settings for the redirected console are as
follows:
115,200 baud rate
Serial I/O
8 data bits, No parity, 1 stop bit (that is, 8-None-1)
No flow control
VL-EPU-4562/4462 Reference Manual 46
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Video Interfaces
7
The Intel Core processor series contains an integrated graphics engine with advanced 2D/3D
graphics, video decode and encode capabilities, and a display controller. The Blackbird provides
the following video interfaces:
Two Mini DisplayPort++ connectors
One LVDS display connector; a 4-pin LVDS backlight control connector is also provided
Mini DisplayPort++ (DP++) Connectors
DisplayPort consists of three interfaces:
Main Link – transfers high-speed isochronous video and audio data
Auxiliary channel – used for link management and device control; the EDID is read over this
interface
Video Interfaces
Hot Plug Detect – indicates that a cable is plugged in
The DisplayPort interface supports:
Audio signaling
DP++ mode allowing connection to an HDMI device through a passive adapter. “Passive”
means that the adapter does not do any protocol conversion from DP to HDMI (the upstream
processor switches to HDMI mode after it detects the adapter) and as a result it does not
require software drivers.
The next figure shows the location of the 20-pin Mini DisplayPort++connector. Table 14 lists the
pinout of these Mini DisplayPort++ connectors.
VL-EPU-4562/4462 Reference Manual 47
Page 48
Figure 20. Location of the Mini DisplayPort++ Connector
Pin
Signal
Pin
Signal
1
GND 2
HOT PLUG DETECT
3
ML_LANE0_P
4 CONFIG 1
5
ML_LANE0_N
6 CONFIG 2
7
GND 8
GND
9
ML_LANE1_P
10
ML_LANE3_P
11
ML_LANE1_N
12
ML_LANE3_N
13
GND 14
GND
15
ML_LANE2_P
16
AUX_CH_P
17
ML_LANE2_N
18
AUX_CH_N
Note
Video Interfaces
Table 14: Mini DisplayPort++ Connector Pinout
19 GND
20 DP_POWER (3.3V)
Note: Power is off in sleep modes and the maximum current is 500mA and has a 1A resettable fuse.
VL-EPU-4562/4462 Reference Manual 48
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Video Interfaces
VGA Output
A VGA monitor can be attached to either Mini DisplayPort++ connector using the VL-CBR2032 Mini DisplayPort-to-VGA adapter, similar to the one below.
Figure 21. VL-CBR-2032 Mini DisplayPort to VGA Adapter
VL-EPU-4562/4462 Reference Manual 49
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LVDS Interface
1
GD1
Guard (tie to Earth Ground).
2
LVDS_ODD0_N
LVDS Odd Lane 0 Neg Diff Signal
3
LVDS_ODD0_P
LVDS Odd Lane 0 Pos Diff Signal
4
LVDS_ODD1_N
LVDS Odd Lane 1 Neg Diff Signal
5
LVDS_ODD1_P
LVDS Odd Lane 1 Pos Diff Signal
6
LVDS_ODD2_N
LVDS Odd Lane 2 Neg Diff Signal
7
LVDS_ODD2_P
LVDS Odd Lane 2 Pos Diff Signal
8
GND1
Signal/Power Ground
9
LVDS_ODDCLK_N
LVDS Odd Clock Neg Diff Signal
10
LVDS_ODDCLK_P
LVDS Odd Clock Pos Diff Signal
11
LVDS_ODD3_N
LVDS Odd Lane 3 Neg Diff Signal
12
LVDS_ODD3_P
LVDS Odd Lane 3 Pos Diff Signal
13
LVDS_EVEN0_N
LVDS Even Lane 0 Neg Diff Signal
LVDS Flat Panel Display Connector
The integrated LVDS flat panel display in the Blackbird is an ANSI/TIA/EIA-644-1995
specification-compliant interface. It can support 18 or 24 bits of RGB pixel data plus 3 bits of
timing control (HSYNC/VSYNC/DE) on the 4 differential data output pairs. The LVDS interface
supports a maximum resolution of 1920x1080 (60 Hz). The figure below shows the location of
the LVDS display connector as well as the location and pin orientation of the LVDS back light
connector.
The BIOS Setup utility provides several options for standard LVDS flat panel types. If these
options do not match the requirements of the panel you are using, contact
Mounting pad on Pin1 end connected
to Guard pins (tie to Earth Ground).
Mounting pad on Pin 32 end
Ground).
33 MP1
Video Interfaces
34 MP2
Note: Panel power goes off in sleep modes.
connected to Guard pins (tie to Earth
The +3.3V power provided to pins 19 and 20 is protected by a software-controllable power
switch (1 Amp max.). The LVDD_EN signal controls this switch from the LVDS interface
controller in the CPU.
Cabling
The following LVDS cables are available for use with the Blackbird board:
If your application requires a custom cable, the following information will be useful:
EPU-4562/4462 Board Connector Mating Connector
Hirose DF19G-20P-1H(54)
• Hirose DF19G-20S-1C (housing)
• Hirose DF19-2830SCFA x19 (crimp socket)
VL-EPU-4562/4462 Reference Manual 51
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Video Interfaces
LVDS backlight enable output. (5V TTL-level signal by default
but will operate at higher voltages if the LVDS_BKLT_PWR is
High = enabled, Low = disabled.
LVDS backlight control output. (5V TTL-level signal by default
but will operate at higher voltages if the LVDS_BKLT_PWR is
set in the BIOS Setup utility.
Optional backlight logic power input. (Can range from +5V to
On-board +5V power is used when this is not connected.
LVDS Backlight Connector
Figure 22 shows the location and pin orientation of the LVDS back light connector. The table
below lists the pinout of the LVDS backlight connector.
Table 16: LVDS Backlight Connector Pinout
Pin Signal Name Function
1 LVDS_BKLT_EN
2 Signal Ground Ground
3 LVDS_BKLT_CTRL
4 LVDS_BKLT_LOGIC_PWR
provided).
provided). This is a PWM signal and the duty cycle can be
+14V and sets the high-value on the LVDS_BKLT_EN and
LVDS_BKLT_CTRL signals.)
Cabling
An adapter cable, part number CBR-0404, is available for powering the LVDS backlight from
the Blackbird board.
If your application requires a custom cable, the following information will be useful:
EPU-4562/4462 Board Connector Mating Connector
Molex 501568-0407 Molex 501330-0400
VL-EPU-4562/4462 Reference Manual 52
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Network Interfaces
8
Network Interfaces
The Blackbird provides two Gigabit Ethernet interfaces with one from an Intel I210-IT Gigabit
Ethernet controller on the baseboard and the second from an Intel I219-LM Gigabit Phy on the
COM Express module (connected to the internal MAC in the Skylake processor). They both
provide a standard IEEE 802.3 Ethernet interface for 1000Base-T, 100Base-TX, and 10Base-T
applications. Both auto-negotiate connection speed. Drivers are readily available to support a
variety of operating systems. For more information on these devices, refer to
Controller datasheet or Intel I219 Ethernet Controller datasheet.
Integrator’s Note: Ethernet Port 1 supports network boot; Port 0 does not.
Ethernet Connector
The Ethernet connector provides access to the Ethernet ports 0 and 1. Ethernet Port 0 connects to
the I210-IT Ethernet controller on the baseboard and Ethernet Port 1 connects to the I219-LM
Ethernet Phy on the COM Express module. The connector uses IEC 61000-4-2-rated TVS
components to help protect against ESD damage. The figure below shows the location and pin
orientation of the Ethernet connector.
Intel I210 Ethernet
Figure 23. Location and Pin Orientation of the Ethernet Connector
VL-EPU-4562/4462 Reference Manual 53
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The following table lists the pinout of the Ethernet connector.
Table 17: Ethernet Connector Pinout
Network Interfaces
Pin 10/100 Signals
1 - Auto Switch (Tx or Rx) BI_DD- 2 + Auto Switch (Tx or Rx) BI_DD+
3 - Auto Switch (Tx or Rx) BI_DB- 4 + Auto Switch (Tx or Rx) BI_DB+
5 - Auto Switch (Tx or Rx) BI_DC- 6 + Auto Switch (Tx or Rx) BI_DC+
Port 0
7 - Auto Switch (Tx or Rx) BI_DA- 8 + Auto Switch (Tx or Rx) BI_DA+
9 - Auto Switch (Tx or Rx) BI_DD- 10 + Auto Switch (Tx or Rx) BI_DD+
11 - Auto Switch (Tx or Rx) BI_DB- 12 + Auto Switch (Tx or Rx) BI_DB+
13 - Auto Switch (Tx or Rx) BI_DC- 14 + Auto Switch (Tx or Rx) BI_DC+
Port 1
15 - Auto Switch (Tx or Rx) BI_DA- 16 + Auto Switch (Tx or Rx) BI_DA+
10/100/1000
Signals
Pin 10/100 Signals
10/100/1000
Signals
Cabling
An adapter cable, part number CBR-1604, is available. This is a 12-inch, 16-pin Click-Mate to
two RJ-45 connector cables.
If your application requires a custom cable, the following information will be useful:
EPU-4562/4462 Board Connector Mating Connector
Molex 503148-1690 Molex 503149-1600
Port 0
Port 1
VL-EPU-4562/4462 Reference Manual 54
Page 55
Ethernet Status LEDs
The figure below shows the location of the Ethernet status LED.
Table 18. Ethernet Status LED Details
LED Ref Des State Description
Green (Activity)
Figure 24. Onboard Ethernet Status LEDs
D10 (Eth 0)
D11 (Eth 1)
On Link Good (pulses with activity)
Off Link is not good or cable is not
connected
Network Interfaces
VL-EPU-4562/4462 Reference Manual 55
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VL-CBR-4005B Paddleboard
9
VL-CBR-4005B Paddleboard
VL-CBR-4005B Connectors and Indicators
This figure shows the locations of the connectors, switches, and LEDs on the VL-CBR-4005B
paddleboard.
Figure 25. VL-CBR-4005B Connectors, Switches, and LEDs
VL-EPU-4562/4462 Reference Manual 56
Page 57
VL-CBR-4005B Paddleboard
Pin
Signal
Pin
Signal
3
USB1_P
4
USB2_P
5
USB1_N
6
USB2_N
7
+5V
8
GND
9
USB3_P
10
USB4_P
11
USB3_N
12
USB4_N
13
+3.3 V (Note 1)
14
GND
27
GPIO1
28
GPIO2
29
GPIO3
30
GPIO4
31
GND
32
GND
33
GPIO5
34
GPIO6
35
GPIO7
36
GPIO8
37
+3.3 V (Note 2)
38
GND
User I/O Connector
The figure below shows the location and pin orientation of the user I/O connector.
Figure 26. Location and Pin Orientation of the User I/O Connector
Table 19: User I/O Connector Pinout
1 +5 V 2 GND
15 SPKR# 16 PLED#
17 PWR_BTN# 18 RST_BTN#
19 GND 20 GND
21 I2C Clock 22 V_BATT
23 I2C Data 24 V_BATT RETURN
25 GND 26 GND
39 ETH0 LED 40 ETH1 LED
Notes:
1. This 3.3 V power goes off in sleep modes. The SPKR# uses this power as should the PLED#
(there is no requirement for PLED# to use this power, but the VL-CBR-4005B paddleboard does).
2. This 3.3 V power can be turned on or off similar to the 3.3V power to the Mini Card via the FPGA
VL-EPU-4562/4462 Reference Manual 57
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VL-CBR-4005B Paddleboard
To prevent shorting, premature failure or damage to the Lithium battery, do not
battery in fire. Dispose of used batteries promptly.
(can go off in sleep modes or always stay on; by default it goes off in sleep modes). It is used for
the 10 kΩ pullup resistor power on the 8x GPIOs and usually for the 2x Ethernet LEDs, however,
the Ethernet LEDs can be powered by a 3.3 V power source.
Cabling
An adapter cable, part number CBR-4005A, is available for connecting the VL-CBR-4005B
paddleboard to the EPU-4562/4462. This is a 12-inch, Pico-Clasp 40-pin to 40-pin cable
If your application requires a custom cable, the following information will be useful:
CBR-4005B Board Connector Mating Connector
Molex 501571-4007 Molex 501189-4010
On-board Battery
CAUTION:
place the board on a conductive surface such as metal, black conductive foam
or the outside surface of a metalized ESD protective pouch. The Lithium battery
may explode if mistreated. Do not recharge, disassemble, or dispose of the
Nominal battery voltage is 3.0 V. If the voltage drops below 2.7 V, contact the factory for a
replacement. The life expectancy under normal use is approximately five years.
VL-EPU-4562/4462 Reference Manual 58
Page 59
VL-CBR-4005B Paddleboard
Pin
Signal
Pin
Signal
1
I2C Clock
2
V_BATT
3
I2C Data
4 V_BATT_RETURN
5
GND
6
GND
7
GPIO1
8
GPIO2
9
GPIO3
10
GPIO4
11
GND
12
GND
13
GPIO5
14
GPIO6
15
GPIO7
16
GPIO8
17
+3.3 V (Note)
18
GND
19
Ethernet Port 0 LED
20
Ethernet Port 1 LED
Auxiliary I/O Connector
The next figure shows the location and pin orientation of the auxiliary I/O connector.
Figure 27. Location and Pin Orientation of Auxiliary I/O Connector
Table 20: Auxiliary I/O Connector Pinout
Note. Pin 17 connects to the 3.3V power on the main connector Pin 37.
VL-EPU-4562/4462 Reference Manual 59
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Dimensions and Mounting Holes
Figure 28. VL-CBR-4005B Dimensions and Mounting Holes
VL-CBR-4005B Paddleboard
VL-EPU-4562/4462 Reference Manual 60
Page 61
Digital and Analog I/O Paddleboards
Pin
Signal
Description
1
ADC_CH1
Analog Input #1
2
ADC_CH2
Analog Input #2
3
AGND
Analog Ground
4
AGND
Analog Ground
5
ADC_CH3
Analog Input #3
6
ADC_CH4
Analog Input #4
7
AGND
Analog Ground
8
AGND
Analog Ground
9
ADC_CH5
Analog Input #5
10
ADC_CH6
Analog Input #6
11
AGND
Analog Ground
12
AGND
Analog Ground
13
ADC_CH7
Analog Input #7
14
ADC_CH8
Analog Input #8
15
AGND
Analog Ground
16
AGND
Analog Ground
17
DAC_OUT1
Analog Output #1
18
DAC_OUT2
Analog Output #2
19
DAC_OUT3
Analog Output #3
20
DAC_OUT4
Analog Output #4
10
Analog I/O (Using VL-CBR-2004)
To access the eight analog-to-digital inputs and four digital-to-analog outputs on the Blackbird, a
paddleboard and 12-inch cable are available from VersaLogic, part number VL-CBR-2004. This
section shows the locations and pin orientations of the connectors on the CBR-2004B
paddleboard.
Table 21. CBR-2004B Pinouts
Digital and Analog I/O Paddleboards
VL-EPU-4562/4462 Reference Manual 61
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Figure 29. Analog I/O and Ground Terminal Block Pinouts
Pin
Signal
Description
Pin
Signal
Description
1
DIO1
Digital I/O
2
DIO2
Digital I/O
3
DIO3
Digital I/O
4
DIO4
Digital I/O
5
DGND
Digital Signal Ground
6
DIO5
Digital I/O
7
DIO6
Digital I/O
8
DIO7
Digital I/O
9
DIO8
Digital I/O
10
DGND
Digital Signal Ground
11
DIO9/OCTC5
Digital I/O (optional Timer Chan
5 Output)
12
DIO10/ICTC5
Digital I/O (optional
Timer Chan 5 Output)
13
DIO11/GCTC3
3 Gate Input)
14
DIO12/GCTC4
Digital I/O (optional
Input)
15
DGND
Digital Signal Ground
16
DIO13/OCTC3
Digital I/O (optional
Timer 3 Output)
17
DIO14/ICTC3
Digital I/O (optional Timer 3
Input)
18
DIO15/OCTC4
Digital I/O (optional
Timer 4 Output)
19
DIO16/ICTC4
Digital I/O (optional Timer 4
Input)
20
DGND
Digital Signal Ground
Digital and Analog I/O Paddleboards
Digital I/O (Using VL-CBR-2005)
The table below shows the specific Digital I/O and ground connections when using the VL-CBR2004 paddleboard and cable VL-CBR-2005 with the Blackbird.
Digital I/O (optional Timer Chan
Timer Chan 4 Gate
VL-EPU-4562/4462 Reference Manual 62
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Figure 30. Digital I/O and Ground Terminal Block Pinouts
Digital and Analog I/O Paddleboards
Dimensions and Mounting Holes
Figure 31. CBR-2004B Dimensions and Mounting Holes
VL-EPU-4562/4462 Reference Manual 63
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Thermal Considerations
By itself, the heat plate is not a complete thermal solution. Integrators should either implement a
below 85 ºC.
The heat plate is permanently affixed to the Blackbird and must not be removed. Removal of the
voids the product warranty and can damage the CPU.
11
Thermal Considerations
This chapter discusses the following topics related to thermal issues:
Selecting the correct thermal solution for your application
EPU-4562/4462 thermal characterization
Installing the passive (HDW-417 heat sink), the active (HDW-418 fan), and the heat pipe
block (HDW-408) thermal solutions available from VersaLogic
Selecting the Correct Thermal Solution for Your Application
This section provides guidelines for the overall system thermal engineering effort.
Heat Plate
The heat plate supplied with the Blackbird is the basis of the thermal solution. The heat plate
draws heat away from the CPU chip as well as other critical components. Some components rely
on the ambient air temperature at or below the maximum specified 85 ºC temperature.
The design of the heat plate assumes that the user’s thermal solution will maintain the top surface
of the heat plate at 90 ºC or less. If that temperature threshold is maintained, the CPU will remain
safely within its operating temperature limits.
CAUTION:
thermal solution using the accessories available from VersaLogic or develop their own thermal
solution that attaches to the heat plate, suitable for environments in which the EPU-4562/4462
will be used. As stated above, the thermal solution must be capable of keeping the top surface of
the heat place at or below 90 ºC and the air surrounding the components in the assembly at or
heat plate voids the product warranty. Attempting to operate the Blackbird without the heat plate
System-level Considerations
The Blackbird is often mounted directly to another thermally controlled surface via its heat plate
(that is, the inside surface of an enclosure). In this case, the user needs to maintain the heat plate
at or below 90 ºC by controlling the mounting surface temperature. The EPU-4562/4462 thermal
solutions available from VersaLogic – the HDW-417 heat sink with or without the HDW-418
fan, or the HDW-408 heat pipe block – can be used in the user’s final system or only used during
product development as a temporary bench-top solution.
The ambient air surrounding the EPU-4562/4462 needs to be maintained at 85 ºC or below. This
may prove to be challenging depending on how and where the EPU-4562/4462 is mounted in the
end user system.
VL-EPU-4562/4462 Reference Manual 64
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Thermal Considerations
At this temperature, the CPU cores throttle back to a lower speed. This
speed.
At this temperature, the operating system typically puts the board into a
sleep or other low-power state.
The CPU turns itself off when this temperature is reached. This is a fixed
trip point and cannot be adjusted.
Notes:
2. The default value in the BIOS Setup utility for this trip point is 100 ºC.
The decision which thermal solution to use relies on several factors including:
Number of CPU cores in the SoC (single, dual, or quad)
CPU and video processing utilization by the user application
Temperature range within which the EPU-4562/4462 will be operated
Air movement (or lack of air movement)
Most of these factors involve the demands of the user application on the EPU-4562/4462 and
cannot be isolated from the overall thermal performance. Due to the interaction of the user
application, the Blackbird thermal solution, and the overall environment of the end system,
thermal performance cannot be rigidly defined.
The ambient air surrounding the EPU-4562/4462 needs to be maintained at 85 ºC or below. This
would include the space between the two main boards as well as the space beneath an installed
Mini PCIe expansion board. Standard methods for addressing this requirement include the
following:
Provide a typical airflow of 100 linear feet per minute (LFM) / 0.5 linear meters per second
(as described in the section titled EPU-4562/4462 Thermal Characterization, beginning on
page 68) within the enclosure
Position the EPU-4562/4462 board to allow for convective airflow
Lower the system level temperature requirement as needed
CPU Thermal Trip Points
The CPU cores in the Blackbird have their own thermal sensors. Coupled with these sensors are
specific reactions to three thermal trip points. The table below describes the three thermal trip
points. Note that these are internal temperatures that are about 10 ºC above the heat plate
temperature.
Table 22: CPU Thermal Trip Points
Trip Point Description
Passive (Note 1)
Critical (Note 2)
Maximum core temperature
1. The default value in the BIOS Setup utility for this trip point is 90 ºC.
reduces the power draw and heat dissipation, but lowers the processing
These trip points allow maximum CPU operational performance while maintaining the lowest
CPU temperature possible. The long-term reliability of any electronic component degrades when
it is continually run near its maximum thermal limit. Ideally, the CPU core temperatures will be
kept well below 100 ºC with only brief excursions above.
VL-EPU-4562/4462 Reference Manual 65
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Thermal Considerations
Operating System
Program Type
Description
Linux
lm-sensors
http://en.wikipedia.org/wiki/Lm_sensors
CPU temperature monitoring programs are available to run under both Windows and Linux. The
next table lists some of these hardware monitoring programs.
Open Hardware Monitor http://openhardwaremonitor.org/
VL-EPU-4562/4462 Reference Manual 66
Page 67
Thermal Considerations
With Heat Sink
(HDW-417)
With Heat Sink + Fan
(HDW-417 + HDW-418)
4562/4462
EBP
VL-EPU-4562/4462
ECP
Integrator’s Note: The ambient air surrounding the EPU-4562/4462needs to be
maintained at 85 °C or below.
Thermal Specifications, Restrictions, and Conditions
Graphical test data is in the section titled EPU-4562/4462 Thermal Characterization, beginning
on page 68. Refer to that section for the details behind these specifications. These specifications
are the thermal limits for using the EPU-4562/4462 with one of the defined thermal solutions.
Due to the unknown nature of the entire thermal system, or the performance requirement of the
application, VersaLogic cannot recommend a particular thermal solution. This information is
intended to provide guidance in the design of an overall thermal system solution.
Table 24: Absolute Minimum and Maximum Air Temperatures
Board With Heat Plate
VL-EPU-
-40 ° to +85 °C -40 ° to +85 °C -40 ° to +85 °C
-40 ° to +85 °C -40 ° to +85 °C -40 ° to +85 °C
Overall Restrictions and Conditions:
Ranges shown assume less than 90% CPU utilization.
Keep the maximum CPU core temperature below 100ºC.
The ambient air surrounding the EPU-4562/4462 needs to be maintained at 85 ºC or below.
This includes the space between the two main boards as well as the space beneath an
installed Mini PCIe expansion board. A recommended overall airflow of 100 linear feet per
minute (LFM) / 0.5 linear meters per second (LMS) addresses this requirement. If this air
flow is not provided, other means must be implemented to keep the adjacent air at 85 ºC or
below.
Heat Plate Only Restrictions and Conditions:
The heat plate must be kept below 90 °C. This applies to a heat plate mounted directly to
another surface as well as when the HDW-408 heat pipe block is used.
Heat Sink Only Considerations:
At 85°C air temperature and 90% CPU utilization, there will be little if any thermal margin
to a CPU core temperature of 100 °C or the passive trip point (see test data). If this is the use
case, consider adding a fan or other additional airflow.
Heat Sink with Fan Considerations:
The heat sink and fan combination cools the CPU when it is running in high temperature
environments, or when the application software is heavily utilizing the CPU or video
circuitry. The fan assists in cooling the heat sink and provides additional air movement
within the system.
VL-EPU-4562/4462 Reference Manual 67
Page 68
EPU-4562/4462 Thermal Characterization
EPU-4562/4462 (Blackbird) dual/quad core CPU with:
USB keyboard and mouse (Note)
Critical thermal trip point setting: 111 ºC
Operating system
Microsoft Windows* 10 Enterprise
- Primarily used to read the CPU core temperature
The EPU-4562/4462 board underwent the following thermal characterization tests:
Test Scenario 1: Core i5 EPU-4562-EBP – active and passive thermal characterization.
Test Scenario 2: Core i7 EPU-4562-ECP – active and passive thermal characterization.
The table below describes the thermal testing setup for the board.
Table 25: EPU-4562/4462 Thermal Testing Setup
16 GB of DDR4 DRAM
HDW-417 (passive heat sink)
HDW-418 (heat sink fan)
One VGA display device (connected through the LVDS interface), one
Hardware
configuration
display for monitor
Two SATA hard disk drives
Two RS-232 ports in loopback configuration
One VersaLogic VL-MPEe-E3 Mini PCIe Gigabit Ethernet module
Two active Ethernet ports in loopback configuration
Two USB 2.0 ports in loopback configuration (Note)
Thermal Considerations
BIOS
Test software
Test environment
Note: This device connects through a VersaLogic VL-CBR-4005B paddleboard.
The test results reflect the test environment within the temperature chamber used. The airflow of
this particular chamber is about 0.5 linear meters per second (~100 linear feet per minute).
Thermal performance improves by increasing the airflow beyond 0.5 linear meters per second.
The system power dissipation is primarily dependent on the application program; that is, its use
of computing or I/O resources. The stress levels used in this testing are at the top of the range of
a typical user’s needs.
ID string: VER2A000
Passive thermal trip point setting: 105 ºC
Passmark BurnIn* Test v8.1 b1018
- CPU utilization ~90%
Intel Thermal Analysis Tool* (TAT) v5.0.1026
Thermal chamber
VL-EPU-4562/4462 Reference Manual 68
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Thermal Considerations
Test Results
Test Scenario 1: Dual Core EPU-4562-EBP – Passive and Active Thermal Characterization
Shown in in the figure below, running the test scenario with just the heat sink, the core
temperature is slightly above 100 ºC at maximum ambient temperature. This will be less in most
applications that require less than 90% CPU utilization. Adding the fan provides an additional 56 ºC of margin. For long-term reliability, ensure the CPU cores are predominately running with
their temperatures below 100 ºC.
Figure 32. EPU-4562-EBP Quad Core Temperature Relative to Ambient Temperature
VL-EPU-4562/4462 Reference Manual 69
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Thermal Considerations
Test Scenario 2: Core i7 EPU-4562- ECP – Passive and Active Thermal Characterization
As shown below, the quad core version of the Blackbird will typically require a heat sink + fan
for operation above 80 ºC, at >90% CPU utilization.
Figure 33. EPU-4562-ECP Quad Core Temperature Relative to Ambient Temperature
VL-EPU-4562/4462 Reference Manual 70
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Thermal Considerations
Installing VersaLogic Thermal Solutions
The following thermal solution accessories are available from VersaLogic:
VL-HDW-401 Thermal Compound Paste – used to mount the heat sink to the heat plate
VL-HDW-417 Passive Heat Sink – mounts to standard product.
VL-HDW-418 Fan Assembly – Cooling fan for the HDW-417 passive heatsink. Operates at
+12 V and includes an EPU-4562/4462 compatible connector
VL-HDW-408 Heat Pipe Block – mounts to heat plate
Hardware Assembly
There are two basic assembly methods:
Heat plate down (in relation to the enclosure)
Heat plate up
These assembly methods are shown in Figure 35 and Figure 36 respectively.
Heat Plate Down
The figure below (a representative image of a similar VersaLogic product) shows the assembly.
Use this assembly method if you are attaching the Blackbird to a larger thermal solution such as a
metal chassis/enclosure.
Figure 34. Hardware Assembly with Heat Plate Down
A thermal interface compound must be applied to the heat plate to thermally bond it to the
mounting plate or other surface to which the Blackbird is mounted. Spread the compound thinly
and evenly across the entire heat plate surface before mounting. The compound is supplied in the
VL-CKR-BLACKBIRD cable kit or sold separately as part number VL-HDW-401.
VL-EPU-4562/4462 Reference Manual 71
Page 72
Thermal Considerations
Installing the VL-HDW-417 Passive Heat Sink
1. Apply the Arctic Silver* Thermal Compound (VL-HDW-401)
Apply the thermal compound to the heat plate using the method described on the Arctic
Silver website - http://www.arcticsilver.com/
2. Position the passive heat sink
Using the next figure as a guide, align the seven mounting holes of the heat sink with the
heat plate.
Orient the heat sink fins in the direction of the system airflow to maximize CPU cooling.
3. Secure the passive heat sink to the heat plate
Affix the passive heat sink to the heat plate using seven M2.5 pan head screws.
Using a torque screwdriver, tighten the screws to 4.0 inch-pounds.
Figure 35. Installing the Passive Heat Sink
VL-EPU-4562/4462 Reference Manual 72
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Thermal Considerations
Installing the VL-HDW-418 Heat Sink Fan
1. Position the fan assembly
Using the figure below as a guide, align the mounting holes of the heat sink fan with the
four holes in the passive heat sink. Position the fan so that its power cable can easily
reach its mating connector (J18).
2. Secure the fan to the heat sink
Affix the heat sink fan using four M3 pan head screws.
Using a torque screwdriver, tighten the screws to 4.0 inch-pounds.
3. Connect power to the fan
Connect the fan’s power cable to J18 on the EPU-4562/4462.
Figure 36. Installing the Heat Sink Fan
VL-EPU-4562/4462 Reference Manual 73
Page 74
13
KNOWN ISSUES
Operating Systems
In Linux, a dual-display configuration (using both the LVDS and the Mini DisplayPort++
connectors) will fail to show output on the LVDS port unless the operating system is
configured to boot in UEFI mode. Single display configurations do not have an issue.
In Ubuntu 14.04, if an LVDS monitor goes into power saving mode or the operating system
goes into suspend or hibernate mode, the LVDS monitor will fail to come back on.
*** End of document ***
VL-EPU-4562/4462 Reference Manual 74
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