• Product is compliant to RoHS directive
and fully compatible with lead free assembly
Applications
• SONET/SDH/DWDM
• Ethernet, Gigabit Ethernet
• Storage Area Network
• Digital Video
• Broadband Access
• Microprocessors/DSP/FPGA
Description
Vectron’s VCC1 Crystal Oscillator (XO) is quartz
stabilized square wave generator with a CMOS
output, operating off either a 1.8, 2.5, 3.3 or a 5.0
volt supply.
f
o
The VCC1 is uses fundamental or 3rd overtone
crystals resulting in low jitter performance,
typically 0.5pS rms in the 12 kHz to 20MHz
band. Also a monolithic IC, which improves
reliability and reduces cost, is hermitically
sealed.
Frequency fO 0.012 189.000 MHz
Operating Supply Voltage 1 VDD 2.97 3.3 3.63 V
Absolute Maximum Operating Voltage -0.5 5.0 V
Supply Current, Output Enabled
IDD
< 1.500 MHz
1.5 to 20 MHz
20.01 to 50 MHz
50.00 to 85 MHz
85.01 to 189 MHz
Supply Current, Out put disabled IDD 30 uA
Output Logic Levels
Output Logic High2
Output Logic Low
2
Output Logic High Drive
Output Logic Low Drive
Output Rise/Fall Time2
VOH
V
OL
I
OH
IOL
tR/tF
< 1.00 MHz
1.00 to 20.00 MHz
20.01 to 50.00 MHz
50.01 to 90.00 MHz
90.01 to 189.00 MHz
Duty Cycle3 (ordering option) SYM 45/55 %
Operating temperature (ordering option) -10/70 or –40/85 °C
Stability4 (ordering option) ±20, ±25, ±32, ±50, ±100 ppm
RMS Jitter, 12kHz to 20 MHz 0.5 1 ps
RMS Jitter 2.5 ps
Output Enable/Disable
5
Output Enabled
Output Disabled
Internal Enable Pull-Up resistor5 100 Kohm
Start-up time 10 ms
1. A 0.01uF and a 0.1uF capacitor should be located as close to the supply as possible (to ground) is recommended.
2. Figure 3 defines these parameters. Figure 4 illustrates the operating conditions under which these parameters are tested and
specified. For Fo>90MHz, rise and fall time is measured 20 to 80%.
3. Symmetry is measured defined as Vs, On Time/Period.
4. Includes calibration tolerance, operating temperature, supply voltage variations, aging and shock and vibration (not under
operation).
5. Output will be enabled if enable/disable is left open.
Under normal operation the Enable/Disable is left open or set to a logic high state. When the E/D is set to a
logic low, the oscillator stops and the output is in a high impedance state. This helps reduce power
consumption as well as facilitating board testing and troubleshooting.
TriState Functional Description
Under normal operation the Tristate is left open or set to a logic high state. When the Tri-State is set to a
logic low, the oscillator remains active but the output buffer is in a high impedance state. This helps facilitate
board testing and troubleshooting.
Outline Diagrams, Pad Layout and Pin Out
Pin # Symbol Function
1 E/D or NC Tristate, Enable/Disable or NC
2 GND Electrical and Case Ground
3 fO Output Frequency
4 VDD Supply Voltage
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional
operation is not implied at these or any other conditions in excess of conditions represented in the
operational sections of this data sheet. Exposure to absolute maximum ratings for extended periods may
adversely affect device reliability.
Table 6. Absolute Maximum Ratings
Parameter Symbol Ratings Unit
Storage Temperature Tstorage -55/125 °C
Reliability
The VCC1 qualification tests have included:
Table 7. Environnemental Compliance
Parameter Conditions
Mechanical Shock MIL-STD-883 Method 2022
Mechanical Vibration MIL-STD-883 Method 2007
Temperature Cycle MIL-STD-883 Method 1010
Solderability MIL-STD-883 Method 2003
Gross and Fine Leak MIL-STD-883 Method 1014
Resistance to Solvents MIL-STD-883 Method 2015
Handling Precautions
Although ESD protection circuitry has been designed into the the VCC1, proper precautions should be taken
when handling and mounting. VI employs a Human Body Model and a Charged-Device Model (CDM) for
ESD susceptibility testing and design protection evaluation. ESD thresholds are dependent on the circuit
parameters used to define the model. Although no industry wide standard has been adopted for the CDM, a
standard HBM of resistance = 1.5kohms and capacitance = 100pF is widely used and therefore can be
used for comparison purposes.
Devices are built using lead free epoxy and can also be subjected to standard lead free IR reflow conditions,
Table 9 shows max temperatures and lower temperatures can also be used e.g. peak temperature of 220C.
Table 9. Reflow Profile (IPC/JEDEC J-STD-020B)
Parameter Symbol Value
PreHeat Time
Ramp Up
t S 150 sec Min, 200 sec Max
R
3 oC/sec Max
UP
Time Above 217 oC t L 60 sec Min, 150 sec Max
Time To Peak Temperature
Time At 260 oC (max)
Time At 240 °C (max)
Ramp Down
A: ±100ppm, -10 to 70C
C: ±100ppm, -40 to 85C
B: ±50ppm, -10 to 70C
D: ±50ppm, -40 to 85C
K: ±32ppm, -10 to 70C
O: ±32ppm, -40 to 85C
E: ±25ppm, -10 to 70C
F: ±25ppm, -40 to 85C
G: ±20ppm, -10 to 70C
USA: Vectron International • 267 Lowell Road, Hudson, NH 03051