Page 1
rnOtl-i:=t304=tD
U)iS=I)
mAnUAL
Page 2
Page 3
REPAIR
AGREEMENT
The
Motherboard
without
implied
However,
period
replace
or
workmanship,
the
defect
INC.,
to
confirm
replacement
Repair,
any
warranty,
warranty
the
above
of
ninety
any Motherboard
1.
Such
Motherboard
2.
VECTOR
claimed
3.
The Mbtherboard
at
customer's
the
if
replacement
workmanship
forth
expense,
expense,
correction.
expiration
addition
repair
the
thereafter.
of
the
subnit
GRAPHIC,
estimate
INC.,
GRAPHIC,
GRAPHIC,
above
rate.
first
defects
period
to
signed
will
provided
to
In
of
to
the
hour,
Prior
in
for
Buyer a
INC.,
of
charges
INC.,
INC.,
any Motherboard
approval
require
to
proceed,
prepayment
work.
sold
hereunder
either
of
fitness
notwithstanding,
(90) days
provided:
defect
left
the
GRAPHIC,
within
ten
expense,
alleged
found
to
or
which
are
be
performed
the
VECTOR
~rforming
the
cost
At
and
material
GRAPHIC,
period
of
the
present
$18.00
to
commencing any
or
no-cost-to-Buyer
written
will
not
has
by
duly
to
shall
until
authorized
commence
have
the
and
of
the
is
expressed
for
following
that
in
is
material
VECTOR
found
GRAPHIC,
INC.,
(10)
days
is
promptly
for
examination
defect,
be
in
order.
correction
discovered
by
Motherboard
INC.,
any
repair,
set
forth
parts
the
then-current
time
per
hour
~rkmanship
estimate
commence
been
with
no
repair
returned
the
obligation
written
VECTOR
GRAPHIC,
estimated
sold
lias
or
intended
VECI'OR
use
GRAPHIC,
delivery
to
contain
or
workmanship
INC.,
is
given
after
its
returned
and
for
of
any
defects
after
VECTOR
is
returned,
for
expiration
GRAPHIC,
such
replacement
above,
tpe
applicable
for
every
repair,
replacement
discovered
repairs,
of
the
VECTOR
ex~cted
until
by
Buyer
representative
repair
to
repair,
estimate
INC.,
repair
charges
lt
is
,
with
implied,
or
merchantability.
INC.,
to
customer,
defects
existed
factory;
notice
discovery;
to
VECTOR
by
VECTOR
subsequent
of
INC.,
also
repair,
or
Buyer
will
VECTOR
rate
hour
of
after
GRAPHIC,
charges,
such time
to
VECTOR
authorizing
work
involved.
replace
has
been
may
at
prior
all
faults
including
will,
repair
-in
materials
at
of
the
GRAPHIC,
GRAPHIC,
repair
in
material
the
period
at
at
Buyer's
replacement
correction
be
charged
GRAPHIC,
is
$35.00
work
required
or
correction
expiration
INC.,
and
as
the
GRAPHIC,
or
returned
its
option
to
commencing
and
any
for
the
time
precise
INC.,
set
Buyer's
after
INC.,
for
will
VECTOR
written
VECTOR
VECTOR
correct
with
also
a
or
or
or
or
in
of
Repair
Agreement
GRAPHIC,
INC.
void
within
if
ten
the
(10)
enclosed
days
of
card
is
not
end consumer
returned
purchase.
to
VECTOR
Page 4
Page 5
VECTOR1MOrHERBOARD
SUBJECT
PARTS
LIST
FEATURES
PARTS
S-100
WARRANTY
(]rY.
LAYOUT
BUS
DRAWING
LISTING
DESCRIPI'ION
TABLE
PARI'S
OF
CONTENTS
LIST
PAGE
BELOW
1
1
2
41
41
1
2
1
1
1
PRINTED
820
100
OHM
~
CIRCUIT
1
2
7805/340T-5
*6-
32X3/8
330
OHM
1/4
470
OHM
1/4
BOARD
WATl'
WATl'
RESISTORS (STRIPES
RESISTORS (STRIPES
REGULATOR
SCRE.W,
WATl'
WATT
NUT
AND
LOCKWASHER
RESISTORS (STRIPES
RESISTORS (STRIPES
OF
GRAY,
OF
:BRa'JN,
OF
ORANGE, ORANGE,
OF
YELLCW,
RED,
BLACK,
BRCWN)
BRCMN)
VIOLET,
BRCWN)
:BR.CMN)
Page 6
MOrHERBOARD
USERS
MANUAL
THE VECTOR 1
STRUCTURE
AND
AVAILABLE.
IN
ACCORDANCE
STANDARDS
AND
TERMINATORS.
NOISE
WITH
IMMUNITY,
SO
CALLED
FEATURES
MOST
CAN
:EOSITIONS
:EQPULAR
BE
USED
'IO
FOR
ACCEPl'S EITHER
MOST
0.75"
:EQPULAR
CENTER
MOTHERBOARD
IS
DESIGNED
WITH
TOP
WITH
"ACTIVE"
VECTOR
QUALITY
THE
BUS
TERMINATION
INCREASED
TERMINATORS,
"ALTAIR/IMSAI"
RETROFIT
18
.125"
SOLDER
0.25"
'ID
CENTER
YOUR
X
PINS
CENTER
SPACING
0.25"
HAS
TO
GRAPHIC
PRODUCTS,
S-100
SECTIONED
100
OR
WIRE
'IO
CENTER
BE'IWEEN
18
SLOTS,
PROVIDE A
INC.'S
OUR
USE
OF
IS
BASED
NUMBER
COMMITMENT
MOl'HERBOARDS
LCltJ
EaVER SCHDrrKY TTL
BECOMESADESIRABLE
FULL
BUS
PIN
WRAP
SPACING
TIME
STRUcrtJRE
ALTAIR
EDGE
PINS
TERMINATION
MOI'HERBOARD
CONNECTORS
BE~EN
CONNECIDRS
ON
OF
FEATURES
ARE
FEATURE.
PIN
THE
TO
ROilS
POPULAR
NOT
S-100
PREVIOUSLY
HIGH PERFORMANCE
NOil
SUPPLIED
AND
Nor
IS
PROVIDED.
TO
ITS
BE
w-rTH
REDUCED
CONFUSED
BUS
BUS
EXTRA
FULL
PLATED
TRACES
LESS
HEAVY
GROUNDPLANE
THROUGH
CN
RISK
OPERATION
MUCH
EASIER'ID
REDUCED
SOLDER
BUS
l?C:WER
BOARD
MASKEDroREDUCE
TERMINATION
RATING:
SIZE
0.93"
WARP
REDUCES
HOLES
BPl.CKOFBOARD
OF
SHORTS
TROUBLE
CAPACITANCE
20AFOR
IS"
X
8.5"
RESISTANT,
mISE
FOR
MORE
CNLY
FROM
SHOOT
BE'IWEEN
RISK
+8
AEROSPACE
CN
BUS
RELIABLE
LINES
CONNECTIONS
QUALITY
CONDUCTIVE ITEM BEING
TRACES
OF
VOLT
SOLDER
TRACE;
BRIDGES
25AFOR
DURING
G-10
INADVERTENTLY
ASSEMBLY
+16V
TRACES
E:EQXY
BOARD
DROPPED
DURING
PAGE
Page 7
~,
5-
MOTHERBOARD
BOTTOM
OPTIONAllYOlTAGE
REGULATOR
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Page 8
MOI'HERBOARD
THE
TERMINA'IDRS PROVIDED
GNU)
•
USERS
MANUAL
ARE
330
BUS
TERMINATION
OHM
RJLL-UP
(TO
+5V)
AND
470
OHM
RJLL-DOWN
(TO
24
- 2
25
- 1
29-AS
30
-
A4
31-A3
32
- Al5
33
- Al2
34 -
A9
35 -
001
36-DOO
37
-
AlO
TABLE
38 -
LINES
004
TERMINATED
39-DOS
40
-
006
41
- 012
42
- 013
43 - 017
47
-
SMEMR
49-CLK
54
- EXT CLR
68-MWRITE
1
76 -
PSYNC
77-BNR
78 - IDBIN
79 -
AO
80
- Al
81
- A2
82 -
A6
83 -
A7
84 - A8
85
- AI3
86-A14
87-All
88 -
002
89 - D03
90 -
007
91
- 014
92
- DIS
93
- 016
94
-
011
95
- 010
PAGE
3
Page 9
[!EE
.0
••
2 3
o 0
00
52
,
-~~~~-------------~
-
----
53
.........
-----,----
---
48
o 0
98 99
49
o
-
3 4
'-0
- 0 0
53
54
••
--~--_
••••••
GND
....
----.--...-
.....
-~_
.....
---
48 49
0·.
98
.
99
PAGE
..-
....
~
o
f
..
4
Page 10
1.
2.
+8V
+16V
UNREGULATED
UNREGULATED
S-100
INPUT
INPUT
BUS
TO
TO
+5V
REGULATORS
+12V
REGULATORS
10.
II.
12.
13.
14.
15.
5.
6.
7.
8.
9.
3.
4.
XRDY
'1710
VII
VI2
'1713
'1714
VIS
VI6
'1717
XRDY2
ANDED
VECTORED
VECTORED
YECTORED
VECTORED
VECTORED
WITH
PRDY
AND
GOES
INTERRUPT REQUEST 0
INTERRUPT REQUEST 1
INTERRUPT REQUEST 2
INTERRUPT REQUEST 3
INTERRUPT REQUEST 4
TO
VECTORED INTERRUPT REQUEST 5
VECTORED INTERRUPT REQUEST 6
VECTORED INTERRUPT REQUEST 7
8080
RDY
16.
17.
18.
19.
20",
21.
22.
23.
24"
25"
26"
STA DSB
cJc
DSB
UNPROT
SS
ADD
DSB
DO
DSB
if/2
ifll
PHLDA
STATUS BUFFER
DISABLE
COMMAND/CONTROL BUFFER
INPUT
INDICATES
ADDRESS BUFFER
DATA
PHASE
PHASE
HOLD
TO
MEMORY
MACHINE
PROTECT
IS
DISABLE
OUT
(FROM CPU) BUFFER
TWO
CLOCK TTL LEVELS
ONE
CLOCK
TTL LEVELS
ACKNOWLEDGE. BUFFERED
DISABLE
CIRCUITRY
IN
SINGE
STEP
DISABLE
8080
OUTPUT
ON
MODE
MEMORY
BOARD
PAGE
5
Page 11
27.
PWAIT
WAIT
ACKNOWLEDGE,
BUFFERED
8080
OUTPUT
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
PINTE
A5
A4
A3
A15
A12
A9
DOl
DOO
AIO
D04
DOS
INTERRUPT ENABLE, BUFFERED
BUFFERED ADDRESS
BUFFERED ADDRESS
BUFFERED ADDRESS
BUFFERED ADDRESS
BUFFERED ADDRESS
BUFFERED ADDRESS
BUFFERED
BUFFERED
BUFFERED- ADDRESS
BUFFERED
BUFFERED
DATA
DATA
DATA
DATA
OUT
OUT
OUT
OUT
LINE
LINE
LINE
LINE
LINE
LINE
LINE
LINE
LINE
LINE
LINE
S
4
3
15
12
1
10
(32)
(16)
(8)
(2)
1
a
4
5
8080
(32768)
(4096)
(1024)
OUTPUT
40.
42.
43.
44.
45.
46.
47.
48.
49.
50.
,
51.
52.
D06
DI2
DI3
DI7
SMI
SOUT
SINP
SMEMR
SHLTA
CLOCK
GND
+8V
-16V
BUFFERED
DATA
DATA
DATA
LATCHED
LATCHED
LATCHED
LATCHED
LATCHED
2
MHZ
LOGIC
UNREGULATED INPUT
UNREGULATED INPUT
DATA
INPUT
INPUT
INPUT
8080
8080
8080
8080
8080
CLOCK, CRYSTAL CONTROLLED
AND
OUT
LINE
LINE
LINE
POWER
2
3
7
MI
STATUS
OUT
INP
MEMR
HLTA STATUS
GROUND
LINE
STATUS
STATUS
STATUS
TO
TO
6
RETURN
+5V REGULATORS
NEGATIVE REGULATORS
54.
SSW
EXT
DSB
CLR
SENSE SWITCH DISABLE
CLEAR SIGNAL
FOR
I/O
DEVICES
PAGE
6
Page 12
55.
RTe
REAL
TIME
CLOCK
OR
48K FAST RESET
56.
'57.
01.
62.
63.
64.
65.
66.
67.
STSTB
DIGI
FRDY
48K REFRESH
PRANTOM
STROBE SIGNAL
ENABLE
880013
SIGNAL
FRONT
(BY
FOR
PANEL
8224
CPU
READY
CLOCK
DI
DRIVERS
SIGNAL
CHIP
8800B
8800B
Dlc
BOARD)
68.
69.
70.
71.
72.
73"
74.
75.
76.
77.
18
19.
..
MWRT
PS
PROT
RUN
PRDY
PTI'fT
PHOLD
PRESET
PSYNC
PWR
PDBIN
AO
WRITE
INDICATES
HiPUT
INDICATES
AND
HTPUT
INPUT
CLEAR
BUFFERED
BUFFERED
BUFFERED
BUFFERED ADDRESS
ED
ENABLE
IF
MEMORY
TO
MACHINE
WITH
8080
TO
TO
8080
SIGNAL
8080
8080
8080
SIGNAL
ADDRESSED
X"~DY
HOLD
FOR
FOR
MEMORY
MEMORY
PROTECT
IS
AND
INTERRUPT REQUEST
REQUEST
CPU
SYNC
WRITE
BDIN SIGNAL
SIGNAL
LINE
CIRCUITRY
IN
RUN
GOES
ENABLE
a
TO
(1)
MODE
8080
SIGNAL
PROTECTED
IS
ON
RDY
MEMORY
BOARD
80.
81.
82.
Al
A!
A6
BUFFERED ADDRESS
BUFFERED
BUFFERED
ADDRESS
ADDRESS
LINE
LINE
LINE
(2)
1
(4)
2
(64)
6
PAGE
7
Page 13
83.
84.
Ai
A8
BUFFERED
BUFFERED
ADDRESS
ADDRESS
LINE
LINE
i
8
(128
(256)
)
85.
86.
87.
88.
89.
90.
91.
92.
93.
94.
95.
96.
97-
A13
A14
All
DOZ
BUFFERED
BUFFERED
BUFFERED
BUFFERED
D03 BUFFERED
DOi
1'14
DIS
D16
DIl
DIO
SINTA
sUO
BUFFERED
DATA
DATA
DATA
DATA
DATA
INPUT
INPUT
INPUT
INPUT
INPUT.
LATCHED
LATCHED
AnnRES S
ADDRESS
LINE
LHTE
ADDRESSLINE
LINE
LINE
LINE
LINE
LINE
LINE
INTA
ilO
OUT
OU~
OUT
4
5
6
1
a
STATUS
LINE
LINE
DATA
DATA
DATA
8080
8080
13
14
11
STATUS
(8192)
(16384)
(2048)
2
3-
7
98.
99.
100.
Q •
SSTACK
PO'C
GND
PHI
LATCHED
La
DURING
LOGIC
8080
AND
STACK
POWER
FmlER
STATUS
UP,
RESET
GROUND
RETURN
PAGE
8
Page 14
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