Vector Graphic Bitstreamer II User Manual

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JI
U)E=I) mAnUAL
BITSTREAMER II BOARD
Revision 1
Revision A
January
1, 1980
Copyright
198~ by
Vector Graphic Inc.
All rights reserved.
Disclaimer Vector Graphic makes no representations or warranties with respect to the contents of this manual itself, \\bether or not the product it describes is
covered
by
a warranty or repair agreement. Further, Vector Graphic reserves the right to revise this publication and to make changes from time to time in the content hereof without obligation of Vector Graphic to notify any
person of such revision or changes, except \\ben an agreement to the contrary exists.
Revisions The date and reV1Slon of each 'page herein appears at the bottom of each page. The revision letter such as A or B changes if the MANUALhas been.
improved but the PRODUCTitself has not been significantly modified. The
date and revision on the Title Page corresponds to that of the page most
recently revised. When the product itself is modified significantly, the
product will get a new revision number, as shown on the manual's title page, and the manual will revert to revision A, as if it were treating a brand new product. EAai MANUALSHOULDONLYBE USEDWITHTHEPRODOCTIDENTIFIEDONTHE
TITLE PAGE.
'Ibe Bitstreamer II Board sold hereunder is sold "as is", with all faults and without any warranty, either expressed or implied, including any implied warranty of fitness for intended use or merchantability. However, the above
notwithstandi1'l3,VEC1'OR GRAPHIC, INC. ,will, for a period of ninety (90) days following delivery to customer, repair or replace any Bitstreamer II Board that is found to contain defects in materials or workmanship, provided:
1. Such defect in material or workmanship existed at the time the
Bitstreamer II Board left the VECTOR GRAPHIC, INC., factory;
2. VECTOR GRAPHIC, INC., is given notice of the precise defect
claimed within ten (10) days after its discovery;
3. The Bitstreamer II Board is promptly returned to VECTOR GRAPHIC,
INC., at customer's expense, for examinationbyVECTOR GRAPHIC, INC., to
confirm the alleged defect, and for subsequent repair or replacement if
found to be in order.
Repair, replacement or correction of any defects in material or workmanship
which are discovered after expiration of the period set forth above will be
performed
by
VECTOR GRAPHIC, INC., at Buyer's expense, provided the
Bitstreamer II Board is returned, also at Buyer's expense, to VECTOR
GRAPHIC, INC., for such repair, replacement or correction. In performing
any repair, replacement or correction after expiration of the period set forth above, Buyer will be charged in addition to the cost of parts the
then-current VECTOR GRAPHIC, INC., repair rate. At the present time the applicable rate is $35.00 for the first hour, and $18.00 per hour for every hour of work required thereafter. Prior to commencing any repair,
replacement or correction of defects in material or workmanship discovered
after expiration of the period for no-cost-to-Buyer repairs, VECTOR GRAPHIC,
INC., will submit to Buyer a written estimate of the expected charges, and
VECTOR GRAPHIC, INC., will not commence repair until such time as the written estimate of charges has been returned by Buyer to VECTOR GRAPHIC,
INC., signed by duly authorized representative authorizing VECTOR GRAPHIC, INC., to corrunence
wit.11
the repair work involved. VECTOR GRAPHIC, INC.,
shall have no obligation to repair, replace or correct any Bitstreamer II
Board until the written estimate has been returned with approval to proceed,
and VECTOR GRAPHIC, INC., may at its option also require prepayment of the
estimated repair charges prior to c~ncing work.
Repair Agreement void if the enclosed card is not returned to VECTOR
GRAPHIC, INC. within ten (10) days of end consumer purchase.
This manual is intended for computer distributors, or others with at least a moderate technical knowledgeof small computers.
It will describe what the Vector Graphic Bitstreamer II Board does in the context of a computer system, howto use the board
both in Vector Graphic and in other
5-10(3
systems, and howthe board circuitry ¥.Orks.
Each section is written at a uniform level of technical depth. "Perspective" describes
WHATthe board does and requi res only a
rooderate knowledgeof computer design. Most other sections tell
HCNl
to makeit do
things and assl1!t"esthe same level of knowledge, plus the ability to solder
jumpers and flip switches. "Theory of
Operation" discusses WHYthe board ¥.Orks and assumesa knolwedgeof digital
electronics.
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.1".1
1.11
Introduction ••••••••••••••••••••••••••••••••••••••••••••••• 1-1
Serial channels generally •••••••••••••••••••••••••••••••••• 1-1 Serial asynchronous communication •••••••••••••••••••••••••• 1-2 Serial synchronous communication ••••••••••••••••••••••••••• 1-2
Interrupt driven serial channels ••••••••••••••••••••••••••• 1-3
RS-232C theory ••••••••••••••••••••••••••••••••••••••••••••• 1-4
RS-232C on the Bitstreamer II •••••••••••••••••••••••••••••• 1-5 2~
mA current
loop•••••••••••••••••••••••••••••••••••••••••
1-7
Real time clock interrupts ••••••••••••••••••••••••••••••••• 1-7 Interrupt vectors and priority ••••••••••••••••••••••••••••• 1-8
Parallel channels •••••••••••••••••••••••••••••••••••••••••• 1-9
Table 1 - Board Address Jumpers •••••••••••••••••••••••••••• 2-2 Table 2 - Functions of I/O Addresses and Connectors Used •••2-2
2.2 Asynchronous serial baud rate selection •••••••••••••••••••• 2-3
2.3 How to connect most RS-232C serial terminals and printers ••2-4
2.4 .How to connect many low speed asynchronous acoustic
couplers and modems ••••••••••••••••••••.••••••••••••••••••• 2-7
2.5 Connecti~ additional RS-232C handshakill3 lines •••••••••••• 2-8 Table 3 - RS-232C and Connections on Bitstreamer II Board ••2-9
Table 4 - Jumper Areas for Each Serial Channel ••••••••••••• 2-ll Table 5 - 8251 Pins in Jumper Areas •••••••••••••••••••••••• 2-l1
Table 6 - RS-232C Lines Available in Jumper Areas, and
Pads Connected to +12 VDC •••••••••••••••••••••••• 2-12
Table 7 - Installill3 a 1488 Quad Line Driver or a
1489 Quad Line Receiver, in a Spare Socket ••••••• 2-l4
2.6 How to connect 20 IDA current loop •••••••••••••••••••••••••• 2-l5
2.7 How to modify the board to generate interrupts ••••••••••••• 2-l5 Table 8 - Interrupt Jumper Pads and Mask Bits •••••••••••••• 2-l5
Table 9 - 8~80 Restart Instructions and Jumpering •••••••••• 2-l7 Table 10- Data Bus Bytes Generatedbya Jumper in Area L •••2-18 Table 11- VI Lines Available in Area K ••••••••••••••••••••• 2-l9
Table 13- Spare Inverters in U2l ••••••••••••••••••••••••••• 2-2l Table 14- Spare Open Collector NAND Gates in Chip U10 •••••• 2-2l
III. Theory of Operation
3.1 Serial
cha.nn.els •••••••••••••••••••••••••••••••••••••••.•••••
3-1
3.2 Parallel input channels •••••••••••••••••••••••••••••••••••• 3-l
3.3 Parallel output channels ••••••••••••••••••••••••••••••••••• 3-2
3.4 Interrupts•••.••.•••••••.•••••.•••••••.•.•.••••.•..•••••.•.3-2
Board layout Schematic errata Schematic
Purpose Multiple serial and parallel input/ouput. Compatibility S-1~0 systems. serial channels 3, using
8251
controller chips.
Channel addresses x2 and x3, x4 and x5, x6 and x7 where x is any digit
o
to 7. Prewired x is 0. (Each serial channel uses
two I/O addresses.) Signal levels EIARS-232C,or 201Mcurrent loop on one channel only. RS-232handshaking Lines 5, 6, and 8 are held high.
Other handshaking lines are not connected
.Jumperpads are provided to connect than.
There is one spare recevier and one spare driver for
handshaking lines on board that can be connected by
jumper. '!here are two spare slots if rooreare needed.
Can be wired for internal or external gynch.
8251 SYNDETline is not connected.
Not nowconnected to the external ~rld as required
for synchronous operation.
Single or double synch character can be programmedfor
each channel independently.
TTL
(input
= 1 'ITL
load; output drives 5
TTL
loads).
8 input, 8 output for each channel. +5 VDC, +12 VDC, -12 VDC, and GND are also provided
for each channel. Over l00K bytes/second. Optional. Has 34-pin female connector and 34-line
ribbon cable. No connector is at the other end, allowing user to configure as required. Must be ordered separately.
If you are using the USARTs on the board as sources of interrupts, you cannot use the output side of Parallel O1annel A for normal parallel output.
Interrupts can be generated fram any combinaton of
the 3 USART RxRDY's, 3 TxRDY' s, and a 55 Hz real time clock. Jumper pads provided. None prewired.
Output to parallel channel A selects (masks) interrupt
sources previously wired in. Dummy input from Parallel Channelaresets 55 Hz real
t~e clock interrupt line during an interrupt service
routine. However, Parallel Channel B can be used for normal input (and output) as well.
Can use 8080, 280 Mode 0, 280 r~de I, or 280 Mode 2
A Bitstreamer II board can generate one of 9 possible
bytes in response to an interrupt, including
three of the restart instructions for usewith 8080 and Z80 Mode 0 interrupts. Software polls to
determine which possible source on a Bi tstreamer II
board is the actual source of the interrupt.
S-100 interrupt bus Pads are provided for jumpering interrupt sources to
the S-100 VI lines. +8 Vdc@720 mA typical.
+16 Vdc@30
IDA
typical.
-16 Vdc@30 IDA typical.
The Vector Graphic Bi tstreamer II Board is an all-purpose input/output
board for S-l~~ systems. It offers three serial I/O channels and 2 8-bit
parallel input/output channels for interfacing with multiple peripheral
devices such as printers, modems, and terminals. It also offers a 55 Hz
real-time clock which can interrupt the CPU for functions such as sharing of the CPU by several users or peripherals.
We will use the term "channel" rather than "port" to avoid confusion
causedbythe fact that each serial channel makes use of two I/O addresses, which are often called I/O "ports."
The CPU sends data to the serial and parallel charmels via I/O addresses.
The I/O addresses used by the board can be changed as a group. The board
uses the eight I/O address x2 to x9 (in hexadecimal notation), where x is
any dig it from 0 to 7. You specify the value of x
by
jumper, as listed in Table 1 in Section 2.1. Table 2 in Section 2.1" lists the function of each of the eight I/O addresses, which are fixed relative to one another.
'!heBitstreamer II Board does not come wi th any software for specific
applications, though Vector Graphic supplies certain items of software that
make use of its featues.
The three serial channels center around three industry standard 8251
USART (Universal Synchronous/Asynchronous Receiver!Transmitter) chips. Much
of the flexibility of the Bitstreamer II board derives from the flexibility of these chips, which can be modified via software. You, through software, can control the rate of transmission, and the format of the transmitted data. Data is transmitted as ASCII code having bet'II'Ieen5 and 8 bits per character, with an optional added-on pari ty bi t (choice of even or odd), and with one start bit and a choice of one, one and a half, or two stop bits per character. Further, using the 825l's, the board can handle either asynchronous or synchronous comm.mication. Each serial channel is entirely
independent of the others. Baud rates, format, handshaking, and whether comnunication is asynchronous or synChronous, is specified independently for each serial channel through software and in some cases hardware modifications.
It is not within the scope of this manual to detail the functioning of the 8251 USART chip, nor to teach the theory of serial communication. In order to write your own communications software or to modify the Bitstreamer
II serial channels, you will need to be thoroughly familiar 'IIith this ch ip. You can refer to Intel's App1 ication Note #16, entitled "Using The 8251 Universal SynchronOUS/Asynchronous Receiver/Transmitter," which Intel will
provide. This Note is also an excellent reference on basic communications.
theory. More readily available references on the
8251,
but ones that have
less to say about communication theory, are the "INTEL
8080
Microcomputer
Systems User's Manual," available either from Intel or most canputer retail
stores, and Adam Osborne's IIAnIntroduction to Microcomputers, Volume II -
Some Real Products,1I also available in many computer stores.
1.3 serial
asynchronous
coommication
Separately for each serial channel, you can select the rate of
transmission and reception from a choice of
110, 150, 300, 600, 1200, 2400,
4800,
or 9600 bits/second. You choose the rate using small dip-switches on
the board.
If you are writing custom software, there is in addition a simple way in
software to divide the chosen rate of a desired channel by 4, allowing some
control of the rate without physically opening up the computer. For
example, if you have a modem that is swi tch selectable for either
1200
bits/second or 300 bits/second, you can write a program that enables the operator usi1'l3the keyboard to change the computer's rate of commun ication to match that of the roodem at any given time.
Separately for each serial channel, you can select via software the
number of data bits in each ASCII character, selecting either 5, 6, 7, or 8. You can also select the number of stop bits in each character, selecting
either 1, 1 1/2, or 2. Finally, you can select whether or not a parity bit
is included for each character, and if chosen, whether or not it is even or odd parity. For how to do this in software, see the references given earlier for the
8251
USART.
You can enable one or more serial channels to communicate in synchronous
mode. Modifications to the board will be required to accompl ish this. In
brief, the
8251
SYNDET pin and the TxC and RxC clock pins must be connected
to the outside world, which is not the case in the standard configuration of the board.
Once set up for synchronous comnunication, you can select separately for each such channel the rate of communication, by using an external clock between" and 56K bits/second. As with asynchronous comrrunication, you can
select via software the character length, selecting either 5, 6, 7, or 8
bits. You can also select via software whether or not a parity bit is included for each character, and if chosen, whether or not it is even or odd
parity. Also via software, you can select separately for each channel wheG~er you are using internal or external synchronization, and whether one or
t~
synch characters are used.
Interrupts can be generated from each of the three 8251 RxRDY pins, and
each of the three 8251 TxRDY pins. You can choose to generate interrupts
from one or any combination of these six signals. Jumper pads are provided
for wiring up the interrupt capability for each of these signals, as
described in Section 2.7.
The board requires that you specify in software which of the signals so wired are to actually generate interrupts. This enables you to wire up several of them, and then to dynamically control which ones generate interrupts at any given time. This procedure is called "interrupt masking" and uses an I/O address known as the "interrupt masking register.
n
For example, assume you are creating a software routine that outputs a
character to an 8251 whenever that 8251 is ready to transmit it, but you do not want to poll the 8251 to determine when it is ready. Assume instead
that you want to arrange for the 8251 to interrupt some other routine
whenever the 8251 is ready to transmit. To do this, you would connect the TxRDY pin of that 8251 to the interrupt line, as described in Section 2.7. Now, as soon as you receive an interrupt, your software will branch to an
interrupt service routine which transmits a character. When it is finished transmitting a character, you do not want to re-enable interrupts until you
are ready to transmit the next character, because otherwise, the 8251 will
tie up the CPU with TxRDY interrupts. The problem is that you do not want
to leave interrupts disabled because you want other peripherals such as the keyboard to be able to interrupt. The way you solve this is to enable interrupts, but also mask out the TxRDY interrupt using the interrupt
masking register until software is ready to transmit another character.
You must use the interrupt masking register whenever you are using the
8251's to generate interrupts. Even if you do not want to disable some of the interrupt sources, you must enable them at the outset by initializing
the interrupt masking register appropriately.
The interrupt masking register is the output side of Parallel Channel A
on the Bitstreamer II Board. The parallel channels are discussed later in
Perspective. The precise way that the interrupt masking register is used
by software is discussed in Section 2.7. If you are using the 8251's as interrupt sources, you cannot use the output side of Parallel Channel A for
any other purpose.
This manual cannot
describe the
RS-232C protocol in detail. For a full
description, obtain a copy of the RS-232C E~ STANDARD document, published by Electonic Industries Association, Engineering Department, 2001 Eye
Street, N.W., Washington, D.C. 20006. Alternately, if you have access to Data Pro or Auerbach reports on communications, they contain thorough articles describing the protocol and its implications. The following
information, however, will be of bronediaterelevence in this manual:
An RS-232C signal can either be POSITIVE (+12 Vdc) or NEGATIVE (-12 Vdc)
Positive is ON or SPACING, Negative is OFF or MARKING. RS-232C line drivers typically invert these signals when they are converted to and from TTL
signals. Hence, RS-232C POSITIVE corresponds to
TIL
low (aboutaVdc) arid RS-232C NffiATIVE corres~nds to TTL high (about 5 Vdc). (TTL is the kind of signal used within the computer.)
An RS-232C cable consists of 25 lines. An RS-232C transmit or receive data line carries a serial sequence of POSITIVE and NEGATIVE pulses that correspond with the characters you want to transmit or receive. There is also associated formating and parity information attached to the information
by
the communication device such as an 8251. In addition to the transmit and receive data lines, there are ground lines, (lines 1 and 7), and there are handshaking lines that are used
by
communication, terminal, and computer equipment to inform each other of their status (lines 4, 5, 6, 8, 20, 22, and a few others that are rarely used). The full RS-232C protocol also
specifies a set of rarely used "secondary" lines which have the same
definitions as some of the primary lines, but carry an independent set of
signals. Altogether there are 25 RS-232C lines defined, but most
applications use only a few of them.
In the real ~rld, very few devices require "full RS-232C" protocol. In
fact, very few devices even require all of the handshaking lines mentioned
above. Many require one or even none. Further, many devices use
handshaking lines differently than defined by RS-232C, violating the
protocol. In short, it is confusing at this time to say that a given device
requires "full RS-232C." You must specify exactly what signals it sends and
expects to receive on each line.
It is important to understand that most of the RS-232C lines are
directional, that is, the protocol specifies which direction the signal
travels on each line, relative to the ends of the cable. Therefore, the protocol specifies that at one end of an RS-232C cable there must be a
device of the type called "Data Communications Equi?ffient", or "DCE
1
'
for
short, and at the other end there must be a device of the type "Data
Terminal Equifffient,or "OTE" for short. The direction of the signal on a
given line can be determined once you decide which end of your cable has
which kind of device.
The tenus Data Communication Equipment and Data Tenuinal Equipment derive
from the original purpose for RS-232C - to connect a terminal with a
communication device such as a modem. A computer does not have to be
involved at all. Since a computer can either play the part of a terminal, when connected to a modem, or it can play the part of communication equipment, when connected to a terminal, a computer serial channel can be
used either as DeE or DTE. However, a given serial channel can only be wired up as one or the other at anyone time. If the channel happens to be wired up to look like CCE, and you want to connect it to another CCE such as a rrodem, then the RS-232C connection will not wo rk. Both ends would be
transmi tting on the same lines and receiving on the same lines. Before tI1e
RS-232C connection can be made, in this case, you must rewire the computer's
serial channel so that it receives and transnits on the lines specified for
I1I'E.
The Bitstreamer II Board is shipped with one RS-232C Serial I/O Cable.
To enable one of the serial channels to communicate over an RS-232C line,
you will connect one end of this line to one of the three serial channel sockets on the board, and the other end, having an RS-232C standard DB-25
female connector, to the back panel of the computer. The cable is designed
so that appropriate signals from the board are directed to the RS-232C lines
at the D8-25 connector as if it were Data Communications Equipment. Thus,
the resulting 08-25 socket at the rear of the computer is a DCE RS-232C
~. channel.
I
Additional 8itstreamer II Serial I/O Cables are available from Vector
Graphic for the second and third serial channels on the board.
Drivers are provided for each serial channel to enable the 8251 Transmit
Data and Receive Data lines to input or output at RS-232C voltage levels.
These receivers and drivers are already connected on the board, requiring no
jumpering. When a serial I/O cable is installed for a given serial channel, these signals are connected to RS-232C lines 3 and 2 respectively.
In addition, for each of the 825l's, three of ~~e RS-232C control lines
are pulled up to +12V (lines 5,
6,
and 8). This is the ON state in RS-232C.
(Normally, this will ENABLE equipment that requires such a signal.) When a
serial I/O cable is installed for a given channel, these signals are
available on the cable's 06-25. These signals are always ON if the board is
used without modification. However, you can install jumpers and RS-232C line drivers to enable the 8251 to dynamically control any t'NO of them via software.
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