V-Data VDS6632A4A-6, VDS6632A4A-5, VDS6632A4A-5.5 Datasheet
V-Data VDS6632A4A
A
1
234
5
6
7
8
9
8
6
8
5
8
4
8
3
8
2
8
1
8
0
797
8
6
6
6
5
6
4
6
3
6
2
6
1
6
0
5
9
5
8
1
0
1
1
1
2
1
3
141
5
1
6
1
7
1
8
1
9
2
0
7
7
7
6
7
5
7
4
73727
1
7
0
6
9
6
8
6
7
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
9
4
0
414
2
4
3
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
464
5
4
4
Synchronous DRAM 512K x 32 Bit x 4 Banks
General Description
The VDS6632A4A are four-bank Synchronous
DRAMs organized as 524,288 words x 32 bits x 4
banks,
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clock cycle.
Range of operating frequencies, programmable
burst length and programmable latencies allow the
same device to be useful for a variety of high
bandwidth high performance memory system
applications
Ordering Information.
Part No. Frequency Interface Package
VDS6632A4A-5 200Mhz LVTTL 400mil 86pin TSOPII
Features
•JEDEC standard LVTTL 3.3V power supply
•MRS Cycle with address key programs
-CAS Latency (2 & 3)
-Burst Length (1,2,3,8,& full page)
-Burst Type (sequential & Interleave)
•4 banks operation
ll inputs are sampled at the positive edge of
•
the system clock
•Burst Read single write operation
•Auto & Self refresh
•4096 refresh cycle
•DQM for masking
•Package:86-pins 400 mil TSOP-Type II
VDS6632A4A-5.5 183Mhz LVTTL 400mil 86pin TSOPII
VDS6632A4A-6 166Mhz LVTTL 400mil 86pin TSOPII
Pin Assignment
DD
V
DQ0
DDQ
V
DQ1
DQ2
SSQ
V
DQ3
DQ4
V
DDQ
DQ5
DQ6
SSQ
V
DQ7
NC
V
DQM0
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
DQM2
DD
V
NC
DQ16
SSQ
V
DQ17
DQ18
V
DDQ
DQ19
DQ20
SSQ
V
DQ21
DQ22
DDQ
V
DQ23
V
DD
DD
SS
V
DQ15
SSQ
V
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
DDQ
V
DQ8
NC
SS
V
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
SS
V
NC
DQ31
DDQ
V
DQ30
DQ29
V
SSQ
DQ28
DQ27
V
DDQ
DQ26
DQ25
SSQ
V
DQ24
SS
V
86-pin plastic TSOP II 400mil
Rev 1.0 April, 2001
1
V-Data VDS6632A4A
Pin Description
PIN NAME FUNCTION
CLK System Clock Active on the positive edge to sample all inputs.
CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least on cycle prior new command. Disable input
buffers for power down in standby
/CS Chip Select Disables or Enables device operation by masking or enabling all input
except CLK, CKE and DQM0 ~ DQM3
A0~A11 Address Row / Column address are multiplexed on the same pins.
Row address : RA0~RA10
Column address : CA0~CA7
BA0~BA1 Banks Select Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
DQ0~DQ31 Data Data inputs / outputs are multiplexed on the same pins.
DQM0~3 Data Mask Makes data output Hi-Z,
/RAS Row Address Strobe Latches row addresses on the positive edge of the CLK with /RAS low
/CAS Column Address Strobe Latches Column addresses on the positive edge of the CLK with /CAS low
/WE Write Enable Enables write operation and row recharge.
VDD/VSS Power Supply/Ground Power and Ground for the input buffers and the core logic.
VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers.
NC No Connection This pin is recommended to be left No Connection on the device.
Block Diagram
CLK
CKE
Address
Clock
Generator
Mode
Register
Address
Buffer
&
Refresh
Counter
Decoder
Row
Bank3
Bank2
Bank1
Bank0
/CS
/RAS
/CAS
/WE
Rev 1.0 April, 2001
Decoder
Command
Logic
Control
Column
Address
Buffer
&
Refresh
Counter
Amplifier
ColumnDecoder
DataControlCircuit
Latch
Data
DQM
DQ
2
V-Data VDS6632A4A
Absolute Maximum Ratings
Parameter Symbol Value Unit
Voltage on any pin relative to Vss VIN, Vout -1.0 ~ 4.6 V
Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V
Storage temperature TSTG -55 ~ +150
Power dissipation PD 1 W
Short circuit current IOS 50 mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
℃
DC Operating Condition
Voltage referenced to Vss = 0V, TA = 0 to 70 ℃
Parameter Symbol Min Typ Max Unit Note
Supply voltage VDD, VDDQ 3.0 3.3 3.6 V
Input logic high voltage VIH 2.0 3.0 VDD+0.3 V 1
Input logic low voltage VIL -0.3 0 0.8 V 2
Output logic high voltage VOH 2.4 - - V IOH=-2mA
Output logic low voltage VOL - - 0.4 V IOL=2mA
Input leakage current IIL -5 - 5 uA 3
Output leakage current IOL -5 - 5 uA 4
Note : 1. VIH (max)=4.6V AC for pulse width ≦ 10ns acceptable.
2.V
3.Any input 0V ≦ V
4.Dout is disabled, 0V ≦ V
IL(min)=-1.5V AC for pulse width ≦ 10ns acceptable.
IN ≦ VDD + 0.3V, all other pins are not under test = 0V.
OUT ≦ VDD.
AC Operating Condition
Voltage referenced to Vss = 0V, TA = 0 to 70 ℃
Parameter Symbol Value Unit Note
AC input high / low level voltage VIH / VIL 2.4 / 0.4 V
Input timing measurement reference level voltage Vtrip 1.4 V
Input rise / fall time TR / tF 1 Ns
Output timing measurement reference level Voutfef 1.4 V
Output load capacitance for access time measurement CL 30 pF 2
Note: 1. 3.15V ≦ VDD ≦ 3.6V is applied for VDS6632A4A5.
2. Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF). For details,
refer to AC/DC output load circuit.
Rev 1.0 April, 2001
3
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