• ‘TOSHIBA’ T6963C flat pack or equivalent LCD controller.
• ‘TOSHIBA’ T6A39 flat pack or equivalent LCD segment drivers.
• ‘TOSHIBA’ T6A40 flat pack or equivalent LCD common drivers.
• 8 K byte display SRAM.
• Yellow-Green LED03 backlight.
• FPC connection.
2. Mechanical Specifications
The mechanical detail is shown in Fig. 1 and summarized in Table 1 below.
Table 1
Parameter Specifications Unit
Outline dimensions 180.0(W) x 65.0(H) x 14.0 MAX.(D) mm
Viewing area 132.0(W) x 39.0(H) mm
Active area 127.15(W) x 33.87(H) mm
Display format 240 (Horizontal) x 64 (Vertical) dots
Dot size 0.48(W) x 0.48(H) mm
Dot spacing 0.05(W) x 0.05(H) mm
Dot Pitch 0.53(W) x 0.53(H) mm
Weight TBD grams
VL-FS-MGLS24064-02C REV. A
(MGLS24064-G-LED03-6-SCH C)
NOV/2004
PAGE 5 OF 11
Figure 1: Module Specification
A
H
V
H
VL-FS-MGLS24064-02C REV. A
(MGLS24064-G-LED03-6-SCH C)
NOV/2004
PAGE 6 OF 11
3. Absolute Maximum Ratings
3.1 Electrical Maximum Ratings – for IC Only
Table 2
Parameter Symbol Min. Max. Unit
Supply voltage (Logic) VDD - VSS -0.3 +7.0 V
Supply voltage (LCD drive) VLCD=VDD – V0-0.3 +30.0 V
Input voltage Vin -0.3 VDD +0.3 V
Note:
The modules may be destroyed if they are used beyond the absolute maximum ratings.
All voltage values are referenced to VSS = 0V.
3.2 Environmental Condition
Item
Operating
Temperature
(Topr)
Min. Max. Min. Max.
mbient Temperature
umidity
0°C +50°C-10°C +60°C
95% max. RH for Ta ≤ 40°C
< 95% RH for Ta > 40°C
ibration (IEC 68-2-6)
cells must be mounted
on a suitable connector
Shock (IEC 68-2-27)
alf-sine pulse shape
Frequency: 10 ∼ 55 Hz
Amplitude: 0.75 mm
Duration: 20 cycles in each direction.
Pulse duration : 11 ms
Peak acceleration: 981 m/s2 = 100g
Number of shocks : 3 shocks in 3
mutually perpendicular axes.
Table 3
Storage
Temperature
(Tstg)
Remark
Dry
no condensation
3 directions
3 directions
VL-FS-MGLS24064-02C REV. A
(MGLS24064-G-LED03-6-SCH C)
NOV/2004
PAGE 7 OF 11
4. Electrical Specifications
4.1 Interface signals
Table 4
Pin No. Symbol Description
1 FG Frame Ground (see note 1)
2 VSS Ground
3 VDD Power supply for logic (+5V)
4 V0 Power supply for LCD drive
5 /WR Data write. Write data to controller T6963C when “L”
6 /RD Data read. Read data from controller T6963C when “L”
7 /CE Chip enable of controller when “L”
8 __
C/D
Command/Data read /write.
“H” for command read/write and
“L” for data read/write.
9 NC No connection.
10 /RST Controller reset when “L”
11 DB0 Data input/output (LSB)
12 DB1 Data input/output
13 DB2 Data input/output
14 DB3 Data input/output
15 DB4 Data input/output
16 DB5 Data input/output
17 DB6 Data input/output
18 DB7 Data input/output (MSB)
19 FS Font select. “H” for 6 x 8 font & “L” for 8 x 8 font
20 NC No connection.
Note 1: This pin is electrically connected to the metal bezel (frame).
User can choose to connect this pin to VSS or leave it open.
VL-FS-MGLS24064-02C REV. A
(MGLS24064-G-LED03-6-SCH C)
NOV/2004
PAGE 8 OF 11
4.2 Typical Electrical Characteristics
At Ta = 25 °C, VDD = 5V±5%, VSS = 0V.
Table 5
Parameter Symbol Conditions Min. Typ. Max. Unit
Supply voltage
VDD –VSS 4.75 5.00 5.25 V
(Logic)
Supply voltage
(LCD)
VLCD
=VDD –V0
VDD = 5V,Note 1 14.3 14.8 15.3 V
Input signal voltage VIN “H” level VDD -2.2- VDD V
“L” level 0 - 0.8 V
(Logic & LCD)
IDD
Character mode,
VDD=5V, Note 1
Checkerboard
- 8.9 13.3 mASupply Current
- 9.4 14.1 mA
mode,
VDD=5V, Note 1
(LCD)
I0
Character mode,
VDD=5V, Note 1
Checkerboard
- 3.4 5.0 mASupply Current
- 3.5 5.2 mA
mode,
VDD=5V, Note 1
Supply voltage of
yellow-green
LED03 backlight
VLED Forward current
4.0 4.1 4.2 V
=220mA
Number of LED
dice=2x22=44dies
Note 1: There is tolerance in optimum LCD driving voltage during production and it will be
within the specified range.
VL-FS-MGLS24064-02C REV. A
(MGLS24064-G-LED03-6-SCH C)
NOV/2004
PAGE 9 OF 11
4.3 Timing Specifications
At Ta = 0°C T o +50°C, VDD = 5V±5%,VSS=0V
Refer to Fig. 2, the bus timing diagram.
Table 6
Parameter Symbol Min. Max. Unit
t
C/D Set-up time
C/D Hold Time
CE_,RD,WR_ Pulse Width
Data Set-up Time
Data Hold Time
Access Time
Output Hold Time
tCE, tRD, t
CDS
t
CDH
tDS
tDH
t
ACC
tOH
WR
100 - ns
10 - ns
80 - ns
80 - ns
40 - ns
- 150 ns
10 50 ns
C / D
CE
RD. WR
D0~D7
(WRITE)
t CDS
t CE.t RD.t WR
t CDH
t DS
t DH
D0~D7
(READ)
t ACC
t OH
Figure 2: Bus Timing Diagram
VL-FS-MGLS24064-02C REV. A
(MGLS24064-G-LED03-6-SCH C)
NOV/2004
PAGE 10 OF 11
4.4 Timing Diagram of VDD Against V0.
Power on sequence shall meet the requirement of Figure 3, the timing diagram of VDD against V0.
VDD
95%
LOGIC SUPPLY
VOLTAGE
0V
50ms(typical)
LCD SUPPLY
VOLTAGE
0V
V0
Figure 3: Timing Diagram of VDD Against V0.
VL-FS-MGLS24064-02C REV. A
(MGLS24064-G-LED03-6-SCH C)
NOV/2004
PAGE 11 OF 11
5. LCD Cosmetic Conditions
a.) Reference document follow VL-QUA-012A.
b.) LCD size of the product is middle.
6. Remark:
a.) Identification labels will be stuck on the module without obstructing the viewing area of display.
b.) Varitronix does not responsible for any polarizer defect after the protective film has been
removed from the display.
c.) The stiffener on FPC/FFC/COF must not be bent during or after assembly.
“Varitronix Limited reserves the right to change this specification.”