VL-FS-MDLS16268CSP-04 REV. A
(MDLS16268CSP-LV-G-LED04G (BB))
JAN./2002
PAGE 2 OF 12
DOCUMENT REVISION HISTORY 1:
DOCUMENT
REVISION
DATE DESCRIPTION CHANGED
BY
CHECKED
BY
FROM TO
A
2002.01.08 First Release
(Based on the test specification
VL-TS-MDLS16268CSP-04, REV. A,
2001.03.01)
PHILIP
CHENG
TOM LEE
VL-FS-MDLS16268CSP-04 REV. A
(MDLS16268CSP-LV-G-LED04G (BB))
JAN./2002
PAGE 3 OF 12
CONTENTS
Page No.
1. GENERAL DESCRIPTION 4
2. MECHANICAL SPECIFICATIONS 4
3. ABSOLUTE MAXIMUM RATINGS 6
3.1
3.2 ENVIRONMENTAL CONDITION 6
4. ELECTRICAL SPECIFICATIONS 7
4.1 INTERFACE SIGNALS 7
4.2 TYPICAL ELECTRICAL CHARACTERISTICS 8
4.3 TIMING SPECIFICATIONS 9
4.4 TIMING DIAGRAM OF VCC AGAINST V0 11
5. CORRESPONDENCE BETWEEN CHARACTER CODES AND
ELECTRICAL MAXIMUM RATINGS (Ta=25°C)
CHARACTER PATTERNS (ROM CODE: 01)
6
12
VL-FS-MDLS16268CSP-04 REV. A
(MDLS16268CSP-LV-G-LED04G (BB))
JAN./2002
PAGE 4 OF 12
VARITRONIX LIMITED
Specification
of
LCD Module Type
Item No.: MDLS16268CSP-04
1. General Description
• 16 characters (5 x 8 dots) x 2 lines STN Positive Yellow Transflective LCD Character Module.
• Viewing Angle: 6 o’clock direction.
• Driving duty: 1/16 duty, 1/5 bias.
• ‘SUNPLUS’ SPLC780A1-01-C(Die form) LCD Controller/Driver or equivalent.
• ‘SUNPLUS’ SPLC100A2-C(Die form ) Segment/Common LCD Driver.
• Yellow-green LED04 backlight.
2. Mechanical Specifications
The mechanical detail is shown in Fig. 1 and summarized in Table 1 below.
Table 1
Parameter Specifications Unit
Outline dimensions 122.0(W) x 44.0(H) x 15.0 MAX.(D) mm
Effective viewing area 99.0(W) x 23.0(H) mm
Display format 16 characters x 2 lines Character size 4.84(W) x 9.22(H) (5 x 8 dots) mm
Character spacing 1.16(W) x 0.53(H) mm
Character pitch 6.00(W) x 9.75(H) mm
Dot size 0.92(W) x 1.10(H) mm
Dot spacing 0.06(W) x 0.06(H) mm
Dot pitch 0.98(W) x 1.16(H) mm
Weight: TBD grams
VL-FS-MDLS16268CSP-04 REV. A
(MDLS16268CSP-LV-G-LED04G (BB))
JAN./2002
PAGE 5 OF 12
Figure 1: Specification Drawing
A
H
V
H
VL-FS-MDLS16268CSP-04 REV. A
(MDLS16268CSP-LV-G-LED04G (BB))
JAN./2002
PAGE 6 OF 12
3. Absolute Maximum Ratings
3.1 Electrical Maximum Ratings(Ta = 25 ºC)
Table 2
Parameter Symbol Min. Max. Unit
Power Supply voltage (Logic) VCC - VSS -0.3 +7.0 V
Power Supply voltage
(LCD drive)
VLCD
=VCC – V0
-0.3 +12.0 V
Input voltage Vin -0.3 VCC+0.3 V
Note:
The modules may be destroyed if they are used beyond the absolute maximum ratings.
All voltage values are referenced to VSS = 0V.
3.2 Environmental Condition
Item
Operating
Temperature
(Topr)
Min. Max. Min. Max.
mbient Temperature
umidity
0°C +50°C -10°C +60°C
95% max. RH for Ta ≤ 40°C
< 95% RH for Ta > 40°C
ibration (IEC 68-2-6)
cells must be mounted
on a suitable connector
Shock (IEC 68-2-27)
alf-sine pulse shape
Frequency: 10 ∼ 55 Hz
Amplitude: 0.75 mm
Duration: 20 cycles in each direction.
Pulse duration : 11 ms
Peak acceleration: 981 m/s2 = 100g
Number of shocks : 3 shocks in 3
mutually perpendicular axes.
Table 3
Storage
Temperature
(Tstg)
Remark
Dry
no condensation
3 directions
3 directions
VL-FS-MDLS16268CSP-04 REV. A
(MDLS16268CSP-LV-G-LED04G (BB))
JAN./2002
PAGE 7 OF 12
4. Electrical Specifications
4.1 Interface signals
Table 4
Pin No. Symbol Description
1 VSS Ground (0V).
2 VCC Power supply for logic (+5.0V)
3 V0 LCD driving voltage.
4 RS Register Select Input:
”High’ for Data register (for read and write)
”Low” for Instruction register (for write),
Busy flag, address counter (for read)
5 R/W Read/Write signal:
‘High’ for Read mode.
‘Low’ for Write mode.
6 E Enable.
Start signal for data read /write.
7 DB0 Data input/output (LSB)
8 DB1 Data input/output
9 DB2 Data input/output
10 DB3 Data input/output
11 DB4 Data input/output
12 DB5 Data input/output
13 DB6 Data input/output
14 DB7 Data input/output (MSB)
15 LED(+) Anode of LED Backlight.
16 LED(-) Cathode of LED Backlight .
VL-FS-MDLS16268CSP-04 REV. A
(MDLS16268CSP-LV-G-LED04G (BB))
JAN./2002
PAGE 8 OF 12
4.2 Typical Electrical Characteristics
At Ta = 25 °C, VCC = 5V±5%, VSS=0V.
Table 5
Parameter Symbol Conditions Min. Typ. Max. Unit
Supply voltage (Logic) VCC -VSS 4.75 5.0 5.25 V
Supply voltage (LCD) VLCD
=VCC –V0
V
”H” level 2.2 - VCC V Input signal voltage 1
IH1
for E,DB0-DB7,R/W,RS.
for OSC1.
V
” L” level -0.3 - 0.6 V
IL1
V
” H” level VCC –1 - VCC V Input signal voltage 2
IH2
V
” L” level -0.2 - 1.0 V
IL2
ICC
(Logic & LCD)
VCC = 5V,
Note 1.
Character
mode
4.75 5.0 5.25 V
- 1.75 2.25 mA Supply current
Checker mode - 1.8 2.7 mA
Character
- 0.5 0.75 µA Supply current (LCD) I0
mode, note 1
Checker mode,
- 0.5 0.75 µA
Note 1
Supply Voltage of
yellow-green LED04
backlight
VLED04 Forward
current
=315mA.
3.9 4.1 4.3 V
Number of
LED chips
=2x21
=42.
Note (1) : There is tolerance in optimum LCD driving voltage during production and it will be
within the specified range.
VL-FS-MDLS16268CSP-04 REV. A
(MDLS16268CSP-LV-G-LED04G (BB))
JAN./2002
PAGE 9 OF 12
4.3 Timing Specifications
At Ta = 0 °C to +50 °C , VCC = 5V±5% ,VSS = 0V.
Refer to Fig. 2, the bus timing diagram for write mode (Writing data from MPU to SPLC780A1).
Table 6
Parameter Symbol Min. Max. Unit Test Condition
E cycle time tC 400 - ns
E
E pulse width tPW 150 - ns
E rise time tR - 25 ns
E fall time tF - 25 ns
Address set-up time) t
Address hold time t
Data set-up time t
Data hold time t
30 - ns
SP1
10 - ns
HD1
40 - ns
SP2
10 - ns
HD2
RS, R/W, E
DB0~DB7
Refer to Fig. 3, the bus timing diagram for read mode (Reading data from SPLC780A1 to MPU).
Table 7
Parameter Symbol Min. Max. Unit Test Condition
E cycle time tC 400 - ns
E
E pulse width tPW 150 - ns
E rise time tR - 25 ns
E fall time tF - 25 ns
Address set-up time t
Address hold time t
Data output delay time tD - 100 ns
Data hold time t
30 - ns
SP1
10 - ns
HD1
20 - ns
HD2
RS, R/W, E
DB0~DB7
VL-FS-MDLS16268CSP-04 REV. A
(MDLS16268CSP-LV-G-LED04G (BB))
JAN./2002
PAGE 10 OF 12
Figure 2: Bus timing diagram for write mode (Writing data from MPU to SPLC780A1).
Figure 3: Bus timing diagram for read mode (Reading data from SPLC780A1 to MPU).
VL-FS-MDLS16268CSP-04 REV. A
(MDLS16268CSP-LV-G-LED04G (BB))
JAN./2002
PAGE 11 OF 12
4.4 Timing Diagram of VCC Against V0.
Power on sequence shall meet the requirement of Figure 4, the timing diagram of VCC against V0.
VDD
95%
LOGIC SUPPLY
VOLTAGE
0V
50ms(typical)
LCD SUPPLY
OV
VOLTAGE
V0
Figure 4: Timing Diagram of VCC Against V0.
VL-FS-MDLS16268CSP-04 REV. A
(MDLS16268CSP-LV-G-LED04G (BB))
JAN./2002
PAGE 12 OF 12
5. Correspondence between Character Codes and Character Patterns (ROM Code: 01)
“Varitronix Limited reserves the right to change this specification.”
FAX:(852) 2343-9555.
- END -
Loading...