The mechanical detail is shown in Fig. 1 and summarized in Table 1 below.
Table 1
Parameter Specifications Unit
Outline dimensions 78.0(W) x 70.0(H) x 13.5 MAX. (D) mm
Viewing area 62.0(W) x 44.0(H) mm
Active area 56.27(W) x 38.35(H) mm
Display format 128(Horizontal) x 64(Vertical) dots
Dot size 0.39(W) x 0.55(H) mm
Dot spacing 0.05(W) x 0.05(H) mm
Dot pitch 0.44(W) x 0.60(H) mm
Weight TBD grams
VL-FS-MGLS12864TZ-10 REV. A
(MGLS12864TZ-HT-LED03 )
JUN/2004
PAGE 5 OF 12
Figure 1(a): Module Specification 1
VL-FS-MGLS12864TZ-10 REV. A
(MGLS12864TZ-HT-LED03 )
JUN/2004
PAGE 6 OF 12
Figure 1(b): Module Specification 2
VL-FS-MGLS12864TZ-10 REV. A
(MGLS12864TZ-HT-LED03 )
JUN/2004
PAGE 7 OF 12
3. Interface signals
Table 2
Pin No. Symbol Description
1 FG Frame ground (see note 1).
2 VSS Ground (0V).
3 VDD Power supply for logic (+5V).
4 V0 Power supply for LCD drive.
5 /WR Data write. Write data to controller T6963C when “L”.
6 /RD Data read. Read data from controller T6963C when “L”.
7 /CE Chip enable for T6963C.
/CE must be “Low” when CPU communicates with T6963C.
/RD = “Low” ….. C/D=”High”: Status Read C/D=”Low”: Data Read.
9 /RST “High”: Normal (T6963C has internal pull-up resistor).
“Low”: Initialize T6963C. Text and graphic have addresses and text and
graphic area settings are retained.
10 DB0 Data input/output (LSB).
11 DB1 Data input/output.
12 DB2 Data input/output.
13 DB3 Data input/output.
14 DB4 Data input/output.
15 DB5 Data input/output.
16 DB6 Data input/output.
17 DB7 Data input/output (MSB).
18 FS
Font select.
“H” for 6 x 8 font &
“L” for 8 x 8 font
19 LED+ Anode of LED backlight
20 LED- Cathode of LED backlight
Note 1: This pin is electrically connected to the metal bezel (frame).
User can choose to connect this pin to VSS or leave it open.
A
H
V
H
VL-FS-MGLS12864TZ-10 REV. A
(MGLS12864TZ-HT-LED03 )
JUN/2004
PAGE 8 OF 12
4. Absolute Maximum Ratings
4.1 Electrical Maximum Ratings (Ta = 25 ºC)
Table 3
Parameter Symbol Min. Max. Unit
Supply voltage (Logic) VDD - VSS -0.3 +7.0 V
Supply voltage (LCD drive) VLCD=VDD – V0 0 +30.0 V
Input voltage Vin -0.3 VDD +3.0 V
Note:
The modules may be destroyed if they are used beyond the absolute maximum ratings.
All voltage values are referenced to VSS = 0V.
4.2 Environmental Condition
Table 4
Item
Operating
Temperature
(Topr)
Storage
Temperature
(Tstg)
Remark
Min. Max. Min. Max.
mbient Temperature
umidity
-20°C +70°C -30°C +80°C
95% max. RH for Ta ≤ 40°C
Dry
no condensation
< 95% RH for Ta > 40°C
ibration (IEC 68-2-6)
cells must be mounted
on a suitable connector
Shock (IEC 68-2-27)
alf-sine pulse shape
Frequency: 10 ∼ 55 Hz
Amplitude: 0.75 mm
Duration: 20 cycles in each direction.
Pulse duration: 11 ms
Peak acceleration: 981 m/s2 = 100g
3 directions
3 directions
Number of shocks: 3 shocks in 3
mutually perpendicular axes.
VL-FS-MGLS12864TZ-10 REV. A
(MGLS12864TZ-HT-LED03 )
JUN/2004
PAGE 9 OF 12
5. Electrical Specifications
5.1 Typical Electrical Characteristics
At Ta = 25 °C, VDD = 5V±5%,VSS = 0V.
Table 5
Parameter Symbol Conditions Min. Typ. Max. Unit
Supply voltage
VDD-VSS 4.75 5.0 5.25 V
(Logic)
Supply voltage
(LCD)
VLCD
=VDD-V0
VDD = 5V,
Note (1)
15.5 16.0 16.5 V
“H” level VDD-2.2 - VDD V Input signal voltage VIN
“L” level 0 - 0.8 V
(Logic & LCD)
IDD
Character mode,
VDD = 5V. Note (1)
Checker board mode,
- 7.3 11.0 mA Supply current
- 7.5 11.3 mA
VDD = 5V. Note (1)
(LCD)
I0
Character mode,
Note (1)
Checker board mode,
- 3.4 5.1 mA Supply Current
- 3.4 5.1 mA
Note (1)
Supply current of
yellow-green LED03
backlight
VLED03 Forward current
=100mA
No. of LED chips
3.8 4.0 4.2 V
=20.
Note (1): There is tolerance in optimum LCD driving voltage during production and it will be
within the specified range.
VL-FS-MGLS12864TZ-10 REV. A
(MGLS12864TZ-HT-LED03 )
JUN/2004
PAGE 10 OF 12
5.2 Timing Specifications
At Ta = -20°C To +70°C, VDD = 5V±5%, VSS=0V
Refer to Fig. 3, the bus timing diagram.
Table 6
Parameter Symbol Min. Max. Unit
t
C/D Set-up time
C/D Hold Time
/CE,/RD,/WR Pulse
tCE, tRD, tWR
CDS
t
CDH
100 - ns
10 - ns
80 - ns
Width
Data Set-up Time
Data Hold Time
Access Time
Output Hold Time
tDS
tDH
t
ACC
tOH
80 - ns
40 - ns
- 150 ns
10 50 ns
Figure 2: Bus Timing Diagram
5.3 Timing Diagram of VDD Against V0.
Power on sequence shall meet the requirement of Figure 4, the timing diagram of VDD against V0.
VL-FS-MGLS12864TZ-10 REV. A
(MGLS12864TZ-HT-LED03 )
JUN/2004
PAGE 11 OF 12
VDD
95%
LOGIC SUPPLY
VOLTAGE
LCD SUPPLY
VOLTAGE
0V
50ms(typical)
0V
V0
Figure 3: Timing Diagram of VDD Against V0.
VL-FS-MGLS12864TZ-10 REV. A
(MGLS12864TZ-HT-LED03 )
JUN/2004
PAGE 12 OF 12
6.0 LCD Cosmetic Conditions.
Refer to VL-QUA-012A.
Remark: LCD size of the product is small.
“Varitronix Limited reserves the right to change this specification.”
FAX:(852) 2343-9555.
URL:http: //www.varitronix.com
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